JPH01302750A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration by a method wherein a via hole is opened wider than the width of an aluminum wiring, the gap between the aperture part and the first layer aluminum wiring is filled up and flattened with an organic insulating film, with the necessity of widening the width of the wiring for the via hole is eliminated. CONSTITUTION:A via hole opened part is provided using a photolithographic technique. A polyimide resin film 8 is coated on a silicon substrate, and the film 8 is converted into an imide by heating. The head part of the first layer of metal wiring, namely, a tungsten film 7, is exposed by etching back the whole surface of a wafer. A second layer of aluminum wiring 5 is formed. The wiring 5 is formed by conducting anisotropic plasma etching using the gas mainly composed of CCl4. At this time, as the polyimide film 8 appears on the under layer at the point of time when the etching on the wiring 5 is finished, the generation of an under-cut and a side etching can be prevented. As a result, the widening of the wiring width for a via hole is unnecessitated, and the degree of integration can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure of multilayer wiring.

[Conventional technology]

Conventionally, in a multilayer wiring structure of a semiconductor device, a pier hole for establishing conduction between a -th layer metal wiring and a second layer metal wiring has a diameter smaller than the width of the first layer metal wiring. In other words, the wiring portion corresponding to the peer hole had to be made wider.

[Problem to be solved by the invention]

The above-described conventional method for forming peer holes has been a major obstacle to increasing the degree of integration in multilayer wiring of semiconductor integrated circuits.

FIG. 3 shows a conventional method for forming a pier hole.

A first layer of aluminum wiring 3 of about 1.0 μm is formed on a silicon oxide film 1 on a silicon substrate (not shown) by DC magnetron sputtering, and a photoresist is used as a mask using a gas mainly composed of OCA'4. Dry etching.

Next, the silicon nitride film 2 as an interlayer insulating film is coated with plasma C.
According to the VD method') N2. 350 NHs and SiH4 gas
℃ to form about 1.0 μm (Figure 3 (a))
.

Using the photoresist 4 as a mask, dry etching is performed with CF 4 + 02 gas to form a peer hole.

(Figure 3 (b)) A second layer of aluminum is formed to a thickness of 1.0 μm by DC magnetron sputtering, and dry etching is performed with a gas containing CCβ4 as a main component using a photoresist as a mask to form a second layer of aluminum wiring 5. do.

(FIG. 3(C)) In this method, as shown in FIG. 3(d), the width of the aluminum wiring must be widened at the portion where the peer hole is located, which is a major obstacle to high integration.

[Means to solve the problem]

The semiconductor device of the present invention has a pier hole which is wider than the width of the metal wiring in the first layer, and a second metal wiring which is resistant to an etchant for forming the metal wiring in the second layer is provided on the surface of the eleventh metal wiring. It is characterized by having a metal layer formed thereon.

Furthermore, a feature is that the gap between the peer hole and the first layer metal wiring is filled with an organic insulating film or spin-on glass.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a manufacturing sectional view illustrating an embodiment of the present invention.

Approximately 1 silicon oxide film 1 is deposited on a silicon substrate (not shown).
．． An aluminum film of about 1.0 μm is formed by DC magnetron sputtering, followed by a tungsten film of about 0.3 μm to form a laminated structure. After exposing and developing the photoresist using a normal photolithography technique, the tungsten film 7 is etched using a gas mainly composed of SF using the photoresist as a mask, and then aluminum 3 is etched using a gas mainly composed of CCβ4. Error 1-Fugu and form the first layer metal wiring.

A silicon nitride film is deposited as an interlayer insulating film on a silicon substrate.
It is formed to a thickness of approximately 1.0 μm by plasma CVD using iH4, NH3, and N2 gases. (Fig. 1(a)) Next, the opening part of the peer hole was formed using photolithography technology.
150sccm, 0250sec, pressure 0.5To
Holes are opened by isotropic dry etching of rr (Fig. 1(b)
)).

Polyimide resin film 8 is deposited on the silicon substrate at 600° rpm.
0.5 μm coating at 100℃N for 230 minutes, 240℃N
Heat at 230°C and 400°C for 230 minutes to imidize. (Fig. 1(C)) At this time, the film thickness is 0.3 to 0.
It decreases to 4 μm. 0215s on the entire wafer surface
Etch back by 0.2 to 0.3 μm using anisotropic plasma etching at a pressure of 0.5 Pa and a power of 300 W to expose the top of the first layer metal wiring, and Aluminum wiring 5 is formed to a thickness of about 1.0 μm by DC magnetron sputtering. If necessary at this time, Ar
The wafer surface may be physically sputter etched with a gas.

(FIG. 1(d)) Next, a second layer of aluminum wiring is formed by anisotropic plasma etching using a gas containing CCβ4 as a main component. At this time, when the etching of the second layer aluminum wiring is completed, an organic film appears on the underlying layer, so there is no undercut or side etching of the aluminum. In addition, since the surface of the first layer aluminum wiring is covered with a tungsten film, C(
It is not etched by the gas containing 14 as a main component, and the etching of the first layer aluminum wiring can also be removed. FIG. 1(e) shows a plan view at that time.

In addition, instead of polyimide resin, a coated oxide film called spin-on glass was applied at 4000 rpm and heated at 100°C.
The gap between the peer hole and the first layer wiring can be filled even by heat treatment for 30 minutes in air and 230 minutes at 400°C.

FIG. 2 is a longitudinal sectional view of Example 2 of the present invention.

A first layer of aluminum wiring 3 is formed on the surface of the silicon oxide film 1 on the silicon substrate to a thickness of about 1.0 μm by normal DC magnetron sputtering, and then anisotropic plasma etching is performed using a gas containing CC124(a) as the main component. , WF, is selectively formed on the surface of the aluminum wiring by a low pressure CVD method at 0.2 Pa to form a tungsten film 10 with a thickness of 0.1 μm.

Thereafter, a polyimide film 8 of approximately 1.0 μm is formed by coating at 3000 rpm, and heat treatment is performed at 100° C. for 30 minutes and at 240° C. for 30 minutes. (Fig. 2 (a)) The polyimide film 8 is etched using a mixed solution of hydrazine and ethylenecyamine by ordinary photolithography to form a pier hole (Fig. 2 (b). 0.5 polyimide film at 6000 rpm
μm formation at 100℃ for 30 minutes, 240℃ for 30 minutes, 400℃
Heat treatment is performed for 30 minutes at °C. (Fig. 2 (C)) Next, the substrate surface is etched back using 02 anisotropic etching, the top of the first layer of aluminum wiring is exposed, and the second layer is etched back.
A layer of aluminum wiring 5 is formed by DC magnetron sputtering. (FIG. 2(d)) Using a photoresist formed by ordinary photolithography as a mask, the aluminum wiring 5 is anisotropically etched using a gas containing cc n 4 f as the main component.

〔Effect of the invention〕

As explained above, in the present invention, the pier hole is opened wider than the width of the aluminum wiring, and the gap between the hole part and the first layer aluminum wiring is filled with an organic insulating film or spin-on glass and flattened. There is no need to widen the wiring width, and the effect of increasing the degree of integration is significant.

Also, because the peer hole is made wider than the wiring width, there is a risk that the first layer wiring will also be etched when etching the second layer wiring, so some or all of the first layer wiring may be etched into the second layer. This can be effectively prevented by coating the wiring with a second metal that is not etched by the etchant.

This second metal is, for example, Mo, W, Ta, Au, etc. when the second layer wiring is aluminum.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are longitudinal cross-sectional views and plan views of one embodiment of the present invention, and FIGS. 2(a) to (d) are longitudinal cross-sectional views and plan views of a second embodiment of the present invention. Figure 3 (a, j'' (d) shows a longitudinal cross-sectional view and a plan view of the conventional example, respectively. 1... Silicon oxide film, 2... Silicon nitride film, 3... ...Aluminum wiring, 4...
Photoresist, 5... Second layer aluminum wiring, 6... Pier hole, 7... Tungsten film, Death... Polyimide, 9...・Second
polyimide film, 10...CVD tungsten film. Agent Patent Attorney Hara Uchi 1 mclD Kunkunuden 7Z, J'7

Claims (1)

[Claims] The first interlayer insulating film has an opening having a diameter wider than the width of the first layer metal wiring formed on the surface of a predetermined semiconductor substrate.
The gap between the opening and the first layer metal wiring is filled with an organic insulating film or spin-on glass, and the surface of the first layer metal wiring is formed on the second layer metal wiring. A semiconductor device characterized in that the semiconductor device is partially or completely covered with a second metal film that is resistant to an etchant for forming metal wiring.