JPH0574759A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent cavities from being generated in a resist film by a method where an SOG film is filled into the recesses provided to a passivation film, where the recesses of the passivation film are not fully filled with resist when resist is applied onto the passivation film, so that cavities are induced in the resist film, in result the unnecessary part is sometimes etched to deteriorate a semiconductor integrated circuit in manufacturing yield and reliability. CONSTITUTION:After a passivation film 3 is formed, an SOG film 4 lower than resist in viscosity is applied thereon, the recesses of the passivation film 3 are filled with the SOG film 4, and then a resist film 5 is formed thereon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for patterning a passivation film.

[0002]

2. Description of the Related Art A conventional patterning method for a passivation film (surface protection film) is shown in FIGS.
Will be described.

First, as shown in FIG. 2A, an Al wiring 2 on an interlayer insulating film 1 formed on a semiconductor substrate (not shown) is patterned. Next, passivation film 3
To form. As the passivation film 3, a plasma-based oxynitride film and a nitride film are used.

Next, as shown in FIG. 2B, a resist film 5 is formed by applying a resist and baking the resist to densify it.

Next, as shown in FIG. 2C, alignment exposure and development are carried out to pattern the resist film 5.

Next, as shown in FIG. 2D, the passivation film 3 is patterned by etching using the resist film 5 as a mask.

Finally, as shown in FIG. 2E, the resist film 5 is peeled off to complete the patterning of the passivation film 3.

[0008]

[Problems to be Solved by the Invention] With the progress of higher integration of semiconductor integrated circuits, Al wiring intervals are becoming narrower and narrower. Therefore, as shown in FIG. 3B, the concave portion of the passivation film 3 in the portion where the Al wiring 2 has a narrow interval cannot be sufficiently filled with the resist 4, so that the "su" 6 is generated.

In this state, if baking is performed to densify the resist 4, the air in the portion "su" 6 expands, and the film thickness of the resist film 5 becomes thin as shown in FIG. 3 (c). At the time of etching, the etching progresses to a place other than a predetermined place, which reduces the yield and reliability of the semiconductor integrated circuit.

[0010]

According to a method of manufacturing a semiconductor device of the present invention, a passivation film is formed on one main surface of a semiconductor substrate, and then an SOG film having a viscosity lower than that of a resist used in a subsequent step is formed. It includes a step and a step of applying the resist.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to (e).

First, as shown in FIG. 1A, an Al wiring 2 having a thickness of 1 μm is formed on an interlayer insulating film 1. Next, the passivation film 3 is formed.

A plasma-based oxynitride film or a nitride film is used as the passivation film 3. However, since these passivation films have poor step coverage, the surface shape is as shown in FIG. 1 (a).

Next, as shown in FIG. 1 (b), the SOG film 4 is applied and baked in an N ₂ atmosphere at 300 ° C. for 60 minutes, and then a resist is applied.
The resist film 5 is densified by baking for 1 minute.

The film thicknesses of the SOG film 4 and the resist 5 were 300 nm and 500 nm, respectively. As the SOG film 4, P-48324 manufactured by Tokyo Ohka Kogyo Co., Ltd. was used.

While the resist film 5 has a viscosity of 50 cp, the SOG film 4 has a very low viscosity of 1 cp. Therefore, as shown in FIG. 3A, the recesses of the passivation film 3 can be sufficiently filled with the SOG film 4 even in a portion where the Al wiring 2 has a narrow interval, and no "su" occurs.

Next, as shown in FIG. 1C, the resist film 5 is patterned by carrying out alignment exposure and development.

Next, as shown in FIG. 1D, the SOG film 4 and the passivation film 3 are etched using the resist film 5 as a mask.

Finally, as shown in FIG. 1E, the resist film 5 is peeled off to complete the patterning of the passivation film 3.

[0020]

According to the conventional method of directly applying a resist, when the space between the Al wirings is 1 μm or less, “spot” occurs. However, by applying the SOG film and then applying the resist as in the present invention, It is possible to prevent the occurrence of "su".

Since the passivation film is formed and the SOG film having a viscosity lower than that of the resist is used to planarize the resist, the resist is applied, so that "spots" do not occur as shown in FIG. 3 (a). Even if the heat treatment for densifying the resist is performed, the resist is not deformed.

As a result, the defect occurrence rate when patterning by the conventional method was 50%, whereas in the present invention the defect occurrence rate was almost 0%.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a passivation film patterning method according to a conventional technique in the order of steps.

FIG. 3 is an enlarged cross-sectional view showing a problem when patterning a passivation film.

[Explanation of symbols]

 1 interlayer insulating film 2 Al wiring 3 passivation film 4 SOG film 5 resist film 6

Claims (1)

[Claims] 1. A semiconductor device including a step of forming a passivation film on one main surface of a semiconductor substrate and then forming an SOG film having a viscosity lower than that of a resist used in a subsequent step, and a step of applying the resist. Manufacturing method.