JPH01296657A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to conduct swiftly verification of the effect of improvement of the channel width of a transistor or the channel length of a transistor by a method wherein a metal wiring layer only, which consists of Al and the like and by which the sources, drains and gates of the transistors are mutually connected, is changed and the channel width and the channel length are designed changeably. CONSTITUTION:A P-channel transistor 11 can be selected the channel length of the transistor from among 3 kinds of channel lengths by making metal wirings 17 connect to one of transistors 19, 120 and 121. Moreover, a transistor 13 can be changed the channel width of the transistor into 2 kinds by connecting or cutting a metal wiring 18. Moreover, a transistor, which is used as the key transistor in a circuit, is not arranged one kind only, but a transistor of a size, which is thought to be necessary in the following experiment and alteration, is also ready-arranged in advance and yet, the connection of the metal wirings is contrived so as to be able to select freely by a change only of a metal wiring layer. Thereby, verification of the effect of a change of the channel width and the channel length can be conducted very swiftly.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

FIGS. 4(a) and 4(b) are layout diagrams and circuit diagrams of a CMOS inverter constituted by transistors in a conventional semiconductor device.

In this conventional system, the input signal A is composed of p-ah) transistors η and n-ah) transistors (a).
CMOS inverter and each transistor (to),
弼, (to).

This circuit is formed by a total of three sets of inverters, two sets of inverters made up of wires, and a time delay in which the output signal B passes through the inverters as an inverted signal of A.

The actual time delay is determined by the transistor sizes of the three sets of inverters.

5(-) and 5(b) are layout diagrams and circuit diagrams of a buffer composed of two n-ah) run rasters used in the final stage of output.

Output (When outputting an H level to Q, set A to an H level and turn Cυ onl (at this time, B is at a low level); conversely, when outputting a low level to an output, set B to an H level and set A to an L level.
OW level).

[Problem to be solved by the invention]

In the inverter circuit used for signal delay in Figure 4, if you try to change the transistor size once set in the actual manufacturing process in order to adjust the delay time, when changing the channel width of the transistor, the source/drain formation It is necessary to change the manufacturing mask for the active region for impurity diffusion, and this step is the very first step in the entire process.
It takes time to confirm the effect, and when changing the channel length of a transistor, it is necessary to change the manufacturing mask for forming the transistor gate, and it is necessary to restart the process from the middle of the process. there were.

Also, in a circuit like the final output stage in Figure 5, if you want to speed up the data output access time, make it a little larger, and the wiring of the output load surface path will be reduced. Depending on the ingredients,
Overshoots and undershoots occur in the output signal itself, and the magnitude of this reaches a level exceeding the output signal DC rating (determined by the product), resulting in a loss of access time as shown in the output waveform in Figure 6. Something happened. Therefore, it is necessary to carefully adjust the transistor size while looking at the data, and as described above, this change was made before the middle of the manufacturing process.

An object of the present invention is to provide a semiconductor device in which improvement effects can be quickly confirmed. Even if the channel width and channel length are changed by simply changing the mask of the metal wiring layer made of An, etc., very late during the manufacturing process, the channel width and channel length can be changed, making it possible to confirm the effect of changes extremely quickly. It is.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained in Fig. 1 (
a) is a layout diagram showing one embodiment of this invention, FIG. 1(b)
is the circuit diagram of FIG.

uo's p-ah) The transistor allows the channel length of the υ transistor to be selected from three types by connecting the metal wiring of the αη part to one of the transistors αi, tA, ■p.0 However, it is possible to change the channel width of the transistor into two types by connecting, cutting, or cutting the transistor (to) and metal wiring (t).

Although this example shows the case where the transistors are arranged vertically, they may also be arranged horizontally depending on the space.
h) Limited to transistors (3), can be applied to n-ah transistors, or can be applied to both at the same time.

This invention allows not only one type of transistor, which is the key to the circuit, but also transistors of the size deemed necessary for later experiments and modifications to be arranged in advance, and connections can be made freely by simply changing the metal arrangement layer. You can now select.

For example, in FIG. 4(a), the p-ah) transistor corresponding to Q]) in the circuit diagram of FIG. 4(b) has a signal "
It is necessary to experimentally adjust the delay time from "A" to "B" several times, and conventionally, a transistor of one size is arranged and a mask for forming the source and drain of that transistor and a transistor gate are created. The final size was determined by repeating experiments to change the mask used for the purpose.If this invention is applied, multiple transistors that are likely to be unnecessary can be installed in advance, as shown in Figure 1(a). The circuit where the metal wiring layers shown as αη, (to) are connected.
That is, by cutting the metal wiring layer α force, (
The size of the transistor can be changed simply by changing the mask of

FIG. 2 shows a layout diagram of another embodiment applied to an output buffer. This is the same as in FIG. 1 above, where the wiring (a) and (5
In step 2), the transistor channel width can be adjusted by connecting or disconnecting the wiring.

Furthermore, FIG. 3 is a layout diagram showing yet another embodiment in which the channel width of a transistor is changed using the same concept. By connecting the wiring (61) and separating the wiring (62),
In this embodiment, the channel width can be 475.

〔Effect of the invention〕

As described above, according to the present invention, by devising the layout in advance, the channel width and channel length of the transistor can be changed simply by changing the wiring process such as A1, so the improvement effect can be quickly confirmed. It is possible to obtain a semiconductor device that can perform the following steps.

[Brief explanation of the drawing]

FIG. 1(a) is a layout diagram of a semiconductor device which is an embodiment of the present invention, FIG. 1(kl) is a circuit diagram of FIG. 1(a), and FIG.
The figure is a layout diagram showing another embodiment in which the present invention is applied to an output buffer, FIG. 3 is a layout diagram showing still another embodiment of the output buffer, and FIG. 4(a) is a layout diagram of a conventional semiconductor device. , Figure 4(1)) is the circuit diagram of Figure 4(a), and Figure 5(1) is the circuit diagram of Figure 4(a).
Figure (a) is a layout diagram of a conventional semiconductor device using an output buffer, Figure 5 (1)) is a circuit diagram of Figure 5 (a), and Figure M6 is an output waveform diagram explaining overshoot and undershoot. . In the figure, (11), (l yen, sea bream, chestnut, 澾, 翰 are p-ah) gate electrode forming a transistor, (2),
0 fan, αQ, (2). (C) and (E) are H-ch gate electrodes forming transistors (17); (g), (51) e (52), (61) t
(62) is the metal wiring layer connected and separated according to the present invention, (to), (x2o), (12x)
0 indicates a p-Oh transistor selected according to the present invention. In the drawings, the same reference numerals indicate the same or corresponding parts. Figure 1 ('') Vtc [Mikou 1-Island ΔOg table E Hascha shell and moxibustion jsr: + Yu () Island ♂V 艮l Gate electric power Don't forget to contact L between Figure 2 vss ( Hill IVD) Figure 3 Figure 4 cc vss (G#D) (b) Original procedural amendment to Figure 6 (voluntary)

Claims (1)

[Claims] (1) The source or drain of a transistor is formed by diffusing p-type or n-type impurities onto an n-type or p-type semiconductor substrate, and the gate of the transistor is formed using a high-melting point metal such as polysilicon or silicide. In the semiconductor device to be formed, the structure and arrangement are such that the channel width or channel length of the transistor can be changed by changing only the metal wiring such as Al that interconnects the source, drain, and gate. Characteristic semiconductor devices.