JPH1140678A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and a method for manufacturing it wherein the resistance value inserted between an external terminal and an ESD protection circuit can be adjusted, there is no risk of lowering of the current supplying ability per unit area of a transistor, there is no risk of increase in the number of processes in a production line, and further the higher integration and miniaturization can be obtained. SOLUTION: In a semiconductor integrated circuit device, provided with an ESD protection circuit including a plurality of transistors as constituent elements, wherein a drain part 21 of these transistor is connected to an external terminal 4, respective gate electrodes 11-13 of a plurality of transistors are provided contiguously to the gate electodes of adjacent transistors, and a diffusion layer 21 to be a drain part is formed between these contiguous gate electrodes 11-13, and regions C, D, wherein no titanium silicide is formed, are provided on this diffusion layer 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit device having an ESD protection circuit including a plurality of transistors as constituent elements and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, an ESD protection element and an output drive element are shared and used as the density increases. In recent years, with further densification, a high-concentration N-type diffusion layer (hereinafter also referred to as an N + diffusion layer)
In order to avoid a decrease in operating speed due to an increase in the resistance value of
A technique for converting an N + diffusion layer to titanium silicide is used.

When the N + diffusion layer is made of titanium silicide, the area resistance of the N + diffusion layer does not change to several hundred Ω / □, but the sheet resistance of the titanium silicide film becomes several Ω / □.
□, the resistance on the N + diffusion layer is several hundred Ω /
From □ to several Ω / □. Therefore, although the operating speed is improved, the resistance value of the N + diffusion layer is significantly reduced, and the ES +
When the D pulse is concentrated on the gate electrode, there arises a problem that the ESD tolerance is reduced.

Therefore, a semiconductor integrated circuit device in which the resistance to ESD is improved by inserting a high resistance into the drain of an N-channel (hereinafter also referred to as Nch) protection transistor has been proposed and put into practical use. For example, in the semiconductor integrated circuit device disclosed in U.S. Pat. No. 5,019,888, a low-concentration N-type diffusion layer (hereinafter, referred to as an N-diffusion layer) is provided between an external terminal and a drain of an Nch protection transistor. ), By inserting TiN or a gate electrode,
High resistance is formed.

FIG. 5 is a plan view showing a first conventional example of a semiconductor integrated circuit device in which a high resistance is formed using an N-diffusion layer. FIG. 6 is a cross-sectional view taken along line AA of FIG. FIG. N
The channel protection transistor includes a gate electrode 1 and N + diffusion layers 21a and 23 formed on a silicon substrate 5, and includes the gate electrode 1 and the N + diffusion layer 2 on the source side.
3 is connected to the aluminum wiring 112 via the contact 63, and the aluminum wiring 112 is grounded 100.

The N + diffusion layer 21a on the drain side of the Nch protection transistor is connected to the N + diffusion layer 21b via the N− diffusion layer 3, and the N + diffusion layer 21b is connected to the aluminum wiring 111 via the contact 62. The aluminum wiring 111 is connected to the external terminal 4.

The N + diffusion layer 21a on the drain side of the Nch protection transistor and the external terminal 4 are connected to the aluminum wiring 1
11 and N + diffusion layer 2 connected via contact 62
1b is separated by a field insulating film 9.
A titanium silicide film 8 is formed on each of the N + diffusion layers 21a, 21b, and 23.
Side walls 7 are formed on both sides of the gate electrode 1.

The area resistance of the N-diffusion layer 3 is, for example, about 10
00Ω / □, when an ESD pulse is applied to the external terminal 4, N
Since the ESD pulse is applied to the channel protection transistor, the ESD tolerance is improved. However,
N-diffusion layer 3 between external terminal 4 and Nch protection transistor
Is inserted to form a resistor, the minimum width of the N- diffusion layer 3 and the concentration of the diffusion component are determined by the manufacturing process, and the selection range of the resistance value is narrow.

Further, when the protection element and the output drive element are shared, the area resistance of the N-diffusion layer 3 is as large as 1000 Ω / □, so that the current supply capability per unit area of the transistor is reduced. In order to secure the output driving capability, it is necessary to increase the area of the ESD protection circuit.

FIG. 7 is a plan view showing a second conventional example of a semiconductor integrated circuit device forming a high resistance using TiN, and FIG. 8 is a sectional view taken along the line BB of FIG. . Nch
The protection transistor includes a gate electrode 1 formed on a silicon substrate 5 and N + diffusion layers 21 and 23.
The contact electrode 1 and the N + diffusion layer 23 on the source side
3 is connected to the aluminum wiring 112 and the aluminum wiring 1
12 is grounded 100.

[0011] N on the drain side of the Nch protection transistor
+ Diffusion layer 21 is connected to contact 62 via TiN 10, contact 62 is connected to aluminum wiring 111, and aluminum wiring 111 is connected to external terminal 4.
In this semiconductor integrated circuit device, the number of steps in the manufacturing line increases because TiN must be selectively added and formed.

FIG. 9 is a plan view showing a third conventional example of a semiconductor integrated circuit device in which a high resistance is formed using a gate electrode, and FIG. 10 is a cross-sectional view taken along line CC of FIG. is there.
The Nch protection transistor includes a gate electrode 1 and N + diffusion layers 21 and 23 formed on a silicon substrate 5. The gate electrode 1 and the N + diffusion layer 23 on the source side are connected to an aluminum wiring 112 through a contact 63. The aluminum wiring 112 is connected to the ground 100.

N on the drain side of the Nch protection transistor
+ Diffusion layer 21 is connected to aluminum wiring 1 through contact 62
11 and the aluminum wiring 111 is connected to the external terminal 4. On the other hand, a gate electrode 11 is arranged between the gate electrode 1 of the Nch protection transistor and a contact 62 connecting the external terminal 4 and the N + diffusion layer 21. An N + diffusion layer 21 is buried under the gate electrode 11 as a resistance element, and the resistance of the N + diffusion layer 21 below the gate electrode 11 is increased.

When this gate electrode 11 is used, N
Since the resistance is formed by embedding the N + diffusion layer 21 and the step of forming the N + diffusion layer 21 is shared with other steps, the resistance value is determined in advance to an optimum value in the manufacturing process. And the selection range of the resistance value is narrow.

FIG. 11 is a plan view showing a fourth conventional example of a semiconductor integrated circuit device disclosed in Japanese Patent Application Laid-Open No. Hei 5-3173, and FIG. 12 is taken along the line DD in FIG. It is sectional drawing. In this semiconductor integrated circuit device, a high resistance is formed by inserting an N + diffusion layer not converted to titanium silicide between an Nch protection transistor and an external terminal.

The Nch protection transistor comprises a gate electrode 1 formed on a silicon substrate 5 and N + diffusion layers 21 and 2.
The gate electrode 1 and the N + diffusion layer 23 on the source side are connected to an aluminum wiring 112 via a contact 63, and the aluminum wiring 112 is grounded 100. The N + diffusion layer 21 on the drain side of the Nch protection transistor is connected to an aluminum wiring 111 via a contact 62, and the aluminum wiring 111 is connected to the external terminal 4.

By forming a region 21c covered by the titanium silicide film 8 and a region 21d not covered on the N + diffusion layer 21, the gate electrode 1 of the Nch protection transistor, the external terminal 4 and the N + diffusion are formed. Between the contact 62 connecting the layer 21 and the resistance of the N + diffusion layer 21 alone, which is not turned into titanium silicide, is inserted. In this semiconductor integrated circuit device, a region 21c where the N + diffusion layer 21 is covered with the titanium silicide film 8 and a region 21d where the N + diffusion layer 21 is not covered with the titanium silicide film 8 are selectively provided between the external terminal 4 and the Nch protection transistor. Therefore, the number of steps in the production line increases.

[0018]

The first problem is that N-
When a high resistance is formed using a diffusion layer, the resistance value is too large, and the current supply capability per unit area of the transistor is reduced. For example, in the first conventional example,
Since the sheet resistance of the N- diffusion layer 3 is 1000Ω / □,
If the length of the N-diffusion layer 3 is 40 μm and the width is 0.4 μm, the resistance value becomes 10Ω and the ON resistance of the transistor becomes 6 μm.
Assuming that the resistance is 6Ω, the resistance value increases by 15% when the same current flows, and the length of the N− diffusion layer 3 must be increased by an amount corresponding to the resistance increase.

The second problem is that since a high resistance is formed between the external terminal 4 and the ESD protection circuit, the number of manufacturing lines of the semiconductor integrated circuit device increases. For example, in the second conventional example, the number of steps increases because TiN must be selectively added and formed.
In the fourth conventional example, the region 21c covered with the titanium silicide film 8 and the region 21d not covered with the titanium silicide film 8 must be selectively formed, so that the production line The number of processes is inevitably increased.

A third problem is that the resistance of the high resistance inserted between the external terminal 4 and the ESD protection circuit cannot be adjusted. For example, in the first conventional example, when the N-diffusion layer 3 is inserted between the external terminal 4 and the ESD protection circuit to form a resistor, the minimum width of the N-diffusion layer 3 and the concentration of the diffusion component are reduced. Is determined by the manufacturing process, so that the selection range of the resistance value is narrowed.

For example, when the width of the N-diffusion layer 3 is 0.8 μm,
If the length is 40 μm, the resistance value is 20Ω, and
To obtain a resistance of 0Ω, the width of the N-diffusion layer should be 8 μm.
m, which increases the area of the ESD protection circuit. Therefore, the selection range of the resistance value is limited to a narrow range.

In the third conventional example, the gate electrode 1
1 is inserted between the external terminal 4 and the ESD protection circuit and the N + diffusion layer 21 is buried under the gate electrode 11 to form a resistor. Since the diffusion layer 21 shares a process with other N + diffusion layers 23, the selection range of the resistance value is limited to a narrow range. For example, if the width of the gate electrode 11 is 0.4 μm, the length is 40 μm, and the area resistance is 30 Ω / □, the resistance value is 3
When a resistance of 200Ω is to be obtained, the width of the gate electrode 11 needs to be as large as 27 μm, and the area of the ESD protection circuit is very large, which poses a practical problem. The range is limited to a narrow range.

The present invention has been made in view of the above circumstances, and it is possible to adjust the resistance of a high resistance inserted between an external terminal and an ESD protection circuit, and to increase the resistance. And the current supply capability per unit area of the transistor is not reduced, and the number of steps in the manufacturing line is not increased. Further, high integration and miniaturization are achieved. To provide a semiconductor integrated circuit device and a method of manufacturing the same.

[0024]

In order to solve the above-mentioned problems, the present invention employs the following semiconductor integrated circuit device and its manufacturing method. That is, the semiconductor integrated circuit device according to claim 1, further comprising an ESD protection circuit including a plurality of transistors as constituent elements, wherein the drain portion of the transistor is connected to an external terminal. Each gate electrode is provided so as to be adjacent to a gate electrode of an adjacent transistor, a diffusion layer serving as a drain portion is formed between these adjacent gate electrodes, and a region where titanium silicide is not formed on the diffusion layer is formed. It is provided.

According to a second aspect of the present invention, in the semiconductor integrated circuit device, the plurality of transistors are arranged on a diffusion layer serving as a common drain of these transistors.

According to a third aspect of the present invention, the distance between the gate electrodes is reduced by enlarging the sidewalls of each of the gate electrodes in a direction approaching each other.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit device, a region where the titanium silicide is not formed has a high resistance.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit device, the transistor is any one of an N-channel protection transistor and a P-channel protection transistor.

According to a sixth aspect of the present invention, in a method of manufacturing a semiconductor integrated circuit device, an ES including a plurality of transistors as constituent elements.
A method for manufacturing a semiconductor integrated circuit device, comprising: a D protection circuit, wherein a drain portion of the transistor is connected to an external terminal, wherein a gate electrode of each of the plurality of transistors is close to a gate electrode of an adjacent transistor. In this method, a region without titanium silicide is formed on a diffusion layer serving as a drain portion between these adjacent gate electrodes.

In the semiconductor integrated circuit device of the present invention, the ESD
A resistor inserted between the transistor and the external terminal uses a diffusion layer between the gate electrodes as a resistor for circuit protection. Titanium silicide on the diffusion layer is formed by heat treatment of the diffusion layer serving as the drain portion and titanium. However, since sidewalls made of a silicon oxide film are formed on both sides of the gate electrode, the titanium silicide is formed between the gate electrode and the gate electrode. If the distance between them is reduced, the area of the diffusion layer becomes narrower, and the heat treatment of titanium and the diffusion layer cannot be performed well. Therefore, the diffusion layer between the gate electrodes is hardly made into titanium silicide, and the resistance becomes higher.

Therefore, a gate electrode of each of the plurality of transistors is provided so as to be close to a gate electrode of an adjacent transistor, and a diffusion layer serving as a drain portion is formed between these adjacent gate electrodes. By providing a region where titanium silicide is not formed, the width of this diffusion layer and the size of the region where titanium silicide is not formed are adjusted, so that the external terminal and the ESD are not formed.
It becomes possible to adjust the resistance value of the high resistance inserted between the protection circuit. Further, the resistance value can be easily adjusted by changing the number of gate electrodes to be used and the distance between the gate electrodes.

Further, by providing the respective gate electrodes so as to be close to each other, the area required for forming the resistance element is reduced, whereby high integration and miniaturization can be achieved. In addition, since the resistance value of titanium silicide is smaller than the resistance values of the diffusion layer and the gate electrode, a reduction in current supply capability per unit area of the transistor is suppressed.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a gate electrode of each of a plurality of transistors is formed so as to be close to a gate electrode of an adjacent transistor, and serves as a drain between the adjacent gate electrodes. By forming a region without titanium silicide on the diffusion layer, the resistance of the diffusion layer between the gate electrodes is not increased to titanium silicide. This makes it possible to manufacture a semiconductor integrated circuit device having a high-resistance diffusion layer between gate electrodes.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor integrated circuit device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line EE of FIG. 1, FIG. 3 is a cross-sectional view taken along line FF of FIG. FIG. 4 is a sectional view taken along the line GG of FIG.

Gate electrode 1 and source side N + diffusion layer 2
2 is connected to an aluminum wiring 110 via a contact 61, and the gate electrode 14 and the N + diffusion layer 23 on the source side are connected to an aluminum wiring 112 via a contact 63. , 112 is ground 100
Have been.

The drain-side N + diffusion layer 21 is in contact with the N + diffusion layer 21 via a resistor formed by reducing the distance between the first gate electrode 11 to the third gate electrode 13. 62, the contact 62 is connected to the aluminum wiring 111, and the aluminum wiring 111 is connected to the external terminal 4, so that the N + diffusion layer 2 serving as a drain portion is formed.
Numeral 1 is connected to an external terminal 4 via a resistor to form an Nch protection transistor whose gate and source are grounded.

At this time, the N− diffusion layer 3 is arranged below the drain N + diffusion layer 21 and is connected to the N + diffusion layer 21. The first gate electrode 11 to the third gate electrode 13 are connected to the aluminum wiring 111 via the contact 64.
Is connected to The resistor is connected to the first gate electrode 11.
And the second gate electrode 12 are arranged on the N + diffusion layer 21 so as to surround the contact 62, and the first gate electrode 11
1 of a region sandwiched between the first gate electrode 12 and the second gate electrode 12 (FIG. 1)
The distance between the regions C and D) enclosed by the middle and
+ Diffusion layer 21 and re-contact 62 and gate electrodes 1 and 1
The fact that the titanium silicide film 8 is not formed on the N + diffusion layer 21 when the distance between the gate electrodes 11 and 12 is reduced by connecting the four electrodes 4 is utilized.

A resistor can be formed even if the distance between the gate electrodes is reduced to a plurality of places. By increasing the number of locations where the distance between the gate electrodes is reduced, it is possible to increase the number of resistors and adjust the resistance value. The gate electrode for forming the resistor is the third gate electrode 13.
In addition, the resistance value can be adjusted by adding an arbitrary number of gate electrodes after the fourth gate electrode.

Further, a gate electrode 1 for forming a resistor is provided.
Reference numerals 1 to 13 surround the contact 64 connecting the N + number-expanding layer 21 and the aluminum wiring 111, and the gate electrodes 11, 12
If the interval between the gate electrodes 12 and 13 is an interval where the titanium silicide film is not formed, N + serving as a drain is formed.
The same effect can be obtained by arranging the gate electrode and the contact at arbitrary positions and directions on the extension layer 21. In addition, although it is composed of two Nch protection transistors, it goes without saying that a similar effect can be obtained even if it is composed of one or a plurality of transistors.

Next, a gate electrode for forming a resistor will be described with reference to FIG. On the silicon substrate 5,
Gate electrode 1 of Nch protection transistor and gate electrode 1
A gate electrode 11 for forming a resistance is disposed in the N + diffusion layer 21 on the drain side between the N channel 4 and the diffusion layers 21 to 2 on the source side and the drain side of the Nch protection transistor.
3, a titanium silicide film 8 is formed, so that the film 3 is made into titanium silicide.

Sidewalls 7 are formed on both sides of each of the gate electrodes 1, 11, and 14, and a field insulating film 9 is disposed at an end of the Nch protection transistor. On the other hand, gate electrode 1 is connected to aluminum wiring 110 via contact 61, gate electrode 14 is connected to aluminum wiring 112 via contact 63, and gate electrode 11 is aluminum wiring 111 connected to external terminal 4. Through a contact 64.

Further, in order to stabilize the potential of the N + diffusion layer 21 on the drain side of the Nch protection transistor,
An N− diffusion layer 3 is arranged on the entire drain side of the Nch protection transistor.
All N + diffusion layers 21 on the drain side of the channel protection transistor are electrically connected.

For example, the sheet resistance of the N-diffusion layer 3 is about 22
It is as large as 00 Ω / □, and does not affect the resistance value of the resistor formed by reducing the distance between the gate electrodes 11 to 13. Also, gate electrodes 11 to 13 for forming resistors
Are arranged at narrow intervals, so that the gate electrodes 11 to 1
The same effect can be obtained even if no potential is applied, unless the space between the three is made of titanium silicide.

Next, a method of inserting a resistor will be described with reference to FIG. The gate electrode 1 of the Nch protection transistor on the silicon substrate 5 and the N + diffusion layer 22 on the source side are connected to the aluminum wiring 110 grounded via the contact 61. Further, the gate electrode 14 and the source side N
+ Diffusion layer 23 is connected to aluminum wiring 112 grounded 100 via contact 63. Then, sidewalls 7 are formed on both sides of the gate electrodes 1 and 14, and a field insulating film 9 is disposed at an end of the Nch protection transistor.

N on the drain side of the Nch protection transistor
By connecting the + diffusion layer 21 to the N − diffusion layer 3 and reducing the distance between the gate electrodes 11 and 12, the region covered with the titanium silicide film 8 and the region Uncovered areas C and D are formed. The drain of the Nch protection transistor is connected to the titanium silicide film 8.
Are connected to the contacts 62 via the regions C and D which are not covered by the wiring, and are connected to the external terminals 4 via the aluminum wiring 111.

Therefore, since the Nch protection transistor and the external terminal 4 are connected via the regions C and D which are not covered with the titanium silicide film 8, the resistance is several Ω when the titanium silicide film 8 is present. Instead of a certain low resistance, a high-resistance resistor having a sheet resistance of about 100Ω / □ of the N + diffusion layer 21 is inserted between the external terminal 4 and the Nch protection transistor.

Next, a method of forming a resistor will be described with reference to FIG. The gate electrodes 11 and 1 are formed on the N + diffusion layer 21 on the drain side of the Nch protection transistor on the silicon substrate 5.
2, and the gate electrodes 11 and 12 are connected to the aluminum wiring 111 via the contact 64. At this time, sidewalls 7 are formed on both sides of the gate electrodes 11 and 12, respectively. The titanium silicide film 8 is made of titanium and an N + diffusion layer 21.
If the distance between the gate electrodes 11 and 12 is small, the N + diffusion layer 21 between the gate electrodes 11 and 12 is covered with the side wall 7 and the titanium and the N + diffusion layer are formed. Since the heat treatment 21 cannot be performed, the titanium silicide film 8 is not formed on the N + diffusion layer 21.

The area resistance of the N + diffusion layer 21 is about 100 Ω /
This resistance is inserted between the Nch protection transistor and the external terminal 4 by using the fact that it is as large as □. At this time, the N + diffusion layers 21 are connected to the N− diffusion layers 3 respectively. For example, when the width of the side wall 7 is about 0.1 μm, when the distance between the gate electrodes 11 and 12 is reduced to a distance of 0.2 μm, which is two of the side walls 7, the N + diffusion layer 21 Is not converted to titanium silicide.

The resistance value can be adjusted to an arbitrary value by changing the interval between the gate electrodes 11 and 12 to change the region to be converted into titanium silicide.
Further, a gate electrode 1 as shown in regions C and D in FIG.
By adjusting the size of the interval between 1 and 12, the resistance value can be adjusted.

For example, if the distance between the gate electrodes 1 and 12 is 0.2 μm, the length is 2 μm, and the area resistance of the N + diffusion layer 21 is 100 Ω / □, the resistance becomes 1000 Ω and the length becomes Is 1 μm, the resistance value is 500Ω. Therefore, when an ESD pulse is applied from the external terminal 4, the ESD pulse contracts between the gate electrode 11 and the gate electrode 12, and the N
The ESD pulse is applied to the drain of the protection transistor via the high resistance of the + diffusion layer 21.

The resistance value of this high resistance depends on the gate electrode 11,
12, the length of the portion for reducing the distance between the gate electrodes 11, 12, the gate electrodes 11, 12 and the contact 6
The resistance value can be easily adjusted by the number of four. Also,
The gate electrodes 11 to 13 for forming the resistors can be arranged at any position and in any direction as long as they are on the N + diffusion layer 21 serving as the drain.

When the Nch protection transistor is an output Nch drive transistor, the inverter type output drive transistor is connected to the output side by connecting the drain of the Pch drive transistor and the drain of the Nch recommended transistor. On the other hand, the gate electrode of the Pch drive transistor and the gate electrode of the Nch drive transistor are connected to form an input side, the source of the Pch drive transistor is connected to the power supply, and the source of the Nch drive transistor is grounded. The internal signal is transmitted from the input side to the output side.

The only difference between the Nch protection transistor and the Nch drive transistor is whether the gate electrode is grounded or connected to an internal signal, and the gate electrode of the Nch protection transistor is connected to the internal signal. Thus, the Nch protection transistor operates as a drive transistor, and a resistor can be inserted between the drain of the drive transistor and an external terminal. Further, needless to say, the same effect can be obtained by using a Pch protection transistor instead of an Nch protection transistor.

According to the present embodiment, the resistance value inserted between the Nch protection transistor and the external terminal can be reduced, and the resistance value can be easily adjusted.
The size of the D protection circuit can be reduced. Further, since high resistance can be formed by the gate electrode, there is an effect that the number of manufacturing steps of the semiconductor integrated circuit device does not need to be increased.

The ESD withstand capability is improved by increasing the resistance value inserted between the Nch protection transistor and the external terminal. However, if the resistance value is large, the current supply capability per unit area of the transistor is reduced. In order to reduce the resistance, the resistance value must secure the necessary ESD resistance,
Although a value that can ensure the current supply capability is required, in the present invention, since the resistance value is small and the resistance value can be easily adjusted, the ESD protection circuit can be reduced in size.

[0056]

As described above, according to the semiconductor integrated circuit device of the present invention, a gate electrode of each of a plurality of transistors is provided so as to be close to a gate electrode of an adjacent transistor. A diffusion layer serving as a drain portion was formed between the electrodes, and a region where titanium silicide was not formed was provided on the diffusion layer.By adjusting the width of the diffusion layer and the size of the region where titanium silicide was not formed, The resistance value of the high resistance inserted between the external terminal and the ESD protection circuit can be adjusted. Further, the resistance value can be easily adjusted by changing the number of gate electrodes to be used and the interval between the gate electrodes.

Further, since the respective gate electrodes can be provided so as to be close to each other, the area required for forming the resistance element can be reduced.
High integration and miniaturization can be achieved. Further, since the resistance value of titanium silicide is smaller than the resistance values of the diffusion layer and the gate electrode, it is possible to suppress a reduction in current supply capability per unit area of the transistor.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the gate electrode of each of the plurality of transistors is formed so as to be close to the gate electrode of the adjacent transistor, and the drain portion between these adjacent gate electrodes is formed. Since a region without titanium silicide is formed on the diffusion layer to be formed, the diffusion layer between the gate electrodes can be made to have a high resistance which is not converted to titanium silicide. Accordingly, a semiconductor integrated circuit device having a high resistance diffusion layer can be manufactured. Further, since there is no need to newly provide a manufacturing process, there is no possibility that the number of processes in the manufacturing line will increase.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 2 is a sectional view taken along the line EE in FIG.

FIG. 3 is a sectional view taken along line FF of FIG. 1;

FIG. 4 is a sectional view taken along line GG of FIG. 1;

FIG. 5 is a plan view showing a first example of a conventional semiconductor integrated circuit device.

FIG. 6 is a sectional view taken along line AA of FIG.

FIG. 7 is a plan view showing a second conventional example of a semiconductor integrated circuit device.

FIG. 8 is a sectional view taken along the line BB of FIG. 7;

FIG. 9 is a plan view showing a third conventional semiconductor integrated circuit device.

FIG. 10 is a sectional view taken along line CC of FIG. 9;

FIG. 11 is a plan view showing a fourth conventional semiconductor integrated circuit device.

FIG. 12 is a sectional view taken along line DD in FIG. 11;

[Explanation of symbols]

 1, 11 to 14 Gate electrode 21 to 23 N + diffusion layer 21a, 21b N + diffusion layer 21c Region covered with titanium silicide film 21d Region not covered with titanium silicide film 3 N-diffusion layer 4 External terminal 5 Silicon substrate 61 to 64 Contact 7 Sidewall 8 Titanium silicide film 9 Field oxide film 10 TiN 100 Ground 110 to 112 Aluminum wiring C, D Region not covered by titanium silicide film

Claims (6)

[Claims] 1. A semiconductor integrated circuit device comprising: an ESD protection circuit including a plurality of transistors as constituent elements, wherein a gate of each of the plurality of transistors is adjacent to a gate of each of the plurality of transistors. Provided in close proximity to the gate electrode of the transistor,
A semiconductor integrated circuit device, wherein a diffusion layer serving as a drain portion is formed between these adjacent gate electrodes, and a region where titanium silicide is not formed is provided on the diffusion layer. 2. The semiconductor integrated circuit device according to claim 1, wherein the plurality of transistors are arranged on a diffusion layer serving as a common drain of the transistors. 3. The space between the gate electrodes is reduced by enlarging the sidewalls of each of the gate electrodes in a direction approaching each other.
13. The semiconductor integrated circuit device according to claim 1. 4. The semiconductor integrated circuit device according to claim 1, wherein the region where the titanium silicide is not formed has a high resistance. 5. The transistor according to claim 1, wherein the transistor comprises one of an N-channel protection transistor and a P-channel protection transistor.
3. The semiconductor integrated circuit device according to claim 1. 6. A method of manufacturing a semiconductor integrated circuit device, comprising: an ESD protection circuit including a plurality of transistors as constituent elements, wherein a drain of the transistor is connected to an external terminal. Forming a region without titanium silicide on a diffusion layer serving as a drain portion between gate electrodes adjacent to each other, and forming a region without titanium silicide. Method.