JPH01291591A - Pal/ntsc system discriminator - Google Patents
Pal/ntsc system discriminatorInfo
- Publication number
- JPH01291591A JPH01291591A JP63120749A JP12074988A JPH01291591A JP H01291591 A JPH01291591 A JP H01291591A JP 63120749 A JP63120749 A JP 63120749A JP 12074988 A JP12074988 A JP 12074988A JP H01291591 A JPH01291591 A JP H01291591A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pal
- vertical synchronizing
- pulse width
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、PALJllIvTR(ビデオテープレコー
ダ)ノ再生信号をPAL/NTSCJ111VTRで記
録する場合のシステム判別装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system discrimination device for recording a playback signal of a PALJllIvTR (video tape recorder) with a PAL/NTSCJ111VTR.
第3図に示すように、PAL用VTR1で再生している
画像を、PAL/NTSC用VTR2で記録する、つま
りダビングする場合には、PAL/NTSC用V T
R2ニおいてPALシステムの映像信号が入力している
ことを自動的に判別し、内部をPALモードに切り換え
て録画動作を行う。As shown in FIG. 3, when recording, or dubbing, an image being played back on a PAL VTR 1 on a PAL/NTSC VTR 2, a PAL/NTSC VTR 1 is used.
R2 automatically determines that a PAL system video signal is being input, switches the internal mode to PAL mode, and performs a recording operation.
このシステム判別は、隣接している垂直同期信号間(フ
ィールド間)の水平同期信号数が、PALでは625/
2、NTSCでは525/2とNTSCの方が少ない点
を利用して、水平同期信号のカウント数が予め設定した
値よりも大きければPAL、少なければNTSCとして
判別を行っている。This system determination is performed when the number of horizontal synchronization signals between adjacent vertical synchronization signals (between fields) is 625/
2. Taking advantage of the fact that NTSC is smaller than 525/2, if the horizontal synchronizing signal count is larger than a preset value, it is judged as PAL, and if it is less, it is judged as NTSC.
ところが、PAL用VTR1においてポーズ釦を操作し
た場合、第4図に示すように、このポーズ釦操作による
ポーズ信号Aが、本来の垂直同期信号Bの直前に挿入さ
れてPAL/NTSC用VTRZ側に送られる。However, when the pause button is operated on the PAL VTR 1, the pause signal A resulting from the pause button operation is inserted immediately before the original vertical synchronization signal B and sent to the PAL/NTSC VTRZ side. Sent.
この場合は、PAL/NTSC用VTRZ側のシステム
判別が、信号A、Hの立上り間の水平同期信号数T1や
T2で行なわれるようになる。しかし、ここでカウント
される水平同期信号数T1、T2は信号Aがない場合の
カウント水平同期信号数(=T I +T 2)よりも
少なくなり、よって、NTSCの信号と誤判別して正常
な録画が行われなくなるという問題がある。In this case, the system determination on the PAL/NTSC VTRZ side is performed based on the number of horizontal synchronization signals T1 and T2 between the rising edges of the signals A and H. However, the number of horizontal synchronization signals T1 and T2 counted here is smaller than the number of horizontal synchronization signals counted in the absence of signal A (=T I +T 2), and therefore, it is misidentified as an NTSC signal, resulting in normal recording. The problem is that it will no longer be done.
本発明はこのような点に鑑みてなされたものであり、そ
の目的は、上記したようにポーズ操作をした場合でも、
正しいシステム判別が行われるようにすることである。The present invention has been made in view of these points, and the purpose is to
The purpose is to ensure that correct system discrimination is performed.
このために本発明は、PAL信号とNTSC信号を垂直
同期信号間に含まれる水平同期信号の数により自動判別
する判別装置において、上記垂直同期信号のパルス幅を
拡張するワンショトマルチを接続し、上記垂直同期信号
の直前に含まれるポーズ信号を除去した。To this end, the present invention provides a discrimination device that automatically discriminates between PAL signals and NTSC signals based on the number of horizontal synchronization signals included between vertical synchronization signals, in which a one-shot multiplier for expanding the pulse width of the vertical synchronization signal is connected, The pause signal included immediately before the vertical synchronization signal was removed.
以下、本発明の実施例について説明する。第1図はその
一実施例のワンショトマルチの回路を示す図である。3
は既に波形成形された垂直同期信号が入力する入力端子
であり、ここに入力した信号はトランジスタQ1をオン
/オフする。そして、そのトランジスタQlからの信号
が、抵抗R1、R2、ダイオードD1、コンデンサC1
からなる積分回路4に入力する。そして、この積分回路
4からの出力が、トランジスタQ2で反転されてシステ
ム判別回路に転送される。Examples of the present invention will be described below. FIG. 1 is a diagram showing a one-shot multi circuit according to one embodiment. 3
is an input terminal to which a vertical synchronizing signal that has already been waveform-shaped is input, and the signal input here turns on/off the transistor Q1. Then, the signal from the transistor Ql is transmitted through the resistors R1, R2, the diode D1, and the capacitor C1.
The signal is input to an integrating circuit 4 consisting of the following. Then, the output from the integrating circuit 4 is inverted by the transistor Q2 and transferred to the system discrimination circuit.
さて、入力端子3から垂直同期信号Aのパルスが入力す
ると、この信号は積分回路4で積分されるが、この積分
回路4は充電時定数T a 、放電時定数Tbが、
Ta =R1xCI
Tb=R2XC1
であり、R1<R2に設定されて、
Ta<Tb
である。即ち、この第1図に示すワンショトマルチは入
力する垂直同期信号のパルス幅を所定のパ 1ルス幅に
拡張する。Now, when a pulse of the vertical synchronizing signal A is input from the input terminal 3, this signal is integrated by the integrating circuit 4, and this integrating circuit 4 has a charging time constant Ta and a discharging time constant Tb, Ta = R1xCI Tb = R2XC1, R1<R2, and Ta<Tb. That is, the one-shot multiplexer shown in FIG. 1 expands the pulse width of the input vertical synchronizing signal to a predetermined pulse width.
従って、その上記放電時定数Tbをポーズ信号Aと垂直
同期信号Bとの間隔T1以上に設定しておけば、連続し
て2個のパルスA、Bが人力すると、トランジスタQ2
のコレクタから得られる信号は、第2図に示すように一
体化されたパルス信号Cとなる。Therefore, if the above-mentioned discharge time constant Tb is set to the interval T1 or more between the pause signal A and the vertical synchronization signal B, then when two pulses A and B are continuously applied manually, the transistor Q2
The signal obtained from the collector becomes an integrated pulse signal C as shown in FIG.
このパルス信号Cは垂直同期信号Bとその周期が同じで
あり、よってこの信号をシステム判別回路に送れば、ポ
ーズ信号Aの影響を受けることなく、正常にPALの判
定が行われるようになる。This pulse signal C has the same period as the vertical synchronizing signal B, so if this signal is sent to the system discrimination circuit, PAL determination will be performed normally without being affected by the pause signal A.
以上から本発明によれば、PAL用VTRからの再生信
号をPAL/NTSC用VTRで録画する際に、PAL
用VTRにポーズをかけた場合であっても、そのポーズ
操作の影響を何等受けることなく、PAL/NTSC用
VTRが正常にそのPAL信号を自動判別するようにな
るという特徴がある。As described above, according to the present invention, when recording a playback signal from a PAL VTR with a PAL/NTSC VTR, the PAL
Even if a pause is applied to a PAL/NTSC VTR, the PAL/NTSC VTR automatically discriminates the PAL signal normally without being affected by the pause operation.
第1図は本発明の一実施例のワンショットマルチ回路の
回路図、第2図は動作のタイミングチャート、第3図は
ダビングの説明図、第4図は誤判別発生の説明図である
。
1・・・PAL用VTR,2・・・PAL/NTSC用
VTR13・・・垂直同期信号入力端子、4・・・積分
回路。
代理人 弁理士 長 尾 常 明FIG. 1 is a circuit diagram of a one-shot multi-circuit according to an embodiment of the present invention, FIG. 2 is an operation timing chart, FIG. 3 is an explanatory diagram of dubbing, and FIG. 4 is an explanatory diagram of occurrence of misjudgment. 1...VTR for PAL, 2...VTR13 for PAL/NTSC...Vertical synchronization signal input terminal, 4...Integrator circuit. Agent Patent Attorney Tsuneaki Nagao
Claims (2)
含まれる水平同期信号の数により自動判別する判別装置
において、 上記垂直同期信号のパルス幅を拡張するワンショトマル
チを接続し、上記垂直同期信号の直前に含まれるポーズ
信号を除去したことを特徴とするPAL/NTSCシス
テム判別装置。(1) In a discrimination device that automatically discriminates PAL signals and NTSC signals based on the number of horizontal synchronization signals included between the vertical synchronization signals, a one-shot multiplier that expands the pulse width of the vertical synchronization signal is connected, and the vertical synchronization signal is A PAL/NTSC system discriminator characterized in that a pause signal included immediately before a signal is removed.
ポーズ信号発生から上記垂直同期信号終了までの期間よ
りも長いことを特徴とする特許請求の範囲第1項記載の
PAL/NTSCシステム判別装置。(2) The PAL/NTSC system discriminator according to claim 1, wherein the one-shot multi output pulse width is longer than the period from the generation of the pause signal to the end of the vertical synchronization signal. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63120749A JPH01291591A (en) | 1988-05-19 | 1988-05-19 | Pal/ntsc system discriminator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63120749A JPH01291591A (en) | 1988-05-19 | 1988-05-19 | Pal/ntsc system discriminator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01291591A true JPH01291591A (en) | 1989-11-24 |
Family
ID=14794034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63120749A Pending JPH01291591A (en) | 1988-05-19 | 1988-05-19 | Pal/ntsc system discriminator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01291591A (en) |
-
1988
- 1988-05-19 JP JP63120749A patent/JPH01291591A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0832536B2 (en) | Bus and interface system for consumer digital equipment | |
US5841987A (en) | Simple bus and interface system for consumer digital equipment | |
JPH01291591A (en) | Pal/ntsc system discriminator | |
US4694256A (en) | Compensation circuit for pulse signals | |
JPS6128188B2 (en) | ||
US5646700A (en) | Simultaneous write/read control apparatus for first-in-first-out memory | |
US5231509A (en) | Burst gate pulse generating device for use in image signal reproducing system | |
JPS59193680A (en) | Automatic discriminating system of television broadcast system | |
JP3046920B2 (en) | VCR recording circuit with snow noise removal function | |
JPH067629Y2 (en) | Sync detection circuit by pulse width | |
US5175620A (en) | Synchronism detecting circuit utilizing pulse width | |
US5784121A (en) | Vertical synchronisation signal detector | |
JP2596183B2 (en) | Vertical blanking pulse output device | |
JPH0134513B2 (en) | ||
JPH0441659Y2 (en) | ||
JPS63308757A (en) | Magnetic recording and reproducing device | |
JPH024071B2 (en) | ||
EP0469241B1 (en) | Circuit for controlling delay time between luminance and chrominance signals | |
JP2725851B2 (en) | Video display device | |
JP3011450B2 (en) | Vertical synchronization frequency discrimination circuit | |
JPS60130971A (en) | Synchronizing signal separating circuit | |
JPS6018077A (en) | Processing circuit of field signal | |
JPS61274479A (en) | Video signal processor | |
JPH0584717B2 (en) | ||
JP3662997B2 (en) | Video control signal output device between digital encoder and frame buffer |