JPH024071B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a PCM system that uses a video tape recorder (hereinafter referred to as VTR) or a part thereof to record and play back PCM signals that conform to standard television signals.
Regarding the continuous muting counter circuit used in recording and playback devices, when the underwater synchronization signal in the PCM signal and the data signal are different by more than a predetermined number of bits, a signal for mutating is generated, and this signal is used to control the PCM. In addition to controlling the opening and closing of the signal reproduction system, if the horizontal synchronization signal and the data signal deviate by a predetermined bit or more twice or more in a row, the muting signal is activated only during the first horizontal period. By occurring,
This prevents the PCM signal reproduction system from being opened and closed continuously.

An embodiment of the present invention will be described below with reference to the drawings.

First, the consumer-use
PCM encoder/decoder shown in the film
The PCM signal format will be explained with reference to FIGS. 1 and 2.

Fig. 1a shows the signal arrangement for the odd field, and Fig. 1b shows the signal arrangement for the even field, each with a vertical synchronizing signal of 3H (H is one horizontal signal period),
It is equipped with equalization pulse signals of 3H each before and after that, a 1H control block, and a 245H data block.
The equalization pulse signal appears after 75H from the end of the PCM data signal, or after 7H from the end of the PCM data signal in the case of the even field in FIG. 1b. FIGS. 1c and d show details of the vertical synchronizing signal and equalization pulse signal in FIGS. 1a and 1b, respectively.

On the other hand, Figure 2a shows the bit-by-bit signal arrangement of the horizontal signal part of the PCM signal format, in which a 13-bit horizontal synchronizing signal is placed 5 bits apart after the 4-bit white reference signal, and then 13
A 4-bit ("1010") data synchronization signal is placed with a gap, followed by a 128-bit PCM data signal, and then a 1-bit gap with the next white reference signal. Therefore, Figure 2a
As shown in Figure 3, one horizontal signal section consists of 168 bits.

Figures 2b and c are shown in Figure 2a, respectively.
It shows a data signal obtained by slicing a PCM signal at level k and a synchronization signal obtained by slicing it at level 1. Note that the data signal includes a data synchronization signal and a PCM data signal.

FIG. 3 shows the overall structure of an embodiment using the present invention, and FIGS. 4 to 18 show the specific structure of each block in FIG. 3. Figures 3 to 18 below
The configuration of this embodiment will be explained with reference to the drawings.

In Fig. 3, A is an input terminal to which the data signal shown in Fig. 2b is applied, B is an input terminal to which the synchronization signal shown in Fig. 2c is applied, and C is an input terminal to which the master clock signal is applied. It is. A clock signal generating circuit 17 generates a clock signal H for punching the PCM signal based on the data signal applied to the input terminal A and the master clock signal applied to the input terminal C. Reference numeral 18 denotes a data signal generation circuit which punches out a data signal applied to input terminal A in response to clock signal H and generates a digitized data signal D; 19 indicates a synchronization circuit which is applied to input terminal B in accordance with clock signal H; This is a sync signal generation circuit that punches out a signal and generates a digitized sync signal E.

The data signal delay circuit 1 receives a data signal D and a clock signal H as input, and delays the data signal D by a predetermined bit.The output signal is sent via an output terminal F to a subsequent digital signal processing section (not shown). ). As shown in FIG. 4, this data signal delay circuit 1 consists of continuously connected 8-bit shift registers 1-1, 1-2, 1-3, 1-4.
Each shift register can be configured with 1-1
By applying the clock signal H to the clock terminals CK of the clocks 1-4, the data signal D is delayed by a predetermined bit.

The synchronizing signal delay circuit 2 receives a synchronizing signal E and a clock signal H, and delays the synchronizing signal E by a predetermined bit, and its output signal I is supplied to a horizontal synchronizing signal generating circuit 8, which will be described later. The synchronizing signal delay circuit 3 delays the output signal J of the horizontal synchronizing signal generating circuit 8 by a predetermined bit based on the output signal J of the horizontal synchronizing signal generating circuit 8 and the clock signal H.

These synchronization signal delay circuits 2 and 3 are connected to 8-bit shift registers 2-1 and 2, as shown in FIG.
-2, 2-3 and D-type flip-flop 2-4, 3
-1 are connected continuously, each shift register 2-1 to 2-3, and a D-type flip-flop 2.
By supplying the clock signal H to the clock terminal CK of the D-type flip-flops 2-4 and 3-1 and the synchronization signal E to the AB input terminal of the shift register 2-1, The output signal K of the output signal I (I ₁ , I ₂ , and I ₃ ) is output from the terminal. In this embodiment, two synchronizing signal delay circuits 2 and 3 are used, but they collectively constitute one synchronizing signal delaying means. In short, data signal delay circuit 1, synchronization signal delay circuit 2,
It is sufficient to make the number of delay stages of 3 equal to each other and to delay the data signal and the synchronization signal by the time necessary for error correction of the horizontal synchronization signal, which will be described later.

The muting control circuit 4 inputs the horizontal synchronization signal K obtained from the output signal J of the horizontal synchronization signal generation circuit 8 via the synchronization signal delay circuit 3, and is connected to the horizontal synchronization signal generation circuit (a mutating control signal generation circuit as described later). The above-mentioned input signal K is controlled intermittently based on the muting control signal L outputted by 8), and its output signal is led to the subsequent digital signal processing section via the output terminal G. This is used for reproducing the data signal from the output terminal F mentioned above. This muting circuit 4 interrupts the erroneous horizontal synchronizing signal to prevent it from being transmitted to the digital signal processing section when the position of the horizontal synchronizing signal has significantly changed from its normal position relative to the data signal. Control and be right at other times. Alternatively, it controls so that the correctly corrected horizontal synchronizing signal is transmitted to the digital signal processing section.

This muting circuit 4, as shown in FIG.
NOR gate 4-1 with inputs (L ₁ , L ₂ , L ₃ )
, an inverter 4-2 that inverts its output, and an AND gate 4-3 that receives the synchronization signal K output from the synchronization signal delay circuit 3 and the output signal of the inverter 4-2, and each gate 4-1,4
-2, 4-3 output signals G, J, and M.

The data signal switching circuit 5 is connected to the data zero detection circuit 1
4 output signal P, horizontal synchronization signal width detection circuit 15 output signal 0, continuous muting counter circuit 1
The output signal N of 6 controls the opening and closing of the data signal D. Specifically, as shown in Figure 7
It is composed of a NOR gate 5-1 and an OR gate 5-2, and if any one of the above output signals P, O, and N is not satisfied, the NOR gate 5-1 will not open and the data signal D will not pass through. to control. In other words, as is clear from Figure 2 a, b, and c, if the PCM signal format is correct, the horizontal synchronization signal width (interval i to j) is 13 bits, and the width of the interval from the start i to the data synchronization signal is 13 bits. Since all the data are zero, this is applied to the horizontal synchronization signal width detection circuit 1.
5. Detected by the data zero detection circuit 14, and if these are in accordance with the format, the data signal opening/closing circuit is opened to allow the data signal D to pass, and if it is not correct, it is shut off, thereby detecting the data synchronization signal in the subsequent stage. It is something that gates whether or not.

The data zero detection circuit 14, the horizontal synchronization signal width detection circuit 15, and the continuous muting counter circuit 1
Reference numeral 6 constitutes a PCM signal format detection means for detecting whether or not the input PCM signal conforms to the PCM signal format based on the input data signal and synchronization signal, and the circuits 14 and 15 , 16 are Figs. 16 and 17, respectively.
It can be configured with a circuit as shown in FIG.

In Figure 16, 14-1 is a monostable multivibrator, R _14-1 and C _14-1 are resistors and capacitors that determine its time constant, and 14-2 and 14-3 are ORs.
The gate and NOR gate 14-4 is a D-type flip-flop, and 14-5 and 14-6 are NOR gates forming the flip-flop.

In Figure 17, 15-1 is a monostable multivibrator, R ₁₅ - ₁ and C ₁₅ - ₁ are resistors and capacitors that determine their specific numbers, 15-2 is an inverter, and 15-3 and 15-4 are OR gates. and NOR gate, 15-5 is a D-type flip-flop, 15-
6, 15-7 constitute a flip-flop
It is a NOR gate.

In Figure 18, 16-1 is an AND gate,
16-2 and 16-3 are monostable multivibrators, and _R16-1 , _C16-1 , _{R16-2 ,} and _C16-2 are resistors and _{capacitors that} determine _their time constants.

The data synchronization signal detection circuit 6 (Fig. 3) detects the data synchronization signal (“1010”) in the output signal Q of the data signal switching circuit 5, and specifically, as shown in Fig. 8. It can be constructed of D-type flip-flop circuits 6-1 to 6-7 and a NOR gate 6-4.

A bit determination circuit 7 that determines the relative relationship between the horizontal synchronization signal and the data synchronization signal receives a clock signal H,
With the data synchronization signal R output from the data synchronization signal detection circuit 6 and the horizontal synchronization signal T output from the horizontal synchronization signal detection circuit 13 as input, between the horizontal synchronization signal and the data synchronization signal (i to m or j to m) This is to determine whether or not the number of bits is correct, and if so, to what degree the number of bits is incorrect. Specifically, it can be constructed by a circuit as shown in FIG.

In Figure 9, 7-1 is an OR gate, 7-
2, 7-3 is a NOR that constitutes a flip-flop
Gate, 7-4 is monostable multivibrator,
_R7-1 , _C7-1 are the resistors and capacitors _that determine the time constant, 7-5 is _the NOR gate, 7-6 to 7-1
0 is a D-type flip-flop. These D-type flip-flops 7-6 to 7-10 constitute a counter, and the counter results are outputted from _U1 to _U8 and transmitted to the horizontal synchronizing signal generating circuit 8.

The horizontal synchronization signal generating circuit 8 generates a horizontal synchronization signal J based on the determination result of the determination circuit 7, and generates a correct horizontal synchronization signal J when it is correct, and generates a correctly corrected horizontal synchronization signal J when it is incorrect. If the correctable range is set to ±1 bit, the circuit can be constructed as shown in FIG. Incidentally, as described above, in this embodiment, the horizontal synchronizing signal generating circuit 8 also has the function of generating the muting control signal L (L ₁ , L ₂ , L ₃ ).

In Figure 10, 8-1, 8-2, 8-3
inputs the signal U (U ₁ to _{U 8} ) from the determination circuit 7, and each horizontal synchronization signal is +1 from the correct position.
A NOR gate detects when the bit is off, when it is correct (when it is off by 0 bit), and when it is off by -1 bit. 8-4 to 8-6 are D-type flip-flops, and 8-7 and 8-8 are NOR gate and
OR gate, 8-9 is a monostable multivibrator, _R8-1 , _C8-1 are resistors and capacitors that determine the time constant, _8-10 to 8-13 are tristate gate circuits, and 8-14 is an inverter circuit _. be.

The control block detection circuit 9 receives the clock signal H, the data signal D, and the output Y of the vertical synchronization signal equalization pulse signal control circuit 12, which will be described later, and detects the control block shown in FIG. Specifically, it can be constructed with a circuit as shown in FIG. In FIG. 11, 9-2 to 9-5, 9-9 are D-type flip-flops, 9-11 is a 4-bit shift register, 9-12 is a monostable multivibrator,
_R9-1 , _C9-1 are the resistors and capacitors that determine the time constant, 9-1 is _the OR gate, 9-6 _, 9-7
is an exclusive OR gate, and 9-6 is a NOR gate.

The data block control circuit 10 receives the output W of the control block detection circuit 9, the clock signal H,
Vertical synchronization signal X from vertical synchronization signal detection circuit 11
is input, and outputs the control signal V of the horizontal synchronization signal generation circuit 8 and the control signal Z of the control circuit 12, as shown in FIG.
2, OR gate 10-3, and inverter 10-
4 and a D-type flip-flop 10-5.

Since the horizontal synchronizing signal to be corrected is only that of the data block shown in FIG. 1, the control block detection circuit 9 and data block control circuit 10 perform correction processing of the horizontal synchronizing signal only in the data block. This is provided to prevent malfunctions by not performing correction processing during this period.

The vertical synchronization signal detection circuit 11 detects the vertical synchronization signal shown in FIG. 1, and can be specifically constructed by a circuit as shown in FIG. 13. In Fig. 13, 11-1 is a 4-bit counter, 11-
3, 11-6 is a D-type flip-flop, 11-5
is a monostable multivibrator, R ₁₁ - ₁ and C ₁₁ - ₁ are the resistors and capacitors that determine its time constant, and the length of the vertical synchronization signal section shown in Figure 1 c and d is detected and the detection output This outputs the following.

The vertical synchronization signal equalization pulse signal control circuit 12 includes:
It detects the vertical synchronization signal and equalization pulse signal shown in FIG. 1, and outputs a signal Y for controlling the control block detection circuit 9 and horizontal synchronization signal detection circuit 13, specifically, as shown in FIG. It can be constructed with a circuit like this. 12-1, 12 in Figure 14
-2 is a NOR gate that constitutes a flip-flop,
12-3 is _a monostable multivibrator, _12-1 ,
C ₁₂ - ₁ is the resistor and capacitor that determines its time constant.

The horizontal synchronization signal generation circuit 13 detects the horizontal synchronization signal shown in FIG. 2. Specifically, as shown in FIG. The horizontal synchronization signal detection output T is output from the OR gate 13-4 to the judgment circuit 7, the data zero detection circuit 14, and the inverter 13-3.
The signal is supplied to the horizontal synchronizing signal width detection circuit 15 and the horizontal synchronizing signal generating circuit 8.

Next, the operation of the above embodiment will be explained.

The data signal and synchronization signal applied to input terminals A and B are supplied to a data signal delay circuit 1 and a synchronization signal delay circuit 2, respectively, and are delayed for a predetermined time.

On the other hand, the data signal D is connected to the data signal switching circuit 5.
It is also supplied to NOR gate 5-1. and PCM
If the signal format detection means 14 to 16 determine that the signal is in accordance with the PCM signal format, their outputs N, O, and P are all "0".
Then, the output of OR gate 5-2 becomes "0". Therefore, the NOR gate 5-1 opens and the data signal D is output as the output Q. When any one of N, O, and P becomes “1”, NOR gate 5
-1 is closed and the data signal D is cut off.

The output Q of the data signal switching circuit 5 is supplied to the D-type flip-flop 6-1 of the data synchronization signal detection circuit 6, as shown in FIG. gate 6
-4 detects the data synchronization signal ("1010") in the input data signal Q and outputs the data synchronization signal R.

This data synchronization signal R is supplied to the OR gate 7-1 of the determination circuit 7 shown in FIG. period of
By opening the NOR gate 7-5 and guiding the clock signal H to the counters 7-6 to 7-10, the period from the horizontal synchronization signal T to the data synchronization signal R is counted. The counter result is U of U ₁ to _{U 8}
stored in the signal. Note that the ξ signal is a signal generated after a certain period from the horizontal synchronizing signal T, that is, after a period when the data synchronizing signal of "1010" is to be detected, and is a signal for resetting the counters 7-6 to 7-10.

The output signal U of the bit determination circuit 7 is supplied to U ₁ to _{U 8} of the horizontal synchronization signal generation circuit in FIG.
When the horizontal synchronization signal is shifted by -1 bit with respect to the regular PCM format, the NOR gate 8
1, the case where the horizontal synchronizing signal is a normal horizontal synchronizing signal is detected by the NOR gate 8-2, and the case where the horizontal synchronizing signal is shifted by +1 bit from the normal PCM format is detected by using the NOR gate 8-3. of
The outputs of NOR gates 8-1 to 8-3 are stored in flip-flops 8-4 to 8-6 using signal S shown in FIG. 9 as a clock signal. Note that the signal S is a signal that changes from "0" to "1" when the data synchronization signal R is applied.

To explain this operation in more detail, for example -1
If the bit is shifted, the output of NOR gate 8-1 becomes "1", and the output of NOR gate 8-2, 8-3 becomes "1".
Since the output of flip-flop 8 is “0”,
The output of -4 becomes "0", the tristate gate circuit 8-10 opens, and _I1 is output to J.
Naturally, in this case, the output of flip-flop 8-5
Q ⁵ , the output of flip-flop 8-6 is “1”
Therefore, tristate gate circuit 8-1
1, 8-12 are closed. Note that the fact that the tristate gate circuits 8-10 to 8-13 are closed means that the outputs of these tristate gates are floating lines. If there is a -1 bit shift, as shown in FIG. 6, the input signal _L1 of the NOR gate 4-1 is "1", so M is "0" and therefore γ is "1".
Therefore, the tristate gate circuit 8-13 is closed. If the difference is 0 bit due to the same operation (if correct), I ₂ is output to J, and +1
If there is a bit shift, _I3 is output to J.
NOR gate 8-7 and OR gate 8-8 generate signals to be applied to the clear terminals and preset terminals of flip-flops 8-4 to 8-6.

The output signal J of the horizontal synchronization signal generation circuit generated in this manner is applied to J of the synchronization signal delay circuit 3 shown in FIG. is output as This signal K is the AND gate 4-3 in Figure 6.
is applied to one input terminal of On the other hand, the signals L ₁ , L ₂ , and L ₃ shown in FIG. 10 are applied to the input terminal of the NOR gate 4-1 of the muting circuit 4 shown in FIG. 6. Here, one of L ₁ , L ₂ , and L ₃ is “1”
When the relationship between data and synchronization signal is ±1
If it is wrong within a bit or is correct, its output M will be "0". Then, γ is "1", the AND gate 4-3 is opened, the signal K is outputted as the signal G as it is, and the corrected or correct horizontal synchronizing signal is outputted as the signal G as is. If L ₁ , L ₂ , and L ₃ are all “0”, that is, the relationship between the data and the synchronization signal is off by ±2 bits or more, then M is “1” and γ is “0”.
Therefore, the signal G is always "0" and the signal K is muted.

OR of control block detection circuit 9 shown in FIG.
The data signal D from the data signal generation circuit 18 and the output signal Y from the vertical synchronization signal and equalization pulse signal control circuit 12 are input to the gate 9-1.
It is included in the control block as determined by the PCM format standard. The “1100” bit pattern is transferred to the flip-flop 9-2 based on the clock signal H.
~9-5, gate circuits 9-6 to 9-8, flip-flop 9-9, and gate circuit 9-9, the counter 9-11 repeats the "1100" pattern, and the output is detected. Input to monostable multivibrator 9-12 to obtain output signal W.

FIG. 12 shows the data block control circuit 10, which receives the output signal W of the control block detection circuit 9 described above and the output X of the vertical synchronization signal detection circuit 11 described later, and controls the NOR gates 10-1 and 10.
- Operate the flip-flop consisting of 2. V ₁ and V ₂ are the output signals of the OR gate 10-3, and when the vertical synchronization signal is input, X becomes "1",
V ₁ becomes “1” and V ₂ becomes “0”. This state continues until the signal W is applied, and the horizontal synchronizing signal generating circuit 8 shown in FIG. 10 operates only in the PCM data signal portion of the PCM signal.

The vertical synchronization signal detection circuit 11 shown in FIG.
Using the clock signal H and the synchronization signal B applied to the input terminal B (this may be the output signal E of the synchronization signal generation circuit 19), the "0" period of the vertical synchronization signal shown in FIG. The vertical synchronization signal is detected by counting. 11-1 is a "0" period counter, a monostable multivibrator 11-5, and a D-type flip-flop circuit 11.
-6, the configuration is such that once a vertical synchronizing signal is detected, the detection is closed by the output of the gate 11-7.

The vertical synchronization signal and equalization pulse signal control circuit 12 shown in FIG.
The output signal X of the data block control circuit 9 and the output signal of the data block control circuit 9 are inputted to generate the constant time signal Y at the input terminal of the signal X.

The horizontal synchronization signal detection circuit 13 shown in FIG.
The output signal of the OR gate 13-1, which receives the above-mentioned signal Y and the synchronization signal E, is sent to the flip-flop 13.
-2, the horizontal synchronizing signal is counted using the clock signal H, and a horizontal synchronizing signal detection output T is generated. Note that during the data block period, the signal Y becomes "0" and no counting is performed.

The data zero detection circuit 14 shown in FIG. 16 operates the monostable multivibrator 14-1 with the horizontal synchronization signal detection output T, and outputs the output from the monostable multivibrator 14-1 up to the m1 bit position shown in FIG. However, during that period, when the data is zero due to the data signal E and clock signal H, the OR
The output of the gate 14-2 is set to "0", and the output Q of the D-type flip-flop 14-4 is set to "0". Thereafter, a data synchronization signal detection signal ξ is applied from the determination circuit 17 shown in FIG. As a result, as mentioned above, if the data is zero from the horizontal synchronization signal detection output T to the determination circuit output, the output P will be "0", and if there is a part where the data becomes "1" during that period, The output Q of the D-type flip-flop 14-4 becomes "1", and the output P becomes "1".

Horizontal synchronization signal width detection circuit 15 shown in FIG.
is, by monostable multivibrator 15-1,
The output of the monostable multivibrator bar 1 is set to "0" from the time when the horizontal synchronization signal detection output T is generated until the period shown by j in FIG. 2, and during that period, the synchronization signal E is
and clock signal H to OR gate 15-3, NOR
The voltage is applied to the gate 15-4. If the period from T to j is “0”, the D-type flip-flop 1
The D input of 5-5 becomes "0", and the output 0 becomes "0" while the signal ξ is applied.

On the other hand, if the width of the horizontal synchronizing signal during the period from T to j is insufficient and is "1", the D input of the D flip-flop 15-5 becomes "1",
Output 0 becomes "1". In addition, here, from T to j
is detected as the width of the horizontal synchronization signal, but
There is actually no problem in setting it several bits shorter than j.

The continuous mutating counter circuit 16 shown in FIG. 18 starts the monostable multivibrator 16-3 about one horizontal period after the mutating control signal M from the mutating circuit 4 shown in FIG. 6 is applied as "1". Set the output to “0”. As a result, the output N becomes "0" in the next horizontal period. Therefore, even if the muting control signal M from the mutating circuit 4 is "1" for two consecutive periods, the signal N is "1" only for the first horizontal period.
However, it becomes "0" in the next horizontal period. That is, this continuous muting counter circuit 16
is for controlling the data signal switching circuit 5 to open based on the muting control signal M from the mutating circuit 4 so that the data signal switching circuit 5 does not continuously interrupt the data signal D.

In the above embodiment, correction is performed when there is a deviation of ±1 bit between the horizontal synchronization signal and the data synchronization signal, and muting is applied when the deviation is ±2 bits or more. The number of NOR gates 81 to 8-3 is increased, and D-type flip-flops 8-4 to 8-6 are increased accordingly.
By increasing the number of bits, it is possible to easily correct a deviation of ±2 bits or more. Since such circuit modifications are obvious to those skilled in the art, detailed explanation will be omitted here.

In addition, in the above embodiment, a PCM signal compliant with a 525-line NTSC standard television signal was explained, but a 625-line PAL/
Compliant with standard SECAM television signals
It goes without saying that the same method can be applied to PCM signals as well.

As described above, the present invention inputs the muting control signal that is output when the horizontal synchronization signal and the data synchronization signal in the PCM signal deviate by a predetermined number of bits or more to the gate circuit, and also inputs the muting control signal to the gate circuit. is delayed by a predetermined horizontal period and then added to the gate circuit to close the gate circuit. Therefore, if the horizontal synchronization signal and the data signal are deviated by a predetermined number of bits or more more than once. Even in the case of continuous operation, the mutating control signal can be outputted from the gate circuit only during the first horizontal period, and the mutating control signal can be cut off during the subsequent predetermined horizontal period. For this reason, when using the above mutating control signal to control the opening/closing of a data signal switching circuit inserted into a data signal transmission line in a PCM signal, for example, the data signal is cut off for the first horizontal period, and the subsequent horizontal period is The data signal can be prevented from being blocked, and the unblocked data signal can be used for further detection or control.

[Brief explanation of drawings]

Figures 1 a to d and Figures 2 a to c are diagrams showing the format of the PCM signal, Figure 3 is a block diagram showing one embodiment of the present invention, and Figures 4 to 18 are each part of Figure 3. FIG. DESCRIPTION OF SYMBOLS 1... Data signal delay circuit, 2, 3... Synchronization signal delay circuit, 4... Muting circuit, 5... Data signal opening/closing circuit, 6... Data synchronization signal detection circuit, 7...
Judgment circuit, 8...Horizontal synchronization signal generation circuit and muting control signal generation circuit, 9...Control block detection circuit, 10...Data block control circuit, 11...
Vertical synchronization signal detection circuit, 12...Vertical synchronization signal, equalization pulse signal control circuit, 13...Horizontal synchronization signal detection circuit, 14...Data zero detection circuit, 15...Horizontal synchronization signal width detection circuit, 16...Continuous muting counter circuit , 17... Clock regeneration circuit, 18... Data signal generation circuit, 9... Synchronization signal generation circuit.

Claims (1)

[Claims] 1. A gate circuit to which a muting control signal is applied during a period when a horizontal synchronization signal and a data synchronization signal in a PCM signal conforming to a standard television signal differ by a predetermined number of bits or more, and a gate circuit to which a muting control signal is applied, and a delay circuit that delays a horizontal period, and by opening and closing the gate circuit with the output of the delay circuit, the muting control signal is output from the gate circuit only for the first horizontal period, and the mutating control signal is outputted from the gate circuit for the following predetermined horizontal period. A continuous muting counter circuit for a PCM recording/playback device, characterized in that a muting control signal is cut off.