JPH01291353A - Data transfer controller - Google Patents

Abstract

PURPOSE:To execute the processing of other data even if an input/output device is inputting or outputting the data by providing a buffer memory and executing a data transfer by a DMA and a hand-shake method between the buffer memory and a main CPU and between the buffer memory and the input/output device, respectively. CONSTITUTION:With respect to a DMA control means 14, a data transfer is executed between a main memory 12 and a buffer memory 13, and when a DMA transfer is ended, an input/output control means 16 executes a control of the data transfer by a hand-shake method between the buffer memory 13 and the input/output part 17, and the input/output part 17 inputs and outputs the data. When read or write of all the data of the buffer memory 13 is ended, the input/output control means 16 outputs a signal of a data end to the DMA control means 14. Accordingly, the DMA processing is started again, and the data transfer is executed between the main memory 12 and the buffer memory 13. In such a way, even if an input/output device 15 is inputting or outputting the data, a main CPU 11 can execute the processing of other data without being awaited.

Description

[Detailed description of the invention] [Summary] A memory dedicated to input/output devices is provided, data is transferred with the main CPU using DMA, and data is transferred with a dedicated LSI for controlling the input/output devices using a handshake method. Regarding data transfer controllers that perform A main memory that stores input/output data under the control of a CPU, a buffer anomaly dedicated to input/output, and data transfer between the main memory and the buffer memory directly without going through the main CPU. Data transfer between the DMA control means that performs control, the buffer memory and the input/output device is performed by a handshake method, and when all the data in the buffer memory has been read or written, the DMA control means performs the data transfer using the DMA. and input/output control means for outputting a request signal for data transfer.

[Industrial application field]

The present invention relates to a data transfer control device, and more specifically, a memory dedicated to input/output devices is provided, data is transferred to and from a main CPU by DMA, and a dedicated LSI for controlling input/output devices is provided. The present invention relates to a data transfer control device that transfers data using a handshake method.

[Conventional technology]

Conventionally, many output devices such as microcomputers, such as printers, are equipped with a dedicated LSI (Large Scale Integrated Circuit) such as a one-chip CPU. In such an output device, data transfer control from the main CPU is performed using a handshake interface.

FIG. 5 is a block diagram showing the configuration of a conventional printer. In the same figure, the main CPU has data and control paths connected to a main memory 2 consisting of a memory 2 that stores print data and other data, and a dedicated LSI 3 such as a one-chip C)) U for printer control. connected via line.

The dedicated LS'I 3 transfers data using a hunt shake method and controls the printing device (mechanical part) 4 of the printer.

The control signals that make up the hunt shake method for data transfer in the printer are the 1-1 copy signal (STI3 signal) given from the main CPtJ1 to the dedicated 1-S13, and the dedicated LSI3. main CI)
This is a confirmation signal (8CK signal) given to U1.

FIG. 6 is a timing chart 1 of data transfer using the handshake method. First, the main CPU 14;
Without outputting print data onto the data bus, the STB signal is changed from low level to high level to notify the dedicated LSI 3 that data has been sent.

The dedicated LSI 3 takes in data on the data bus using each STB signal. The person who received the data] -41L
SI 3 changes the CK signal from low level to high level and indicates that data has been received (main CI) U
Let 1 know. The main CPUI resets the output data in response to the ACK signal, and one print data transfer is completed. The printing device 4 performs printing operations under the control of the dedicated LSI 3.

[Problem to be solved by the invention]

However, in conventional output devices such as printers, the data transfer method is a handshake type interface, and the main CPU 1 has to wait until the printing device 4 finishes printing when data is transferred. Therefore, the main CPU 1 could not perform other data processing during that time.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data transfer control device in an input/output device such as a printer, in which a twin CPU can process other data even while data is being input/output.

[Means to solve the problem]

FIG. 1 is a block diagram illustrating the principle of a data transfer control device according to the present invention. In the same figure, 11 is the main CP
U (central control unit), 12 is connected to °ζ main CPU II via a lot line, and is a main memory consisting of a RAM etc. for storing output data and other data; 13 is a buffer memory for storing input/output-only data; 14 is a DMA (DMA) that directly transfers data between the main memory 12 and the buffer memory 13 without going through the main CPU 1.
Direct Memory Access) control means, 15 is an input/output device, 16 is an input/output control means for controlling data transfer between the buffer memory 13 and the input/output section 17 constituting the input/output device 15 using a hunt shake method, and monitors this buffer memory 13. The input/output section ill means outputs a data transfer request signal by DMA to the control means 14 to the DM8 when all the data has been read or written.

61 [Function] In the data transfer control device of the present invention, first, the main CPU
DM to the DMA control means 14 under the control of I1.
When the A process is started, data is transferred between the main memory 12 and the buffer memory 13. D
When the MA transfer is completed, the 8-stage input/output controller 16 performs 1lil control of data transfer between the buffer memory 13 and the input/output unit 17 using a handshake method. The input/output unit 17 inputs and outputs data. Input/output control means 16
When all the data in the buffer memory 13 has been read or written, it outputs a data end signal to the DMA control means 14. As a result, the DMA processing is restarted, and data transfer is performed between the twin memory 12 and the buffer memory 13. Therefore, even if the input/output device 15 is inputting/outputting data, the main CPU 11 can process data without having to wait.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of the data transfer control device according to the embodiment of the present invention. This embodiment uses a printer as an example of an output device. Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals.

In the figure, 11 is a main CPU, 12 is a main memory connected to the main CPU 11 via a lot line for data and control, and includes a RAM for storing output data and other data, and 13 is a main memory for storing output-only data. A buffer memory 14 stores data in the twin memory 12 directly to the buffer memory 13 without going through the main CPU 11.
DMA control means for controlling data transfer; 5 is a printer; The printer 15 includes a switching circuit 21, a printer control section 22 consisting of a dedicated LSI, a signal control section 23, a printing section 24 consisting of mechanical parts, and the like. The switching circuit 21 is a circuit that switches data read from the buffer memory 13 based on a control signal based on a control f word. The printer control section 22 is a section that controls the printing section 24 based on control signals. The signal control unit 23 sends and receives handshake control signals to and from the printer control unit 22, and also sends and receives handshake control signals to and from the buffer memory 1.
3 and outputs a read end signal to the DMA control means 14 when all data has been read. This read end signal becomes a data transfer request signal to the DMA control means 14.

FIG. 3 is a specific circuit diagram configuring a part of the blink control section. In the same figure, reset seso 1-(R
3) The set input terminal of the flip-flop 31 is supplied with a data transfer signal (Rr, Y signal) from the printer control unit 22, and the reset input terminal is supplied with a data transfer request signal (
E'MP signal) is given. Further, the STB signal constituting the handshake signal is applied to the seven-node input terminal of the other RS flip-flop 32 via the inverter 33, and the data confirmation signal (A) is applied to the reset input terminal.
CK (number g) is given via in-hark 34. The respective outputs (Q, η) of the RS flip-flops 31 and 32 are applied to an AND gate 1.35, and the output of this AND gate 35 is applied to a count enable terminal that enables the counter 36 to perform counting. There is. That is, this counter 36 receives the RDY signal, the ACK signal, and the E
The start and end of counting is controlled by the MP signal. The counter 36 is, for example, a 4-pitch counter, and each output is given to a 4-man power or game 1-37 and a 4-man power Nantes gate 38, respectively.

The output of the OR game 1-37 and the output of the Nants gate 38 are the seso I and input α1 of the RS flip-flop 39, respectively.
111 and the input terminal to the recessor 1. That is, the RS flip-flop 39 is set when the output of the counter 36 is other than r0OOJ, and r0OO
It is set when OJ is used. The output of this RS flip-flop 39 is applied to a gate terminal of a gate circuit 40, and opening/closing of the gate is controlled.

Data is applied to the data input terminal of the gate circuit 40 from the Hasofame Shichiri 13 via a data bus, and the output of the gate circuit 40 is sent to the printing unit 24 or the like as print data. Further, the output of the counter 36 is applied to a four-man AND gate 44 via inverters 41, 42, and 43.

In this tend gate 44, the output of the counter 36 is r 0
A high level strobe signal (ST
Inverters 41, 42, and 43 are connected to output the signal B). This STB signal is transmitted to the printer control unit 2.
2, etc., and also to the count input terminal of the counter 45. The output of this counter 45 is given to the buffer memory 13 as read address data. In addition, the output of the force holder 45 is as follows:
The buffer memory 13 is supplied to one input terminal of the comparator circuit 46, and the buffer memory 13 is supplied to the other input terminal of the comparator circuit 46.
The number of set data stored in is given in advance.

When the output of the counter 45 becomes equal to the number of cent data, the comparison circuit 46 sends a data transfer request signal (EMP signal) to the DMA to notify that the reading has been completed.
It is output to the control means 14.

FIG. 4 is a circuit diagram configuring a part of the signal control section of the DMA control means 14. In the figure, the DMA request signal is passed through an inverter 47 to an RS flip-flop 48.
The DMA confirmation signal (heart-MAAC'T signal) from the main CI) Ull is applied to the sensor I input terminal of the main CI. The output signal of each RS flip-flop 48 is a DMA request signal (DMAR
Q signal) is given to the main CPU II.

The operation of the data transfer control device having the above configuration will be explained. First, the operation of DMA transfer will be explained. Main C
The PUII sets information such as a memory transfer start address, number of transferred words, data input/output, etc. in a register (not shown) in the DMA control means 14 using a predetermined initialization program. Next, the DMA control means 14 issues a DMA request signal based on information set in a register or the like. This D
When the MA request signal is accepted by the main CPU II, a DMA confirmation signal is returned to the DMA control means 14, and thereafter print data is transferred from the main memory 12 to the buffer memory 13. When a predetermined data transfer is completed, an interrupt signal is input to the twin CPU II, and the DMA transfer is completed.

Next, the operation on the printer side will be explained. First, DM
When the A transfer is completed and printing is started, the printer control unit 22 gives a transfer start signal to the RS flip-flop 31, and the OR gate 37 and the Nant gate 38 output the counter 3.
During the counting of 6, print data from the buffer memory 13 applied to the gate circuit 40 is output to the pass line.

Further, at this time, the STB signal is output from the AND gate 44 only when the output of the counter 36 becomes roloJ. This STB signal is counted by a counter 45, and each time the S'T'B signal is output, the read address data is incremented and provided to the buffer memory 13. Zunawaji, the print data in the buffer memory 13 is sequentially transferred for 6 hours by the transfer start signal from the printer control unit 22.
Served. When the final read address of the buffer memory 13 is reached, it matches the number of data sent in advance by the comparator circuit 45, and a read end signal (EMP signal) is output from the comparator circuit 45 to the DMA control stage 14. be done. This reading end signal is sent to the impark 47
])
The MA request signal is output to the twin CPU II, and DMA transfer is performed again by the same operation as above.

Therefore, while the printer is printing, the main CP
UII can perform other data processing.

Although the above embodiment has been explained using a printer as an example, the data inputted from a predetermined data input device is sequentially written to the sofa memory, and when all data is written, it is transferred to the main memory by DMA. It is also applicable to devices that transfer data with input/output devices using at least a handshake method.

〔Effect of the invention〕

As explained in detail above, according to the present invention, a buffer memory dedicated to input/output devices is provided, data is transferred with the main CPU using DMA, and data is transferred with a control device dedicated to input/output using a handshake method. By performing the transfer, even if the input/output device is inputting/outputting data, the main CPU can process other data without having to wait.

[Brief explanation of the drawing]

Fig. 1 is a block diagram explaining the principle of the data transfer control device of the present invention, Fig. 2 is a block diagram showing the configuration of the data transfer control device of the embodiment of the present invention, and Fig. 3 is a concrete diagram of the control portion of the printer. 4 is a circuit diagram of the signal control portion of the DMA control means, FIG. 5 is a block diagram showing the configuration of a conventional printer, and FIG. 6 is a timing diagram of data transfer using the conventional handshake method. It is. 11...7420 copies) Ul 12... Main memory, 13... Buffer memory, 14... Control means for DM8, 15... Input/output device, 16... Input/output control means, 17 ... input/output section, 21... switching circuit, 22... printer control section, 23... signal control section, 24... printing section. Patent applicant Fujitsu Toden Co., Ltd.

Claims (1)

[Claims] A main memory (12) that stores input/output data under the control of a main CPU (11), a buffer memory (13) dedicated to input/output, the main memory (12), and a buffer. Memory (13)
A DMA control means (14) directly controls data transfer between the main CPU (11) and the main CPU (11).
), the data transfer between the buffer memory (13) and the input/output device (15) is performed using a handshake method, and when all the data in the buffer memory (13) has been read or written, the DMA control DMA in means (14)
1. A data transfer control device comprising: input/output control means (16) for outputting a data transfer request signal.