JPH01289321A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To improve the error correction capability by providing a software discrimination decoding means receiving an input signal as an analog quantity, and applying error correction by taking the reliability into account and a hardware decision error correction applying hardware decision error correction when correction is disabled by the software deciding/decoding means. CONSTITUTION:A signal is received in a form analog quantity 102 and software deciding/decoding applying error correction by taking the reliability into account is applied and hardware decision error correction is applied if correction is disabled. If a flag output signal 203 shows the presence of an error at the end of hardware decision error correction, the error correction by the software decision is proceeded. In the error correction by the hardware decision, while a syndrome register 201 is being referenced, whether or not one bit is in error is decided by a deciding a circuit of an error pattern calculating circuit 202 and a decision output 207 is sent to a software decision error correction circuit 208 receiving all data strings. After the hardware decision error correction is implemented as to all bits, when the flag output signal 203 shows no error, it is decided that the data string of the software decision error correcting circuit 208 is corrected correctly. Thus, lookover error is reduced.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an error correction circuit widely used in digital transmission or recording, etc., which receives or reproduces a signal as an analog value and performs soft-decision decoding. This invention relates to a circuit that performs error correction.

[Summary of the invention]

In the present invention, when the soft-decision error correction circuit cannot correct an error, the conventional hard-decision error correction circuit corrects the error, thereby further improving the error correction capability.

[Conventional technology]

Conventionally, this type of error correction circuit has adopted a circuit system in which the soft decision result itself is treated as a received signal. For example, in an error correction code that can be decoded by a majority logic element, ^PP (A Po5terioriProbab
ity ) decoding is applicable.

FIG. 2 shows a basic configuration diagram of the APP decoding circuit.

Reference numeral 101 is a digital signal after a conventional hard decision, and is a "0" or "1" signal. 10
2 is an analog signal that is determined as a multi-value signal rather than a binary signal such as O"1 "1". For example, 0, 25
．． 6103.104 indicating a value such as 0.75 is a switch, which switches input signals to 105 and 108 described below. 105 indicates a shift register that stores digital signal +01 and cyclically stores data during error correction; 106 indicates a shift register that stores analog signal 102 similarly to shift register 105 and cyclically stores data during error correction. Indicates a register. however,
This shift register 106 must have a capacity to store multi-level signals.

107 and 108 are feedback lines for storing data cyclically. Reference numerals 109 and 110 indicate parity check sum signals excluding only the first bit to be corrected. However, for the first bit, BO is output as is. Reference numerals 111 and 112 are weight calculators using a parity check sum matrix excluding the first big.

113 indicates a circuit that adds these values.

11B is a determination circuit. Here, fd-Σ(1-211
, 1) ff+, and when this value fd is fd>0,
If Cm-0 is fd<0, Cmi is output.

In this way, conventional circuits do not include error correction circuits based on hard decisions.

[Problems to be Solved by the Invention] Conventional soft-decision error correction circuits have adopted a system in which error correction is performed in response to the analog value of a human-powered digital signal, taking into consideration the reliability of that data.

However, in such a system, if the number of error bits exceeds the correction capability, all errors may not be corrected and some error bits may remain when the correction is completed. Note that if the total number of error bits in this case is less than or equal to the number of error correction bits of this code, error correction using conventional hard decisions can be sufficient to correct the error.

Therefore, in view of the above-mentioned points, an object of the present invention is to propose an error correction circuit that performs hard decision error correction after soft decision error correction, thereby improving error correction capability.

[Means to solve the problem]

The error correction circuit according to the present invention includes a soft-decision decoding means that receives an input signal as an analog value and performs error correction in consideration of its reliability, and hard-decision error correction when the soft-decision decoding means cannot correct the error. and hard-decision error correction means.

(Function) In the present invention, the digital reproduced signal (or received signal, etc.) is not composited only by the conventional hard-decision error correction that judges "0" and "1", but the signal is received as an analog value. After performing soft-decision decoding that performs error correction in consideration of the reliability, if correction cannot be made, hard-decision error correction is performed.

〔Example〕

Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 shows an embodiment of an error correction circuit to which the present invention is applied. 1'01 and 102 in this figure correspond to the numbers in FIG. 2 and indicate hard decision output and soft decision output, respectively. 201
is a syndrome register, which displays the remainder when the input signal string is divided by the generator polynomial. 202 is a circuit that calculates error patterns in correspondence with syndromes. 2
03, the contents of the syndrome register 201 are all “0”
This is a flag output signal indicating whether the syndrome register 201 is “O” or not, and if the contents of the syndrome register 201 are not all “O”, it means that there is an error somewhere.

204 and 205 are exclusive OR circuits, which modify the syndrome register 201 when input data is inverted as a result of error correction. 206 is input hard decision data. 115 is corrected output data shown in the second diagram. 20
7 is a hard-decision error correction output signal determined by the contents of the syndrome register 201. 208 is a soft-decision error correction circuit, which represents the second cap body.

Next, the flow of signals in the first base body will be described.

First, the syndrome register 201 is automatically reset to all "0"s. The hard-decision and soft-decision signals 101 and 102 are input to a soft-decision error correction circuit 208, respectively. At the same time, the hard decision signal 101 is led to the syndrome register, and after all the signal sequences are loaded, the syndrome register 201 is filled with the generator polynomial (
or the remainder of the generator matrix) is displayed. That is, if there is no error in the input signal string 101, the contents of the syndrome register 201 are all "O".

It can be determined from the flag output signal 203 whether there is an error or not. If there is no error, neither the soft-decision error correction circuit 208 nor the hard-decision error correction circuit is operated, and a signal 209 is output. Alternatively, a signal that is the source of signal 101 stored in another register is used.

If there is an error, the soft-decision error correction circuit 208 is operated, and at the same time the contents of the syndrome register 201 are shifted by l bits each time. When error correction is necessary, that is, the correction output signal 115 and the human hard decision data 20
If the contents of 6 are different, the syndrome register 20
Modify the contents of 1. Perform soft decision error correction on all bits.

If the flag output signal 203 indicates that there is an error at the end of soft decision error correction, then hard decision error correction is started. Hard decision error correction is performed by the judgment circuit of the error pattern calculation circuit 202 while referring to the syndrome register 201.
It is determined whether the bit is erroneous or not, and the determination output 207 is sent to the soft-decision error correction circuit 208 containing the entire data string. The syndrome register will also be revised. After performing hard decision error correction on all bits, the flag output signal 203
indicates no error, the soft decision error correction circuit 208
It is determined that the data string of ゜ has been correctly corrected. If the flag output signal 203 indicates that there is an error, it is determined that an error has been detected.

Further, even if the flag output signal 203 indicates no error after inputting the first data string, if soft decision error correction and hard decision error correction are sequentially performed, there is a possibility that missed errors can be reduced accordingly.

This can also be designated as mode switching from the outside.

In Fig. 1, an example of the circuit configuration is shown using an error correction code that can be decoded by a majority logic element, but BCI
It goes without saying that the present invention can also be applied to other error correction codes such as + codes.

It goes without saying that the present invention can also be constructed by the invention of the "correction decoding system".

Furthermore, regarding the soft-decision error correction circuit, A
It goes without saying that the present invention is also applicable to Hartman-Rudolph algorithm, Welton algorithm, Chase algorithm, etc. other than the PP decoding circuit.

〔Effect of the invention〕

In the present invention, a hard-decision error correction circuit can be added to a conventional soft-decision error correction circuit to improve error correction capability. In this case, the data register that is a part of the hard-decision error correction circuit is made to be that of the soft-decision error correction circuit, thereby simplifying the circuit configuration and making it possible to lower the melting point.

Further, in the present invention, two modes can be specified from the outside. In other words, if the syndrome is all “O” in the hard decision data, error correction is not performed,
A mode that reduces processing time and performs soft-decision error correction even when all syndromes are "0",
It is also possible to provide a mode for reducing missed errors.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional soft decision error correction circuit (APP). DESCRIPTION OF SYMBOLS 101... Digital signal, 102... Analog signal, 103... Switch, 104... Switch, 105... Shift register, 106... Shift register, 107... Feedback line, 108
... Feedback line, 109 ... Parity check sum signal, 310 ... Parity check sum signal, 111 ... Weight calculator, 112 ... Weight calculator, 113 ... Addition circuit, 114 ... Judgment circuit, 115... Correction output signal, 201... Syndrome register, 202
... Error pattern calculation circuit, 203 ... Flag output circuit, 204 ... Exclusive OR circuit, 205 ...
・ tJj alistic OR circuit 06 ... Input hard decision data, 207 ... Hard decision error correction output signal, 208 ... Soft decision error correction circuit, 209
... Output signal.

Claims (1)

[Scope of Claims] 1) Soft-decision decoding means that receives an input signal as an analog value and performs error correction in consideration of its reliability, and hard-decision error correction when the soft-decision decoding means cannot correct errors. An error correction circuit characterized by comprising: hard decision error correction means for performing.