JPS62159922A - Error correction coding and decoding device - Google Patents

Abstract

PURPOSE:To attain high speed decoding even when an information bit string is long by constituting a function generator by two function generators and constituting a state holding circuit by a circuit holding a new information bit string and a circuit holding the internal state decided by the past information bit string. CONSTITUTION:A bit string holding circuit 218, a state holding circuit 208, a function generator F209 and a function generator T210 of a decoder have the same function as that provided to a corresponding coder. When the decoder discriminates the past decision to be wrong, the decoder brings the circuits 218, 208 to the past state, extracts a bit string whose decision is estimated to be wrong from the circuit 218 and inputs the bit string to a function generator W205. A reception signal on a line 212 is restored to the past value and the result of decision executed first to the reception signal is fed to a line 214. Then the function generator 205 compares the values on the lines 213, 214, outputs the result of decision seeming to be sure from a selector 207 to the circuit 218 and holds it. In restoring the result to the past state, the past result of decision is restored from the output buffer 203 to the circuit 208 and from the circuit 208 to the circuit 218 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an error correction decoding device that automatically corrects errors occurring in data due to transmission or storage of digital data.

<Prior Art> It is recognized that errors caused by transmission or storage of digital data are often caused by noise on the transmission path or physical defects in the storage medium. Conventionally, in order to avoid the effects of such noise and defects, the data sending side divides the information bit string into several bit strings and converts each bit string according to predetermined rules to add redundancy. After that, it is sent to a transmission path or storage medium, and on the receiving side, errors in each bit string are detected and corrected based on the redundancy of the bit string sent from the transmission path or storage medium. method is adopted.

Convolutional codes and convolutional codes are conventionally well-known and used methods for converting information bit strings and adding redundant bit strings, and for restoring the original information bit string from converted bit strings with redundant bits added. There are methods using tree codes such as trellis codes and methods using sequential decoding algorithms. For details on tree codes and sequential decoding algorithms, see
It is described in detail in the publication ``Coding Theory'' published in 1973.

Of these methods, the method of converting an information bit string and adding a redundant bit string will be briefly described. An error correction encoding device (hereinafter simply referred to as an encoder) is a device that maintains an internal state, such as a shift register. It has a dedicated circuit and changes its internal state in a predetermined manner depending on the input information bit string. When a shift register is used as a circuit for holding an internal state, the internal state is changed by inputting an information bit string to the shift register. On the other hand, the encoder inputs the internal state to a predetermined function generator and outputs a code bit string. If the length of the code bit string (4) is made longer than the information bit string, the above operation is nothing but adding redundancy to the information bit string.

The code bit string output from the encoder passes through the transmission path,
Alternatively, the data is once recorded on a storage medium and reproduced, and then sent to a decoder. The received bit string received by the decoder does not necessarily match the transmitted code bit string due to errors caused by noise on the transmission path or physical defects in the storage medium.

To briefly describe the method of restoring information from a received bit string using a sequential decoding algorithm, an error correction decoding device (hereinafter also simply referred to as a decoder) is a circuit that has the same function as a corresponding encoder (hereinafter referred to as an encoder). For example, if the length of the information bit string is 2 bits, the encoder will have an encoder when all possible bit strings of 00, 01, 10.11 are input to the encoder replica. The duplicate output bit strings are each compared with the received bit string, and the information bit string that provides the output bit string closest to the received bit string is determined to be the transmitted information bit string. As a measure of closeness, a likelihood called Fano likelihood defined by the following equation is generally used.

λ=Jog2(p(ylx)/p(y)) BHere, p(y) is the probability that the received bit string is y, and p(ylx) is the probability that the received bit string is y.
x) is the probability that the decoder receives or receives the received bit string y when the encoded bit string In the sequential decoding algorithm, basically, the information bit string with the largest Fano likelihood is determined as the transmitted information bit string. However, when there is strong noise on the transmission path, there is a possibility that false 9s will occur frequently in the received bit string, and the incorrect information bit string will be determined to be the transmitted information bit string.

If the decoder once makes a wrong decision, the internal state of subsequent encoder copies will be inconsistent with the encoder's internal state, and from then on, even if the decoder tries to find an information bit string with a large Fano likelihood, Since it is difficult to find it, it is possible to detect that an incorrect determination was made in the past. Therefore, in the sequential decoding algorithm, when the decoder becomes difficult to find an information bit string with a large Fano likelihood, it determines that it made an incorrect decision in the past, returns the internal state of the encoder replica to the past state, and then The information bit string with the next highest Fano likelihood after the information bit string selected in is determined to be the transmitted information bit string, and the decoding is slightly adjusted. However, when you try to find the next large information bit string, if it has already been searched and cannot be found,
Return to the previous state and perform the same operation. The exact criteria for determining that a decoder has made incorrect decisions in the past are described in the above document. Note that in the sequential decoding algorithm, decoding is performed through repeated trial and error, so the decoding results once output may be changed later, so the decoding results of the decoder are not output to the outside of the device. When you do this, you need to use a buffer.

Now, an error correction encoding device and an error correction decoding device for encoding and decoding information bit strings as described above were developed by, for example, American George David Forney, Jr.
It can be implemented with a circuit such as that described in U.S. Pat. No. 3,665,396 to R.

<Problems to be Solved by the Invention> However, in the conventional error correction decoding device, the bit string with the largest 7-anonymous likelihood among all possible information bit strings was determined to be the transmitted information bit string. As the length of the information bit string increases, the number of possible information bit strings increases, and the amount of calculations required to find the information bit string with the maximum Fano likelihood increases. For example, if the length of the information bit string is 1, the possible information bit string is 0.1
Since there are only two, the information bit string can be determined with one comparison operation, but when the length of the information bit string becomes 3, the possible information bit strings are 000,001. ..., 111-8
Since there are many variations, at least seven comparison operations are required to determine the information bit string. That is, conventional error correction encoding devices and error correction decoding devices have a drawback that high-speed decoding cannot be performed when the length of the information bit string becomes large.

The purpose of the present invention is to eliminate the above-mentioned drawbacks of conventional error correction encoding devices and error correction decoding devices, and to provide a new redundancy adding method that enables high-speed decoding even when the length of information bit strings becomes large. An object of the present invention is to provide an error correction encoding device that incorporates the above technology.

<Configuration of the Invention> The error correction encoding device of the present invention changes the internal state of a state holding circuit according to information bit strings that are sequentially input, and at the same time inputs the internal state to a function generator, and changes its output. An error correction encoding device that outputs a code bit string for an input information bit string, the function generator comprising two circuits, a first function generator and a second function generator, and further comprising the state holding circuit. The circuit consists of two circuits: a bit string holding circuit that holds a newly input information bit string and a state holding circuit that holds the internal state determined by the previously input information bit string. The output when input to the function generator and the information bit string of the bit string holding circuit are input to a second function generator that can define an inverse function regarding the information bit string, and the output is used as a code bit string for the input information bit string. It is characterized by output.

Further, in the error correction decoding device of the present invention, the state holding circuit
It consists of two circuits: a bit string holding circuit that holds newly input information bit strings and a state holding circuit that holds the internal state determined by the previously input information bit strings.The internal state of the state holding circuit is input to the function generator. The output when doing so and the information bit string of the bit string holding circuit are input to another function generator that can define an inverse function for the information bit string, and the output is sequentially input as a code bit string for the information bit string that is input in sequence. An error correction decoding device corresponding to an error correction coding device that outputs an error correction decoding device, comprising an inverse function generator of another function generator capable of defining the inverse function, and the inverse function generator includes a received bit string. Is the information bit string sent by inputting a part of the 1d injured bit string? Particular function characterized by estimation In the present invention, the encoder calculates the output bit string f=F( 8) and the newly input information bit string U are input to another function T, and the output bit string x=T(u, f) of T is converted into the information bit string U.
Output as a code bit string for However, the function T
is the inverse function T when the input f is fixed and seen as a function of U.
71 can be defined. For such an encoder, the decoder does not judge the information bit string with the maximum Fano likelihood as the transmitted bit string, but instead uses the inverse function T to determine the received bit string y or the hard decision result of the received bit string y. The previous judgment of determining that the input bit string T((y) is the sent bit string is correct, and.

If there are few errors in the received bit string, there is a high probability that the received bit string is the information bit string to be sent. Also, when redoing decoding going back to the past, the information bits with the next largest Fano likelihood and the past judgment U,
The bit string W (u o p u j) obtained by inputting the above into a predetermined function W is re-judged to be the sent bit string. Here, the subscript j of U indicates the number of times the determination has been revised in the past. Further, it is assumed that the function W is determined so that the probability that the bit string given by %W(u, u-) is sent is 4, which is the next most likely information bit string after U. In this way, comparison operations are not required, so high-speed decoding can be performed even if the information bit string becomes long. Figure 1 is a basic configuration diagram of the error 9 correction encoding device of the present invention. , the information bit string input from the input terminal 101 is sent to the bit string holding circuit 110 via the line 102.
is entered and retained. When the next information bit string is input, the bit string held in the bit string holding circuit 110 is input to the state holding circuit 103 via the line 112 and is input to the 0 bit string holding circuit 110 which updates the internal state of the state holding circuit 103. The held bit string is also supplied to the function generator T107 via the line All. Further, the function generator F is connected to the function generator T107 via the line 106.
The output bit string of 105 is also input. Function generator P
105 shows the internal state of the state holding circuit 103 on line 1.
It is input via 04. Note that each time an information bit string is input, an output bit string of the function generator T107 is outputted to an output terminal 109 via a line 108 as a code bit string.

FIG. 2 is a basic configuration diagram of an error correction decoding device for the error correction encoding device of FIG. 1. In the figure, bit string holding circuit 218. State holding circuit 208, function generator F20
7. The function generator T210 has the same function as that provided in the corresponding encoding device. However, since the bit string holding circuit 218 and the state holding circuit 208 need to return to their past states during the decoding process, they must be able to reversibly change their internal states. For example, the state holding circuit 208 can be replaced with a shift register. In this case, it is necessary to use a bidirectional shift register.The received bit string input from the 0 input terminal 201 is temporarily transferred to the input buffer 2021.
When the decoder determines that the past judgment is correct, it inputs the received bit string to the function generator T'f 206 and outputs it. It determines that the bit string is the sent information bit string, and inputs it to the bit string holding circuit 218 via the selector 207 and line 215. If the decision made by the decoder in the past is correct, the function generator T'i 20
There is a high probability that the output of No. 6 is the transmitted information bit string. On the other hand, when the decoder determines that the past judgment is incorrect, the decoder first returns the bit string holding circuit 218 and the state holding circuit 208 to the past state, and holds the bit string that was assumed to be incorrect. The received signal which is taken out from the circuit 218 via line 213 and fed to the 0 line 212 which is input to the function generator W2O5 is also returned to its past value, and the line 214 is supplied with the signal which is applied to the received signal for the first time. a mouth function generator 205 to which the determination results are supplied;
is line 213. The values supplied to 214 are compared, and the next most probable judgment result after the current judgment result is selected by selector 2.
07, the value held in the bit string holding circuit 218 is output to the bit string holding circuit 218 via the line 215, and is held therein, i.e., correcting the past determination result. , line 221, and finally the output buffer 20
It is stored in 3. However, when the decoder returns the states of the bit string holding circuit 218 and the state holding circuit 208 to the past states in order to correct past judgments, the past judgment results are taken out from the output buffer 203 and the line 221 is to the state holding circuit 208 via the state holding circuit 20
Past determination results are also taken out from 8 and returned to the bit string holding circuit 218 via line 220. Note that the determination result stored in the output buffer 203 is output from the output terminal 204 after a certain period of time has elapsed. The sequential decoder control circuit also uses the Fano likelihood of the received signal supplied to the line 212 and the output of the function generator T210 supplied to the line 222 to determine whether the past determination result is correct. A circuit that makes decisions, such as the American Forney (
George ])avid Forney, Jr.)
This can be accomplished with a circuit such as that described in U.S. Pat. No. 3,665,396.

<Example> As an example, 1% constructed according to the present invention! The 4-bit correction code correction bag is shown in FIG. 3, and the corresponding error correction decoding device is shown in FIG. 4.In addition, as another embodiment,
An error correction encoding device constructed according to the present invention is shown in FIG. 5, and a corresponding error correction decoding device is shown in FIG.

Figure 3, Figure 4, Figure 5, Figure 6, respectively, the first
Blocks or lines having the same functions as those in FIGS. 2 and 2 are designated by the same numbers. In these embodiments, the length of the information bit string is 3 bits and the length of the code bit string is 4 bits. Note that the length of the received bit string varies depending on the structure of the demodulator that converts the analog signal that has passed through the transmission path into a digital quantity. However, in a conversion called soft decision (instead of simply converting to 0°1, a bit indicating how close the converted value is to 0 or 1 is also added), the length of the code bit string becomes longer. In the embodiment, a decoder compatible with a hard-decision demodulator is shown, but a decoder compatible with a soft-decision demodulator is
Number of terminals of input terminal 201 in Fig. 4 and Fig. 6, line 21
The basic configuration is the same as this embodiment except for the number of lines of 2 and the structure of the sequential decoder control circuit 211.

In the encoding device shown in FIG. 3, the information bit string input from the input terminal 101 is
022 to the bit string holding circuit 110 and held there. The bit string holding circuit 110 includes a latch 1100.
1101 and 1102, and when the next information bit is input, the status holding circuit 1 is transmitted via line 112.
03 updates the internal state of the state holding circuit 103. The 0 state holding circuit 103 is configured with shift registers 1030, 1031, 1032 as a circuit for holding the internal state, and the internal state, that is, the contents of the shift register is input to the line 104. to the input of the function generator F105. The internal state is updated using the shift register 103.
This is accomplished by shifting the contents of 0, 1031, and 1032 to the right one bit at a time. Bit string holding circuit 110
The bit string held in is also supplied via line 111 to function generator T107.

Function generator T has lines 1060, 1061, 10
The output bit string of the function generator F105 is also input via 62 and 1063. Inside the function generator T107, the information bit strings are supplied on lines 1110, 1111, 1112.

The bit-by-bit exclusive OR with the output bit string of the function generator F105 supplied to lines 1060, 1061, and 1062 is taken by 1070, 1071, and 1072, and the output bit string of the function generator T107 is output on the line as 3 bits. Output to 1080, 1081, 1082. Therefore, the inverse function Ti''(y) for the information bit string of the function generator T107 is the line 1080, 1081 of the received bit string y.

1082 and lines 1060, 1061, . . . of the output bit string of the function generator F105. 106
It can be easily configured by performing a bit-by-bit exclusive OR with the 3 bits corresponding to 2. Note that the bit corresponding to line 1083 of the output bit string of function generator T107 is given as the output bit of function generator T1078, which has the information bit string and the output bit string of function generator 105 as inputs. The function generator T, 1073 is composed of logic circuits such as logical sum, logical product, and logical negation, and a read-only memory. In this embodiment, the state holding circuit 10
3 in parallel 3-stage shift registers 1030, 1031
. do. Also, function generator F10
5 is composed of a logic circuit and a read-only memory. Note that each time an information bit string is input, the function generator T
The output bit string 107 is outputted to an output terminal 109 as a K code bit string.

In the decoding device shown in FIG. 4, the bit string holding circuit 218
, the state holding circuit 208, and the function generator F209% function generator T210 have the same functions as those provided in the encoding device shown in FIG. 3. However, the bit string holding circuit 218
The state holding circuit 208 needs to return to the past state during the decoding process, so in addition to the functions provided by the encoding device, it also has a function that can shift the contents of the shift register to the left, and a function that can shift the contents of the shift register to the left. Output buffer 2 for storing state
03 is connected. Normally, the judgment result supplied to the line 215 is sent to the latch 2180 of the bit string holding circuit 218.
.

It is held in 2181 and 2182. When the next decision result is provided on line 215, the latch 2180
, 2181.

The determination result held in 2182 is input to the state holding circuit 208 via line 220. State holding circuit 2
08, when the judgment result is input, the shift register 20
The contents of 80, 2081, and 2082 are shifted to the right one bit at a time, and the judgment results input to the left end are held. It is stored in the buffer 203. Bit string holding circuit 2
18 and the state holding circuit 208 to the past state, the contents of the shift registers 2080, 2081, and 2082 are shifted to the left one bit at a time, and the past judgment result taken out from the output buffer 203 is held at the right end. Also, shift registers 2080 and 2081.

The judgment result of overflowing from the left end of 2082 is line 22.
0 to the latch 2180 of the bit string holding circuit 218
.

It is held in 2181 and 2182. If this operation is repeated, the internal states of the bit string holding circuit 218 and the state holding circuit 208 will go back in time. Output buffer 203
consists of random access memory or shift registers. The received bit string input from the input terminal 201 is temporarily stored in the input buffer 202K, and is supplied to the line 212 when the decoder needs it.When the decoder determines that the past judgment is correct, it generates a function. The received bit string is input to the selector T71206, the output bit string is determined to be the transmitted bit string, and the selector 20
7 and the latch 2180 of the bit string holding circuit 218 via line 215.

The determination results are held in 2181 and 2182. Three bits out of the four output bits of the function generator T107 of the encoding device shown in FIG. 3 are obtained by taking the exclusive OR of three bits out of the output of the function generator F105 and three bits of the information bit string. 206 is the output of the function generator F209 and the received bit string.
It can be constructed by performing an exclusive OR with each bit. If the decisions made by the decoder in the past are correct, there is a high probability that the output of the function generator T, 206 is the transmitted information bit string. On the other hand, when the decoder determines that the past judgment was wrong, the decoder returns the internal states of the bit string holding circuit 218 and the state holding circuit 208 to the past states, and returns the judgment result assuming that the judgment was wrong. It is taken out from the bit string holding circuit 218 via line 213 and input to the function generator W2O5.

The received signal supplied on line 212 is also returned to its past value, and line 214 is supplied with the result of the determination made for the first time on the received signal. The judgment result that is assumed to be incorrect is held in the latch 205o and is sent to the line 214.
That is, the value of the function generator T;
0 input to the address terminal of ROM 2
The output of 051 is again exclusive ORed with the output of function generator T7 206 and becomes the output of function generator W2O5 ◇The contents of ROM 2051 are, for example, sequentially 1 from address 0.
1.2.4.5゜3*6e 7 in e-decimal notation (001.010.100.101゜011.110 in binary notation)
, 111), then the function generator W
The output of 2O5 is input to the bit string holding circuit 218 via the selector 207 and line 215, and is held there. In other words, past determination results are corrected.几OM 205
If the contents of 1 are determined as described above, when correcting past judgments, the bit strings that are similar in pattern to the first judged correct bit string can be tried in order, so the probability of correct correction in a short time is high. It is practical. Note that the determination result held in the bit string holding circuit 218 normally moves in the order of line 220, state holding circuit 208, and line 221, and is finally stored in the output buffer 203K. However, when the decoder returns the states of the bit string holding circuit 218 and the state holding circuit 208 to the past state in order to correct past judgments, the output buffer 203
Past judgment results are taken out from the state holding circuit 208 via line 221, and past judgment results are also taken out from the state holding circuit 208 and sent back to the bit string holding circuit 218 via line 220. It will be done. Note that the determination result stored in the output buffer 203 is output from the output terminal 204 after a certain period of time has elapsed. The sequential decoder control circuit 211 also receives the injury signal supplied on line 212 and the function generator 'I' 210 supplied on line 222.
For example, American George David Ii'orney (J.
r. ) U.S. Patent No. 3T665RD96”
It can be expressed with a circuit like the one shown in j.

In the encoding device shown in FIG. 5, the information bit string input from the input terminal 101 is
.

1022 to the bit string holding circuit 110K and held. The bit string holding circuit 11o is a latch 110
0, 1101. , 1102, and when the next information bit is input, it is input to the state holding circuit 103 via the line 112 and the internal state of the state holding circuit 103 is updated. The state holding circuit 103 includes a shift register 1030 as a circuit that holds the internal state.

1031 and 3032, and supplies the internal state, ie the contents of the shift register, via line 104 to the input of function generator F105. Updating the internal state is accomplished by shifting the contents of shift registers 1030, 1031, and 1032 to the right one bit at a time.

The bit string held in the bit string holding circuit 110 is also supplied to the function generator T 107 via line 111.

Function generator T has lines 1060 and 1061.

The output bit string of the function generator F105 is also input via 1062 and 1063. Function generator T 107
Inside, the values when the information bit strings supplied to lines 1110, 1111, and 1112 are considered as numerical values,
Lines 1060, 1061, 1062, 1063
The output bit string of the function generator T107 is obtained by adding the output bit string of the function generator F105, which is supplied to the function generator T107, with the value when the output bit string is regarded as a numerical value, and the output bit string of the function generator T107 is obtained as the output bit string of the function generator T107 on the line 1080.

Output to 1081, 1082, 1083. In addition,
When the information bit strings supplied to lines 1110, 1111, and 1112 are considered as numerical values, the information bit strings of the function generator T107 can be inputted to the function generator T107 after multiplying the values by 2, instead of inputting the values as they are. The inverse function Tf(y) for can be easily constructed by subtracting the value obtained by considering the output bit string of the function generator F105 as a binary number from the value obtained by considering the received bit string y as a binary number, modulo 16. . Note that in this embodiment, the state holding circuit 103 is composed of parallel three-stage shift registers 1030, 1031, 103.
2, but it is also possible to configure these in series. However, in that case, in order to input the information bit string to the state holding circuit 103K, the
It takes twice as much time.

Further, the function generator F105 is constituted by a logic circuit and a read-only memory. Note that each time the information bit string is input, the output bit string of the function generator T 107 is outputted to the output terminal 109 as a code bit string.

In the decoding device shown in FIG. 6, the bit string holding circuit 218
, state holding circuit 208, and function generator F209.

The function generator T210 has the same function as that included in the encoding device of FIG. However, since the bit string holding circuit 218 and the state holding circuit 208 need to return to the past state during the decoding process, in addition to the functions provided by the encoding device, the contents of the shift register can also be shifted to the left. An output buffer 203 for storing functions and past states is connected. Normally, the judgment result supplied to the line 215 is held in latches 2180, 2181 and 2182 of the bit string holding circuit 218. When the next decision result is provided on line 215, the latch 2180 so far.

The determination results held in 2181 and 2182 are input to the state holding circuit 208 via line 220. When the judgment result is input, the state holding circuit 208 shifts the contents of the shift registers 2080, 2081, and 2082 to the right one bit at a time and holds the judgment result input at the left end.
.

The judgment result overflowing from the right end of 2082 is line 22
1 and stored in the output buffer 203. When returning the bit string holding circuit 218 and state holding circuit 208 to their past states, shift registers 2080 and 2081 are used.

The contents of 2082 are shifted to the left one pit at a time, and the past determination results taken out from the output buffer 203 are held at the right end. Also, a shift register 2080.

The determination results overflowing from the left ends of 2081 and 2082 are held in latches 2180 , 2181 , and 2182 of the bit string holding circuit 218 via line 220 . If this operation is repeated, the internal states of the bit string holding circuit 218 and the state holding circuit 208 will go back in time. Output buffer 203 is constituted by a random access memory or a shift register. The received bit string input from the input terminal 201 is temporarily stored in the input buffer 202, and when the decoder needs it, it is supplied to the line 212.0 When the decoder determines that the past judgment is correct, it generates a function. Input the received bit string to the device T; 1206, determine that the output bit string is the transmitted bit string,
Latches 2180 , 2181 , 2182 of bit string holding circuit 218 via selector 207 and line 215
The judgment results are stored in The 4-bit output from the function generator T107 in FIG. 5 is obtained by adding the value when the 4-bit output from the function generator F105 is regarded as a numerical value and the value when the 3-bit information bit string is regarded as a numerical value, with a modulus of 16. Therefore, the output of the function generator T71206 is 4 of the received bit string.
It is obtained by subtracting the value obtained by considering the output of the function generator F209 as a numerical value using the modulus 16 from the value obtained by considering the bits as a numerical value. However, since the information bit string is 3 bits, the upper 1 bit of the subtraction result is unnecessary. If the decisions made by the decoder in the past are correct, there is a high probability that the output of the function generator T71206 is the transmitted information bit string. On the other hand, when the decoder determines that the past judgment was wrong, the decoder returns the internal states of the bit string holding circuit 218 and the state holding circuit 208 to the past states, and returns the judgment result assuming that the judgment was wrong. It is taken from the bit string holding circuit 218 via line 218 and input to the function generator W 205. The received signal supplied on line 212 is also returned to its past value, and line 214 is supplied with the result of the determination made for the first time on the received signal.

The judgment result that is assumed to be incorrect is held in a latch 2050 and inputted to an address terminal of a read-only memory (ROM) 2051 along with the value on a line 214.

The output of the ROM 2051 becomes the output of the function generator W.

The contents of the ROM 2051 are arranged so that bit strings that are closest to the value obtained by combining the first bit string determined to be correct with a binary number appear in order. The decoder then uses a function generator W
The output of 205 is inputted to bit string holding circuit 218 via selector 207 and line 215, and is held there. In other words, past determination results are corrected.几0M205
If the contents of 1 are determined as described above, when correcting past judgments, the bit strings that are similar in pattern to the first judged correct bit string can be tried in order, so the probability of correct correction in a short time is high. It is practical. Note that the determination result held in the bit string holding circuit 218 normally moves in the order of line 22o, state holding circuit 208, and line 221, and is finally stored in the busy output buffer 203. However, when the decoder returns the states of the bit string holding circuit 218 and the state holding circuit 208 to the past states in order to correct past judgments, the past judgment results are taken out from the output buffer 203 and the line 221 is Past determination results are taken out from the state holding circuit 208 and returned to the bit string holding circuit 218K via line 220, respectively. Note that the determination result stored in the output buffer 203 is output from the output terminal 204 after a certain period of time has elapsed.

The sequential decoder control circuit 211 also measures the Fano likelihood of the received signal supplied to the line 212 and the output of the function generator T210 supplied to the line 222, and determines whether the past determination result is correct. For example, the American George Bitt Forney Jr.
As described above, according to the present invention, conventional error correction codes can be realized by a circuit such as that described in U.S. Pat. A high-speed encoding/decoding device can also be constructed.

Moreover, in the case of the error correction encoding/decoding device shown in the example, it is easy to implement because it can be configured with a simple circuit. It is clear that it can be effective in terms of improving reliability in dissemination.

[Brief explanation of drawings]

Figure 1 is a diagram of the basic materials of the present invention, Figure 2 is a diagram showing the basics of a decoding device used with the present invention, Figures 3 and 5.
Figure 4 and Figure 6 are diagrams showing an example of the configuration of a decoding device corresponding to the encoding devices of Figures 3 and 5, respectively. , 201...input terminal, 109. 204・
. . . Output terminal, 110, 218 . . . Bit string holding circuit, 103. 208...state holding circuit, 105.
209...Function generator F, 107°210...
Function generator T, 205...Function generator, 206...
Function generator T, , 1030, 1031, 103292
080°2081, 2082...shift register,
202... Input buffer, 203... Output buffer, 211... Sequential decoder control circuit. Figure 1 Figure 2

Claims (2)

[Claims] (1) Change the internal state of the state holding circuit according to the information bit string that is sequentially input, and at the same time input the internal state to a function generator, and output the output as a code bit string for the input information bit string. In the error correction encoding device, the function generator is composed of two circuits, a first function generator and a second function generator, and the state holding circuit is a bit string holding circuit that holds a newly input information bit string. It consists of two circuits: a circuit and a state holding circuit that holds the internal state determined by the information bit string input in the past, and the output when the internal state of the state holding circuit is input to the first function generator and the bit string holding circuit. An error correction encoding device characterized in that an information bit string of a circuit is input to a second function generator capable of defining an inverse function regarding the information bit string, and its output is output as a code bit string for the input information bit string. (2) The state holding circuit consists of two circuits: a bit string holding circuit that holds a newly input information bit string and a state holding circuit that holds the internal state determined by the previously input information bit string. The output when the internal state is input to the function generator and the information bit string of the bit string holding circuit are input to another function generator that can define an inverse function regarding the information bit string, and the output is used as input information in order. An error correction decoding device corresponding to an error correction coding device that sequentially outputs a code bit string for a bit string, further comprising an inverse function generator of another function generator capable of defining the inverse function, 1. An error correction decoding device that estimates a transmitted information bit string by inputting a received bit string or a part of the received bit string to a receiver.