JPS5919453A - Metric arithmetic circuit - Google Patents

Abstract

PURPOSE:To speed up the processing, by devising an arithmetic equation obtaining a path metric in a Viterbi decoder for decreasing an arithmetic amount. CONSTITUTION:A branch metric operating circuit 601 receiving a receiving signal for one branch's share in a Viterbi decoder to a convolution code having 3 of restricting length and 1/2 of coding rate, calculates a pair branch metric and inputs it to a path metric arithmetic circuit 602. Basing on the circuit 602 outputs each metric of the survival path at a preceding decoding step stored in a path metric storage 603, and a just inputted pair branch metric, executing the prescribed metric arithmetic equation, thus the newest survival path in each state and the most probable and the oldest symbols in the survival paths are outputted from an output terminal 640 via path memory 604.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for calculating and updating metrics at each point in time within a Viterbi decoder.

Conventionally, the Piterbi decoder has been known as the decoder with the best performance for decoding error correction codes, especially convolutional codes, but on the other hand.

The drawbacks are that the amount of calculation processing is large and the hardware scale is large.

For this reason, efforts have been made to reduce the number of calculations or hardware in each subcircuit within the Viterbi decoder.

An object of the present invention is to reduce the number of arithmetic operations performed by a metric arithmetic circuit in a Viterbi decoder, and to provide a simple metric arithmetic circuit that is faster in processing time than the conventional one.

According to the present invention, the metric calculation circuit is a metric calculation circuit for the path in a Viterbi decoder comprising a branch metric calculation circuit, a path metric calculation circuit 1, a path metric storage circuit, and a path memory; The path metric pairs of state pairs corresponding to the metric arrangement icM bare branch metrics are respectively input from the technique metric calculation circuit and the path metric link storage circuit, and the difference between the paired branch metrics and the difference between the IJ knocks are calculated. a first circuit that calculates the sum of the two difference amounts and a positive or negative sign of the difference, and outputs the positive or negative sign of the sum and the difference as a control signal for updating the path memory. and the sign of the sum and difference depending on the first output terminal and the sign of the difference, respectively.

A third step of selecting one branch metric of the bare branch metric and one path metric of the path metric pair, and calculating the sum of the selected metrics in a normalized form according to a signal from a fourth circuit described later. circuit and the respective sums obtained.

As a new path metric for each state, the second output terminal for outputting each new path metric to the path metric storage circuit and the new path metric are sequentially input, and the maximum value among all states is input. a fourth circuit for detecting a state having a new metric and generating said normalized signal; and a third output terminal for sending a detection signal for a state having said maximum metric to said path memory. It is configured as a metric calculation circuit characterized by comprising: For convenience of explanation, the Viterbi decoding method will first be briefly explained, and then the present invention will be explained in detail. Thereafter, differences between the circuit of the present invention and conventional circuits and embodiments of the present invention will be explained.

FIG. 1 is a diagram showing an embodiment of a convolutional encoder. , The convolution device in Figure ■ is 3. This constitutes an encoder with a coding rate of 1/2. 1 manually input from input terminal 100
or 00 signals are stored in registers 1 and 2 sequentially. An exclusive OR circuit 3 adds the input signal, the contents of register 1, and the contents of register 2 modulo 2, and outputs the result from the output terminal loi. In addition, the addition of No. 1 and register 2 modulo 2 is obtained by the exclusive OR circuit 4 manually.

It is output from the output terminal 102. In this way, a 1-bit input signal is converted into 2-bit signals and transmitted. Since the two output bits are determined by the contents of registers 1 and 2 and the input signal, the state transition diagram of this encoder is as shown in FIG. In Figure 2, there are four states (00), (10), (0
1) and (11) correspond to the internal states of registers 1 and 2, respectively, and connect each state to the secondary state.Ag!
(This is called a branch.) (5) means that the state moves to the next different state depending on the value of the input signal. Also (00) and (11) on the branch.

The expressions (1o) and (ot) are terminal 101 and terminal 10.
It represents the value output from 2. For example, register 1
, 2 are (0, 0) and the signal 1 is input, the output becomes (1, 1) and the state of register 1.2 changes to (1, 0). Figure 2 shows 1 following this.
．． The change in state when a signal of 0.1 is input is shown by a thick line. In this way, broken lines on the state transition diagram are formed in one-to-IK correspondence to each input signal string. This broken line is called a normal path.

Now, the Viterbi decoder calculates the correlation value between the transmission sequence and the reception sequence corresponding to each path, determines the path with the maximum correlation value, and performs decoding. The correlation value between the received sequence and each path is usually called a path metric. The Viterbi decoder stores path metrics corresponding to the four types of MK shown in FIG. 2, and updates the path metrics every time two symbols corresponding to one bit of information are received. As is clear from Figure 2, each of the four states corresponds to the transmitted signal.
), two branches emerge, and one of the four states reappears. From the perspective of the new state, the new state is the result of transmitting different codes from two of the previous states. For example, the state (1°0) is (0,
0), ゝゝl'' is input, and (1, 1
) is output and reaches (1,0), and (0,1) and b
There are cases where "1" is input and (0,0) is output when n(1,0) is reached.

In these two cases, the Viterbi decoder adds the correlation value between the received signal and the reception candidate No. 111g1 corresponding to each school (this is called the branch method) to the previous pass IJ value. , the path metric is updated by using the larger one as the new path metric. The path/me) IJ sock calculation and update method will be explained in more detail.

Now, the path metrics corresponding to the fourth received signal are Ma (00) and Ma (10), respectively.

Expressed as MA(Ol), MA(11), A+1st 2
The correlation value between the received bit signal and the 2-bit reception candidate signal (L1.L2) corresponding to each school is *R4+1 (Ll
, L2).

In this case, 2, for example, the (A+1)th path metric M
4N (Io) is MJ (00) + R Haruka +, (11)
and MA(01)+R,4+,(00), which is the thicker b side. Therefore.

M4+, (00), MJ+, (10)l Mle+,
If (01), M4+, and (11) are expressed mathematically, they will be of the first order.

However, Mu (A, B) indicates that it takes the larger value of A and B. If A=B, it doesn't matter which one you choose, but for the sake of explanation, I will choose it here.

Let us choose A.

In other words It is.

Now, depending on which of the two branches you select, you can tell which path you took, so based on that selection signal, the Viterbi decoder that corresponds to the encoder in Figure 1 always makes 4 passes and 9 passes. I will remember. In other words.

Candidates for four transmission sequences are stored. The circuit that stores this path is usually called a path memory.

FIG. 3 shows an example of paths stored in the path memory.

Only the selected path is shown in FIG. If all the paths stored in the path memory at time A in FIG. 3 are traced backwards, it can be seen that all the portions before time B result in the same path. Therefore, no matter what kind of signal is received in the future, it is impossible for the signal to deviate from the path before time B (thick line part). This phenomenon is called merging, and when merging occurs, the previously received sequences are uniquely determined, so a judgment output can be obtained from them. Generally, the length of the path until merging varies depending on the transmission path error pattern, and depending on the error pattern, it may not be possible to merge indefinitely. In an actual circuit, it is impossible to store a path of infinite length (9), so the length of the path must be cut off somewhere. In this case, it may be necessary to make a determination before the four paths are merged. In order to reduce the number of errors in judgment when paths are not merged, a method is used in which the most probable path at the current time (judgment time) is determined as the correct path. Therefore, in a normal Viterbi decoder, a bus memory of a fixed length is used, and the maximum path length (I) is determined at each judgment time.
The basic Gronk diagram of the decoder that determines the value corresponding to the first symbol of the path with rank J can be shown as shown in FIG.

In FIG. 4, a two-symbol received signal is input from an input terminal 400, and a branch metric calculation circuit 401 calculates a branch metric for the received signal for each school. The branch metric and path metric storage circuit 403
A new surviving path for each state is determined from each metric of the surviving path in the previous decoding step stored in (10).

This is performed by the path metric calculation circuit 402.

As a result, the sequence corresponding to the surviving path is stored in the surviving path memory 404, and the earliest symbol, that is, the most probable path among the surviving paths, is outputted to the output terminal 405 as a decoded symbol.

The present invention relates to the configuration of the IJ sock arithmetic circuit in the above-mentioned sheet-tabi decoder.

- First, we will explain in more detail the above (112), which represents the Pasume l-IJ Cook calculation.

Conventionally, a circuit has been used that directly calculates the performance of equation (1) according to the calculation equation of equation (0). Against this.

In the present invention, by changing the performance order of equation (1), the amount of calculation is reduced and a simple path metric calculation circuit with faster processing time than the conventional one is provided.

When the arithmetic expression of equation (1) is illustrated, it can be seen that it is expressed as shown in FIG. In Fig. 5, the left end shows each path metric corresponding to the Mth data of each state, the edges show the branch metrics to be added, and the right end shows each new path corresponding to the (J-H)th data. represents a metric.

As is clear from FIG. 5, it can be seen that the path metric link calculation expressions are classified into nine categories, with two expressions each being bare.

In equation (1), two bears are created.

Furthermore, it can be seen that there are only two types of branch metric values in each bear, and the reception candidate signals (L, , A2) corresponding to the two types of branch metrics are in an inverted relationship with each other. These two types of branch metrics will hereinafter be referred to as "bare branch metrics." Here, the branch metric, i.e. the received signal (U.

Let the correlation value between u2) and the reception candidate signal (L, , L2) be (l'1+L2u2), and further.

rr * r2 + pigeon 2M2 is determined as follows.

r, = R4+, (00) RA+, (11)
-----(31r2= R4,, (10)-1
'LA,, (01) ・-Song-・-Song・Song (41M1
-Ma (00) -MA (01) ・・・・・・・
・・・・・・・・・・・・+51M2 = MA (1
0) -MJ (11) ・・・・・・
...... 1 bond 6), 1. If it is counted as -1.

The reception candidate signal L2 represents +1 or -1. Therefore, the branch metric is (L, uI+L2I
+□), it is clear that ``A + 1
(11)=-JL family, (OOL R4+, (ox)-R
4+, (10), so r, = 2 RA+, (00) ・・・−・・
・・・・・・・・・・・・・・・・・・(7) [2= 2
R44,, (10) ・・・・・・・・・・・・・
...-...+8).

Now, from equations (3) to (6), the calculation formula for equation 0 above is:
By paying attention to equation (2), it can be seen that K can also be expressed as linear. That is, 2 (13) Therefore, 1st stroke, (00) 1MA+, (10) 1st stroke, (
01) 1MA++ (11) are each = N4'+
+ r1+ Ml r++ M2+r2+M2-r2
By checking the positive and negative signs of , it is possible to determine which of the two candidates it is.

Here 1 e.g. Mru+, (oo) and Mmu+, (1o
) will be compared with the conventional case.

In the conventional case, 1 time (00) 10 RA + 1 (oO) 1 MA (
ol) 10RA+I(11), (MA(00)+I14
+, (00)) (MJ(01)+R4+, (11)
) and = (MJ(00)+Rx++(”))
, (MXOI) 10R4++ (00)).

(Ma (00) + R4 +, (11) ) - (M, (0
1)+aJ+, (00) )O6 additions and subtractions are required. On the other hand, if the calculation order used in the present invention is followed.

MA(OO)-λ(s(01'),(MA(00)
MJ(Of)) 10r+(MA(00)−MJ(o
3 additions and subtractions of x )″)−rl and.

MA (00) 10R6A++ (00) or MJ (01
)+RJ+, either operation of (11) and MA
(00) 10R6, (11) or (14) or M, (01) Only 2 additions of either +RA, -, (Oo), a total of 5 additions and subtractions are required, which is different from the conventional case. It can be seen that the computation cost can be reduced by comparison.

The same applies to the number of operations when calculating the values of M+1 (01) and MA+1 (lI). This is an effective method for Viterbi post-decoder processing high-speed data. Unfortunately, as described above, in order to determine the decoded symbol to be output, it is necessary to determine the most probable path among the surviving paths. This means that we are looking for the path with the highest path metric value at each point in time.

MA+1(00)1MA+1(lO)1MA+l(01
) 1M Luya, we need to choose the largest one among (11).

Shikuru k (7) - From the sequel Because it is.

Which of M, (00), M,4+, and (10) is larger is determined by the positive or negative sign of M, + r, l M, -r, and the positive or negative sign of M1゜rl. You can also do it.

Similarly, which of M stroke, (01), MA+, and (10) is larger is determined based on the positive/negative sign of M2 + rz * M2 r2 and M2. The number of comparison operations that can be determined by the positive or negative sign of r2 can be reduced by half by using the already calculated 4rl'' or M2. It is.

Now, the path metric M4 (ru,,ru2) is (7)~Q
If the calculation is continued according to l2, the path metric will continue to increase each time data is input to the Viterbi decoder. Therefore, it is necessary to perform appropriate normalization on the path metric so that the bus metric storage circuit does not overflow.

Usually, the maximum or minimum path metric is found among the path metrics for all MVCs.

Normalization is performed by subtracting the maximum or minimum path metric from each path metric. Of course, a path metric of a specific size other than the maximum or minimum may be used. In addition, for the normalization of the path metric Ma4+('+,=21) corresponding to the A+1st received signal, the path metric Ma4+('+, which corresponds to the Rth received signal, the maximum path 7 of Dukyo Small) may be used. .

The explanation so far is based on restraint length 3. We have explained the metric calculation in the Kitabi decoder for convolutional codes with a coding rate of 1/2, but we will also explain the metric calculations in the Kitabi decoder for convolutional codes with other parameter mesinators. Only the number of expressions increases, #1
This will be explained.

, -ε Next, a description will be given with reference to FIG. 6, which is a block diagram of a G1Tabi decoder including a one-shot 1j11 embodiment.

In FIG. 6, a portion 602 surrounded by two dotted lines corresponds to a metric arithmetic circuit according to the present invention.
7) Reference numerals 603 and 604 respectively indicate a branch metric calculation circuit, a path metric storage circuit, and a path memory in FIG.

Now, with respect to the received signal for one branch input via the input line 610 at the clock (A+x), the branch metric link calculation circuit 601 calculates the bare branch metric "A+1 (lacquer, !2) * RA+1 ( The bare branch metrics, ri, are sequentially calculated.The bare branch metrics, ri, are sequentially sent in series or parallel to the path metric calculation circuit 602.However, as described above, each branch metric of the pair branch metrics is normally is in a relationship with the positive and negative signs reversed, so
You may send only one of them. Reference numeral 621 that received a bare branch metric or a single branch metric.
The circuit is.

This circuit calculates the difference r between the bare technique metrics (in the case of a single metric, the difference r is equal to twice the single metric).

On the other hand, it corresponds to the branch metric. Bus metric pair Ma(j,,j2)1M4(s,,52
) (that is, the buster (18) trick pair appearing on the right side of each equation of (7) to OI equation) is read out from the path metric storage circuit 603 via line 630, and the difference M between the path metric pairs is calculated by the subtraction circuit. 622.

Next, M and r are input to a circuit 623, and the sign of the sum and difference of 2M and r is determined in the circuit 623.

The sign of the sum and the difference and the branch metric pair R +
1(Ll'ru2""A+I, ji) and the path metric pair MA(j,, J2)+"j(s+"2)
are input to the circuit 624, and according to the positive and negative signs of the sum and difference, the branch metric pairs R+, (L, ·L2)+R4+, as shown in equations (7) to 01 above, are
(Saku, et al.) and the path metric pair MA (
j, , j2), MA ($1182) are selected, and the circuit 624 calculates the respective sums of the selected branch metric and the path metric.

Each calculated sum is a new pasta) IJTSUKM
4+, (u + * uz ) r M4+, (V
r l V2 ), but as mentioned above, each new path metric is subtracted by a certain value by the normalization signal from the 6250 circuit described later,
The subtracted path metric link is updated and stored in the path metric storage circuit 603.

However, when subtracting a certain value, KMJ(j, ,
After subtracting a certain value from J2) and M4(s, os2), and then taking the sum of the above, the circuit 62
4 may be configured. On the other hand again. The positive and negative signs of the sum and difference serve as a signal indicating which path has been selected at the clock (A+1), and are used as a signal for updating the path memory in the path memo')-6.
Sent to 04. In the pass memo IJ-604, the pass memory is updated in accordance with the signal for this update.

Sara K again. The normalized new path metric is
It is sent to sequential circuit 625. For all pairwise branch metrics and corresponding state pair metric pairs for the received signal at clock (A+1).

The above-described operations are performed, and the second circuit 625 is a circuit that detects the state having the maximum path metric, sum ν, and maximum metric among the new path metrics for all states tlK. The maximum metric detected is
It is supplied to the circuit 624 as a constant value to be subtracted from the normalization reserve. - Also, the detection signal of the state having the maximum metric is the bus memory 604
In the bus memory, the oldest bit of the bus memory for that state flows as a decode signal to line 640.

As described in detail above, the metric calculation circuit according to the present invention changes the conventional calculation order and reduces the number of calculations, resulting in a simpler circuit with shorter processing time than the conventional one. Therefore.

Aim - It is important as a metric calculation circuit for a ≠9 Tavi decoder that processes ultra-high-speed data.

In the present invention, the metric calculation has been described in a form in which serial VC is performed sequentially for each pair of branch metrics, but it is clear that a circuit that performs the metric calculation in parallel for -1C high-speed processing can be constructed in a similar manner.

(21)

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a convolutional encoder, and FIG. 2 is a diagram showing state transitions of the encoder shown in FIG. FIG. 3 is a diagram showing an example of selected surviving paths. ε Fig. 4 is a block diagram showing the configuration of the h-Tabi decoder and the positioning of the path metric calculation circuit, Fig. 5 is a diagram showing the path metric calculation formula for each pair, and Fig. 6 is a block diagram showing the configuration of the h-Tabi decoder and the positioning of the path metric calculation circuit. FIG. 2 is a configuration block diagram of a V-Mitabi decoder including an embodiment. In Figure 1, reference numbers 1.2 are registers, 3.4 are exclusive OR circuits, 100 are input terminals, 101°102
represents an output terminal. In Figure 4, b is the number 400.
401 is an input terminal, 401 is a branch metric calculation circuit, 402 is a path metric calculation circuit, 4o3 is a path metric storage circuit, and 404 is a bus memory. 405 represents an output terminal. In Figure 6, reference numeral 6
01 is a branch metric calculation circuit, 602 is a path metric calculation circuit, 603 is a bus metric storage circuit, 604
is the bus memory, and 601 is the input line. 640 is the output line, 630 is the metric performance of the path (2
2) Input line to the arithmetic circuit 602; 621 is a circuit for calculating the difference between bare techniques metrics; 622 is a circuit for calculating the difference between a pair of metrics; 623 is a circuit for calculating the difference between pairs of metrics; A circuit 624 for calculating the sum of the difference between
It represents a circuit that calculates the normalized sum of the input branch metric and the path metric. (23) O l Figure O 2 Mouth time O 3 Circle No. 4 Question/+ 5 Figure R rope +t (/-0)

Claims (1)

[Scope of Claims] In the path metric calculation circuit in the Viterbi decoder, which includes a branch metric calculation circuit, a path metric calculation circuit, a path metric storage circuit, and a path memory, the pair branch metric and the bare branch metric are The path metric pairs of state pairs corresponding to the above are respectively input from the branch metric calculation circuit and the path metric storage circuit. A first circuit that calculates the difference between the bare branch metrics and a difference between the pair of metrics, a second circuit that calculates the sum of the two difference amounts and the sign of the difference, and a second circuit that calculates the sign of the sum and the difference. A first output terminal for outputting a sign as a control signal for updating the path memory, and one branch metric of the bare branch metric and the pair of path metrics according to the positive and negative signs of the sum and difference, respectively. Select one path metric and calculate the sum of the selected metrics as the fourth
a third circuit that calculates each in a normalized form according to the signal from the circuit, and outputs each of the obtained sums to the path metric storage circuit as a new path metric in a state corresponding to each. the second output terminal of the IJ sock (the second output terminal of the new buster) and the fourth one which sequentially inputs the IJ sock and generates the normalized signal as well as the detection of the state which has the largest new table metric among all the states. and a third output terminal for sending a detection signal of the state having the maximum metric link to the path memory.