JPH0420530B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to addition comparison selection (ACS).
The present invention relates to a Compare-Select circuit, and particularly relates to an addition comparison selection circuit included in a Vitabi decoder used, for example, in a digital communication device.

[Conventional technology]

Generally, a Vitabi decoder used in a digital communication device receives a convolutionally encoded data sequence, decodes it using a maximum likelihood decoding technique, and reproduces transmitted data. That is, in the Vitabi decoder, first, from among all possible data sequences that satisfy the encoding rules, some data sequences that are considered to be probable based on the received data are retained. These remaining paths are selected as paths and continue to be saved while being updated each time data is received. Second, each time one symbol of data is received, the most probable one among the remaining paths is selected, and one symbol of decoded data is output from this selected path. In this Viterbi decoder, certainty is expressed by path metrics, which are obtained by adding branch metrics supplied for each symbol of data along the branches of the data sequence. Therefore, the Vitabi decoder adds the stored path metric and the branch metric of the received data in several combinations, compares the addition results, selects a new path metric, and simultaneously adds the selected new path metric. Signal processing is performed in which the smallest path metric is selected to determine the maximum likelihood state.

Conventionally, as an addition comparison selection circuit (ACS circuit), for example, A. Shenoy and P. Johnson, "Serial
implementation of Viterbi decoders”
COMSAT Tech.Rev., vol.13, pp.315-330,
The one disclosed in Fall, 1983. is known.
FIG. 6 is a block diagram showing an example of a conventional ACS circuit. In the figure, 1 is the branch metric λ obtained from the received data, 2 is the branch metric register that stores the branch metric λ1, 3 is the branch metric λ output from the branch metric register 2, and 4 is the remaining path. 5 is the path metric Γ output from the path metric register 4, 6 is an ACS unit that creates a new path metric Γ from the path metric Γ5 and the branch metric λ3, and 7 is the new path metric Γ'. , 8 is the new path metric Γ′7
9 is the minimum path metric detection circuit Γ _nio which is the output of the minimum path metric detection circuit 8;
10 is a subtraction circuit that subtracts the minimum path metric Γ _nio 9 from all the path metrics Γ'7; 11 is the path metric Γ which is the output of the subtraction circuit 10; 12
is a maximum likelihood state selection circuit which selects the maximum likelihood state from the path metric Γ11, and 13 is a maximum likelihood state signal representing the selected maximum likelihood state.

FIG. 7 is a block diagram showing an example of the minimum path metric detection circuit included in the ACS circuit of FIG. 6. In the figure, 14 to 17 are input terminals of four types of path metrics Γ'(0), ..., Γ'(3), 48 is a comparator for comparing each path metric Γ'(0) and Γ'(1); 49 is a comparator for comparing each path metric Γ'(2) and Γ'(3), and 50 is a comparator for comparing each path metric Γ'(0) and Γ'(1) by the output signal of comparator 48
51 is a comparator 4, which selects the smaller one of
A selector 52 selects the smaller of path metrics Γ'(2) and Γ'(3) according to the output signal of 9; a comparator 52 compares the outputs of the selectors 50 and 51;
is a selector which outputs the minimum path metric Γ _nio 9 according to the output signal of the comparator 52, and 54 is an output terminal of the minimum path metric Γ _nio 9.

Next, the operation of the conventional ACS circuit shown in FIG. 6 will be explained. The branch metric λ3 stored in the branch metric register 2 is
It is supplied to the ACS unit 6 together with the path metric Γ5 stored in the path metric register 4. The ACS unit 6 adds the path metric Γ5 and the branch metric λ3 in a predetermined combination to create candidates for a new path metric, selects a likely path from these, and outputs the path metric Γ'7. do.

The functions of the ACS unit 6 will be explained in more detail by taking an example. What we will discuss is
This is the case of a convolutional code with a constraint length of 3 as proposed by Ungerboeck. At this time, 00,
8 expressed as 20, 01, 21, 10, 30, 11, 31
The eight remaining paths corresponding to the two states and their path metrics {Γ(00), Γ(20), Γ(01), Γ
(21), Γ(10), Γ(30), Γ(11), Γ(31)}. On the other hand, there are also eight branch metrics {λ(0), . . . , λ(7)}.
Here, we will focus on the process of creating a new path metric Γ'(00). First, four types of addition are performed: Γ(00)+λ(0), Γ(20)+λ(4), Γ(01
)＋
λ(2), Γ(21)+λ(6) are created, and then the smallest of these is selected to become Γ'(00). For other path metrics, similar addition,
A comparison and selection is made.

The new path metric Γ'7 created as described above is input to the minimum path metric detection circuit 8 and the subtraction circuit 10. If there is no noise in the received signal, the branch metric λ1 usually contains the smallest branch metric whose value is equal to 0, and as a result the path metric Γ'7 also contains the smallest branch metric. , whose value is equal to 0 is included. In this case, it is known that the maximum path metric Γ'7 does not exceed a certain value. However, in reality, the minimum value of the branch metric λ1 is greater than 0 due to noise in the received signal, and due to this, the path metric Γ'7 tends to increase gradually and without limit with time. The minimum path metric detection circuit 8 and the subtraction circuit 10 are provided to prevent this phenomenon. First, the minimum path metric detection circuit 8 detects and outputs the minimum path metric Γ _nio 9, which is the minimum value of the input path metrics Γ'7. Next, the subtraction circuit 10
Now, subtract the constant minimum path metric Γ _nio 9 from all the path metrics Γ'7. In the path metric Γ11 created in this way, the minimum value is equal to zero. Note that a method of replacing the minimum path metric Γ _nio 9 with an arbitrary path metric among the path metrics Γ'7 without providing the minimum path metric detection circuit 8 is known, for example, from Japanese Patent Application Laid-Open No. 59-19453. ing. When this method is used, the minimum value of the path metrics Γ11 is not necessarily 0, but can take any positive, negative, or 0 value.

The path metric Γ11 created in this way is branched, one of which is fed back to the path metric register 4 and used to update its value, and the other is supplied to the maximum likelihood state selection circuit 12. The maximum likelihood state selection circuit 12 finds the minimum path metric Γ11 and outputs the state signal corresponding to it as the maximum likelihood state signal 13.

Next, the operation of the minimum path metric detection circuit 8 shown in FIG. 7 will be explained in more detail. 4, represented here as 0, 1, 2, 3 for simplicity
There exist two states, so Γ′(0),...
Consider the case where there are four types of path metrics Γ'(3). In the combination of comparator 48 and selector 50, each path metric Γ'(0) and Γ'(1)
The smaller of these, i.e. Min{Γ′(0),
Γ′(1)} is selected. Similarly, in the combination of comparator 49 and selector 51, Min{Γ′(2), Γ′(3)
}
is selected. Therefore, the minimum path metric Γ _nio 9 output from the combination of the comparator 52 and the selector 53 to the output terminal 54 is Min{Γ'(0),
Γ′(1), Γ′(2), Γ′(3)}, that is, the input 4
is the smallest of the path metrics.

[Problem that the invention seeks to solve]

Since the conventional ACS circuit described above is configured as described above, when the number of states and therefore the number of path metrics is large, not only does the hardware of the minimum path metric detection circuit 8 increase. , due to the longer signal processing time,
There was a problem in that the path metric feedback loop including the path metric register 4 could not support high-speed data transmission. Note that if the minimum path metric detection circuit 8 is not provided and a method is adopted in which an arbitrary path metric is used instead of the minimum path metric, the path metric Γ11 after subtraction can take a negative value, and is fed back to the next time. It is also possible that the result when added to the branch metric λ3 as the path metric Γ5 becomes negative. Therefore, in this method
Since it is necessary to handle both positive and negative numbers in the addition processing and comparison processing in the ACS unit 6, the hardware configuration of the ACS unit 6 becomes complicated. There was a problem in that the overall operating speed of the comparison and selection circuit decreased.

The present invention was made to solve these problems, and aims to simplify the signal processing of path metric subtraction, create a simple hardware configuration, and obtain an ACS circuit that can handle high-speed data transmission. shall be.

[Means for solving problems]

The ACS circuit according to the present invention includes a metric generation circuit instead of the minimum path metric detection circuit, converts each path metric in advance according to a certain law in the metric generation circuit, and converts the converted path metric to the metric generation circuit. This is almost the same as finding and subtracting the minimum value from the path metric by performing a simple logical operation on the path metric and generating a metric whose value is close to, but not exceeding, the minimum value of the path metric. Equivalent signal processing is realized using simpler logical operations.

[Effect]

In the ACS circuit of the present invention, the constant value to be subtracted from the path metric can be obtained by a simple logical operation, and there is no need to use many comparators or selectors, so the hardware configuration for path metric subtraction is simple. At the same time, its signal processing time is reduced and the operating speed of the ACS circuit is increased.

〔Example〕

FIG. 1 is a block diagram showing an ACS circuit according to an embodiment of the present invention, with each reference numeral 1 to 7, 10 to
13 is the same as the conventional circuit described above. In the figure, 8a is a metric generation circuit, and 9a is a metric Γ _n which is the output of the metric generation circuit 8a, and its value is close to the value of the minimum path metric Γ'7 input to the metric generation circuit 8a.
and not exceed that value.

FIG. 2 is a block diagram showing an example of a metric generation circuit included in the ACS circuit of FIG. 1. In the figure, 18 to 21 are path metric conversion circuits for each path metric, and 22
is a logic circuit that performs a logical operation on each digit of the converted path metric to create the metric Γ _n , 23
27 is an AND gate, 28 is an exclusive OR gate, and 29 to 32 are output terminals for each bit of the metric Γ _n .

FIG. 3 is a circuit diagram showing a path metric conversion circuit included in the metric generation circuit of FIG. 2. In the figure, 33 to 36 are input terminals for each bit of one path metric Γ'(j), 37, 38, 4
0 is an AND gate, 39, 41-43 are OR gates, 44-47 are converted path metrics G
This is the output terminal for each bit of (j).

FIG. 4 is a diagram for explaining the metric generation process in the metric generation circuit of FIG. 2.

Next, the operation of the ACS circuit shown in FIG. 1, which is an embodiment of the present invention, will be explained. Based on the path metric Γ′7, the metric generation circuit 8
In a, the metric Γ _n 9a of the value to be subtracted from each of them is output. Here, the value of the metric Γ _n 9a is close to the minimum value of the path metric Γ'7 and does not exceed the minimum value.

Next, the metric generation circuit 8 shown in FIG.
The operation of a will be explained in more detail. However, it is assumed here that there are four path metrics Γ'(0), . . . , Γ'(3), and each path metric is expressed as a 4-bit positive value.
Each path metric Γ′(0),…,Γ′(3) is
First, each path metric conversion circuit 18-21 performs conversion according to a certain rule. Next, a logical operation is performed for each digit of the converted path metric in the logic circuit 22, and as a result, the metric Γ _n is output to each output terminal 29 to 32.
is output to.

Next, the operation of the path metric conversion circuit shown in FIG. 3 will be explained in more detail. Let one path metric be Γ′(j)=(γ ₃ , γ ₂ , γ ₁ , γ ₀ ), and the converted path metric be G(j)=(g ₃ , g ₂ , g ₁ , g ₀ ).
shall be. Each bit of the path metric Γ'(j) and the converted path metric G(j) is applied to each input terminal 33-36 and each output terminal 44-47, respectively. Here, the law of conversion is given by the following logical operation.

g ₃ = γ ₃・(γ ₂ + γ ₁ γ ₀ ) g ₂ = γ ₃ + γ ₂ γ ₁ γ ₀ g ₁ = γ ₃ + γ ₂ + γ ₁ γ ₀ g ₀ = γ ₃ + γ ₂ + γ ₁ + γ ₀ Therefore , the values of each path metric Γ'(j) and G(j) are expressed in decimal notation as follows.

G(j)= 0, when Γ′(j)=0 1, when Γ′(j)=1, 2 3, when 3≦Γ′(j)≦6 7, when 7≦Γ′(j)≦10 15, when 11≦Γ′(j)≦15 holds true.

The binary representation of the converted path metric G(j) is
It has the feature that the upper few bits are consecutively read as 0, and the lower several bits are consecutively read as 1. Therefore, the value of the smallest of the converted path metrics G(j) can be easily determined by performing a logical AND operation on the bits of each digit of all G(j). However, when 11≦Γ′(j)≦15, the value of G(j) is larger than the value of Γ′(j), so this must be reflected in the logical operation. logic circuit 22
performs such logical operations to create the metric Γ _n .

Figure 4 shows each path metric Γ'(0), ..., Γ'(3
)
This figure shows the relationship between the converted path metric G(j), the metric Γ _n , and the subtraction result Γ'(j) - Γ _n for the path metric Γ'(j) with the minimum value.
As is clear from the table shown in FIG. 4, the value of the subtraction result Γ'(j)-Γ _n does not exceed 4. Furthermore, if the initial value of the minimum path metric is 0 and the maximum value of the branch metric is 7, it can be seen that in the ACS circuit according to this embodiment, the minimum value of the above subtraction result does not exceed 3. In fact, in the worst case, if the values of the branch metrics corresponding to the minimum path are 6, 7, 7, 7, etc., then the minimum path metric starts from Γ = 0 and sequentially
+λ-Γ _n =0+6-3=3, 3+7-7=3,
3+7-7=3, 3+7-7=3,... In this way, the metric generation circuit 8 according to the present invention
A is different from the minimum path metric detection circuit 8 of the conventional example in that, in combination with the subtraction circuit 10, the path metric can be kept at a small value by preventing the phenomenon in which the value of the path metric Γ11 increases infinitely with time. performs the same function as

As is clear from the above explanation, this invention
The metric generation circuit 8a in the ACS circuit is
The same function as the minimum path metric detection circuit 8 of the conventional example is realized by simpler logical operations. This shows that the metric generation circuit 8a can not only be realized with simpler hardware than the minimum path metric detection circuit 8, but also has a shorter signal processing time, and can therefore correspond to the high-speed operation of the ACS circuit. There is. This means that
This problem becomes even more noticeable when the number of states and path metrics is large. For example, in the minimum path metric detection circuit shown in FIG. 7 above, if there are four path metrics, only three comparators and selectors are required, and from the input terminal of the path metric to the output terminal of the minimum path metric. It is only necessary to pass through the comparator and selector twice each. However, if the number of path metrics increases to 16, 15 combinations of comparators and selectors are required, and from the input terminal of the path metric to the output terminal of the minimum path metric, each comparator and selector must be passed four times. have to,
This increases signal processing time. On the other hand, in the metric generation circuit shown in Fig. 2, even if the number of states increases, it is only necessary to provide a path metric conversion circuit for each path metric, and for this reason, the signal processing Time is almost independent of the number of states.

Note that in the above embodiment, the metric generation circuit 8
The case where the ACS circuit is configured to subtract the metric Γ _n 9a, which is the output of a, from the path metric Γ'7 has been described. did
In conjunction with the configuration of the ACS circuit, as shown in Fig. 5, the branch metric λ1 to the metric Γ _n 9a
The value of λ3a may be subtracted by the subtraction circuit 10a and supplied to the branch metric register 2a, and the branch metric λ3a may be output from the branch metric register 2a, and the same effect as in the above embodiment can be obtained. play.

〔Effect of the invention〕

As explained above, the present invention includes a metric generation circuit in place of the minimum path metric detection circuit in the ACS circuit, and generates a constant value that is close to the minimum path metric value and does not exceed it by simple logical operations. Since the ACS circuit is configured so that it occurs when there is a large number of states, the hardware configuration can be simplified compared to conventional ACS circuits of this type, and the ACS circuit can easily handle high-speed data transmission. This has excellent effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an ACS circuit according to an embodiment of the present invention, and FIG.
A block configuration diagram showing an example of the metric generation circuit included in the ACS circuit, FIG. 3 is a circuit diagram showing a path metric conversion circuit included in the metric generation circuit of FIG. 2, and FIG. 4 is a circuit diagram of the metric generation circuit of FIG. FIG. 5 is a block configuration diagram showing an ACS circuit according to another embodiment of the present invention; FIG. 6 is a block configuration diagram showing an example of a conventional ACS circuit; FIG. 7 is a block diagram showing an example of the minimum path metric detection circuit included in the ACS circuit of FIG. 6. In the figure, 1, 3, 3a... branch metric λ, 2, 2a... branch metric register, 4... path metric register, 5, 11...
...Pathmetric Γ, 6...ACS unit, 7
...The path metric Γ', 8 before being subtracted...
Minimum path metric detection circuit, 8a... Metric generation circuit, 9... Minimum path metric Γ _nio , 9
a...Metric Γ _n , 10, 10a... Subtraction circuit, 12... Maximum likelihood state selection circuit, 13... Maximum likelihood state signal, 14-17... Input terminal of path metric Γ', 18-21... Path metric conversion circuit,
22...Logic circuit, 23-27, 37, 38, 4
0...AND gate, 28...Exclusive OR gate, 29-32...Output terminal for each bit of metric _Γn , 33-36...Input terminal for each bit of path metric Γ'(j), 39 , 41-43...OR gate, 44-47...Output terminal of each bit of the converted path metric G(j), 48, 49, 5
2... Comparator, 50, 51, 53... Selector, 5
4...This is the output terminal of the minimum path metric Γ _nio . In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. For a first data signal consisting of a plurality of input data signals and a second data signal created based on the first data signal that has already been input,
Signal processing of addition, comparison, and selection is performed to create a third data signal, and a subtraction operation is performed on the third data signal to create a fourth data signal.
In the circuit for replacing the data signal with the second data signal to update the content of the second data signal and selecting the one having the minimum value among the fourth data signals, As a constant value to be subtracted from the third data signal in the subtraction operation, a constant value that is close to the minimum value of the third data signals and does not exceed the minimum value is generated by a logical operation. An addition comparison selection circuit characterized in that by providing means, the result of the subtraction operation is always greater than or equal to zero. 2. The means for obtaining a constant value from the third data signal includes means for converting this third data signal in advance according to a certain rule, and a means for obtaining a fixed value from the third data signal. means for generating a fifth data signal by ANDing; means for generating the most significant bit of a sixth data signal by ANDing the two most significant bits of the fifth data signal; By the exclusive OR of the sixth
means for making the next most significant bit of the data signal; and means for making each bit of the fifth data signal each bit of the sixth data signal for the following digits; 2. The addition comparison selection circuit according to claim 1, further comprising means for setting the signal to the constant value. 3. According to the above-mentioned certain rule, when one third data signal is composed of 4 bits, means for creating the first bit obtained by logical product of the lower two bits of this third data signal. and the second bit from the top of the third data signal and the first bit.
means for making a logical product and a logical sum with a bit of the third data signal and making these a second bit and a third bit, respectively; and a logical product of the third bit and the most significant bit of the third data signal. and a means for logically disposing these as the most significant bit of the seventh data signal and the third bit from the most significant bit thereof, and the most significant bit of the second data signal and the third data signal. means to make a logical OR of all the bits of the third data signal and set it as the second most significant bit of the seventh data signal; 3. The addition comparison selection circuit according to claim 2, further comprising means for converting said third data signal.