KR100324066B1 - Viterbi decoder - Google Patents

Abstract

The present invention relates to a Viterbi decoder, and focuses on the fact that the decoded paths are matched with a high probability when performing backtracking, and if a point that matches the previous backtracking path is found during the current backtracking process. By configuring the path bit strings stored in the previous traceback, the computation amount and the computation time of the traceback can be reduced.

Description

Viterbi decoder {VITERBI DECODER}

The present invention relates to a Viterbi decoder, and more particularly, to a Viterbi decoder which more simply implements a process of backtracking original data before error correction encoding from received data.

As is well known, in a general communication system, digital data (hereinafter, referred to as 'error correction') is used to detect or correct an error in digital data in order to detect and correct an error in digital data transmitted through a communication channel or stored in a storage medium. Code ”is added to the digital data to be transmitted or stored, and the error is detected using the error correction code thus added when decoding the received digital data or the stored digital data into the original digital data. Or by correcting, the reliability of digital data transmitted and received or digital data stored / read is improved.

Since the theory of such error correction codes was published by Cloud Shannon in 1947, the technique of encoding the error correction code in addition to the digital data and the error correction code were added to the original coded digital data. A number of techniques for decoding digital data have been developed. Among them, the Viterbi algorithm has been widely used in the field of digital data transmission, magnetic recording, voice recognition and communication since it was published in 1967 to decode convolutional code. It is used.

As described above, in the communication system, after performing error correction encoding during data transmission, a decoding process of restoring an original data string from received data, that is, error correction encoded data is required. A general Viterbi decoder which traces back the original data from the data will be schematically described with reference to FIG. 1.

First, in the present embodiment, a Viterbi decoder corresponding to an encoder having a constraint length of 3 and a code rate of 1/2 is taken as an example, and is limited to perform the source data traceback process according to the present embodiment. An encoder of length 3 and code rate 1/2 will be briefly described as follows.

1 is a block diagram showing an example of a conventional Viterbi decoder.

Referring to FIG. 1, a general Viterbi decoder includes a branch metric calculator (BMC) 100, an add compare selector 200, and a path metric memory. 300, a survival path memory 400 and a trace back unit 500 are used. The method of backtracking the original data in the Viterbi decoder is as follows. In this case, a bit string encoded by an encoder having a constraint length of 3 and a code rate of 1/2 is described as an example.

First, since the bit stream input by being demultiplexed is a bit stream encoded by an encoder having a limited length of 3, the bit to be input in a specific state will be 0 or 1. Accordingly, the branch metric calculation unit 100 calculates the branch metric when 0 is input and the branch metric when 1 is input, and adds the branch metric corresponding to the virtual input bits 0 and 1 to the comparison comparison selector 200. To provide.

The addition comparison selecting unit 200 receives a path value, that is, a path value that accumulates the branch metric on the surviving path in the previous state, from the path metric memory 300, and the branch metric corresponding to the path value and the virtual input bit 0. And add the branch metric corresponding to the path value and virtual input bit 1, and then compare the respective added path values with each other. The surviving path memory stores the addition value of the virtual input bit having the small addition as a new path value, while the state value transitioned by the virtual input bit having the small addition is the path bit. Save to 400. At this time, the path value provided from the path metric memory 300 is alternately read from two memories or two areas and provided to the comparison addition selecting unit 200 or to an address generator not shown. Is read out from a plurality of areas that are cyclically designated by the address, and is provided to the comparison addition selection unit 200.

The backtracker 500 performs the backtracking based on a path bit of each bit input time point, that is, a state value at each time point, located on the survival path stored in the survival path memory 400 by such a process. Trace source data from route information. In this case, the preset backtracking path information is paths in all cases determined corresponding to the configuration of the encoder.

However, in the conventional Viterbi decoder, since backtracking is performed for every input bit, the computational amount is large. Therefore, the mobile terminal employing the battery-powered method not only has a problem of high power consumption, but also has a deeper path. The operation time is long, there is a problem of reducing the signal processing speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide a method for backtracking a source data of a Viterbi decoder suitable for reducing the amount of computation and the time required for backtracking.

In order to achieve the above object, in the present invention, in the Viterbi decoder for backtracking the original data from the added and selected path bits, the path bits are serially provided by a predetermined number of bits, and stored in parallel. Serial-to-parallel transition memory; A plurality of pretrace path bits on which the previous traceback process was performed, a current trace path bit provided from the serial-parallel transition memory, data bits previously decoded by the trace track path bits, and the current trace track path bits. A memory in which data bits decoded by the memory are stored in bank units; The unit path bits of the current traceback path bits and the representative bits of the plurality of traceback path bits are compared, so that the path bits before the path bits of the current traceback path match with the representative bits are matched to the current path bits. And a back tracer for outputting the decoded data based on the output bit, and outputting the data bits decoded by the back trace path bits after the path bits of the current trace back path match with the representative bits. To provide.

1 is a block diagram showing an example of a conventional BTV decoder,

2 is a block diagram showing an example of a Viterbi decoder according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: branch metric calculation unit 200: comparison addition selection unit

300: path metric memory 400: survival path memory

410: write bank 420/1 to 420 / n: decryption bank

430: preliminary decryption bank 440: decryption bank

500: traceback unit 510: comparator

520/1 to 520 / n: representative bit memory 530: first multiplexer

540: counter 550: first parallel serial transition memory

560: second parallel serial transition memory 570: second multiplexer

Hereinafter, with reference to the accompanying FIG. 2, a Viterbi decoder according to a preferred embodiment of the present invention will be described.

The core technical idea of the present invention is to 'determine whether the path of the back trace is consistent with the path of the previous trace in the process of performing the current trace, taking into consideration that the decoded path has a high probability in the process of trace back the source data, If the current traceback is matched with the previous traceback path in a specific state, by mapping the path bit string previously stored in the traceback, the operation amount of the traceback is reduced and the calculation time is shortened. The embodiment to be understood will be understood based on the core technical idea of the present invention as such.

2 is a block diagram of a Viterbi decoder according to a preferred embodiment of the present invention.

Referring to FIG. 2, the Viterbi decoder according to the preferred embodiment of the present invention is similar to the general Viterbi decoder, such as the branch meter calculation unit 100, the addition comparison selector 200, the path metric memory 300, and the survival path. The memory 400 and the traceback unit 500, but in order to achieve the core technical idea of the present invention, a serial-to-parallel transition memory 600 between the addition comparison selection unit 200 and the survival path memory 400, Further, the survival path memory 400 and the traceback unit 500 has the following characteristics, respectively.

First, the serial-to-parallel transition memory 600 sequentially stores path bits provided from the addition comparison selection unit 200 in series, and when the preset number of bits (for example, 8 bits) is reached, the preset number of bits The path bits of are provided in parallel to the survival path memory 400. In a preferred embodiment of the present invention, a path currently being traced back (hereinafter referred to as a 'current traceback path') for each predetermined bit unit (for example, 8 bits set as described above) and previously reversed. In order to determine whether the traced and stored traceback paths (hereinafter referred to as 'trace trace paths') are matched, the serially provided path bits are shifted in parallel, but in such a way to reduce the number of accesses by storing them in memory in parallel, As a result, a side effect of reducing power consumption can be obtained.

The survival path memory 400 is composed of a plurality of banks having a storage capacity of a predetermined bit unit, and in particular, the write bank 410, the traceback banks 420/1 to 420 / n, and the reserved decoding bank. 430, and a decryption bank 430, each of which operates as follows.

First, in the write bank 410, path bits provided in parallel in the parallel-parallel transition memory 600 are stored, and path bits corresponding to one state transition among the stored path bits (hereinafter, 'unit path bits'). Are provided to the comparator 510 sequentially.

Also, a plurality of path bits included in the backtracking path are stored in a predetermined number of bits (for example, 8 bits) in the plurality of backtracking banks 420/1 to 420 / n. Each time a bit is updated, the most significant path bit or the start path bit of each bank among the updated path bits is stored in the representative bit memories 520/1 to 520 / n corresponding to each bank.

The data decoded by the current traceback path is stored in the preliminary decryption bank 430, and the data decoded by the traceback path is stored in the decryption bank 440.

The tracer 500 may include a comparator 510, a plurality of representative bit memories 520/1 to 520 / n, a first multiplexer 530, a counter 540, and a first parallel serial transition memory 550, The second parallel serial transition memory 560 and the second multiplexer 570, each operation is as follows.

First, the comparator 510 is a unit path bit provided from the write bank 410 of the survival path memory 400 and one of the representative bit memories 520/1 to 520 / n through the first multiplexer 540. Compares the representative bits provided from &lt; RTI ID = 0.0 &gt; and &lt; / RTI &gt; and provides the second multiplexer 570 with information about a match or inconsistency (e.g., a match outputs a '1' mismatch to '0').

In the representative bit memories 520/1 to 520 / n, the representative bits are stored corresponding to each of the plurality of traceback banks 400/1 to 400 / n provided in the survival path memory 400, and the representative bits are stored in the representative bit memories 520/1 to 520 / n. The bits are again provided to the first multiplexer 530. In this case, the representative bit is a start bit or most significant bit among the path bits stored in each traceback bank, and will be a state value at one time point.

The first multiplexer 530 provides the comparator 540 with representative bits provided in any one of the plurality of representative bit memories 520/1 to 520 / n based on the count value of the counter 540.

The counter 540 counts from 1 to n for the plurality of representative bit memories 520/1 to 520 / n, and provides the count value to the first multiplexer 530, thereby providing a first multiplexer 530. In this example, the representative bits provided from any one of the plurality of representative bit memories 520/1 to 520 / n can be provided to the comparator 510.

The first and parallel transition memory 550 consists of last-in-first-out (LIFO) memory and is provided in parallel from the preliminary decryption bank 430 (ie, by backtracking by the current path bit). Decoded data) to one end of the second multiplexer 570.

The second parallel serial transition memory 560, like the first parallel serial transition memory 550, consists of a last-in-first-out (LIFO) memory, and is provided with data provided from the decryption bank 440. Data previously decoded by the traceback path) is provided to the other end of the second multiplexer 570.

The second multiplexer 570 outputs the decoded data bits provided from the first parallel serial transition memory 550 or the second parallel serial transition memory 560 based on the comparison result provided from the comparator 510. do.

Hereinafter, the operation of the Viterbi decoder configured as described above according to the present invention will be described. In this case, since it has been described in the above-described prior art, the step before the process of selecting the path bit in the addition comparison selecting unit 200 is omitted, and the path bit selected in the addition comparison selecting unit 200 is a serial-parallel transition memory according to the present invention. The process provided at 600 will be described.

First, when the path bits are serially provided from the addition comparison selection unit 200, the serial / parallel transition memory 600 sequentially stores the received path bits, and then the stored data has a preset number of bits (for example, , 8 bits), the data is stored in parallel in the write bank 410 of the survival path memory 400.

The write bank 410 sequentially provides the comparator 510 for each unit path bit among the path bits provided in parallel in the serial / parallel transition memory 600.

Meanwhile, in the plurality of traceback banks 420/1 to 420 / n included in the survival path memory 400, a plurality of path bits included in the traceback path are preset bit numbers (for example, 8 bits). Representative bit memories 520/1 to 520 / n each stored in units, and each time the stored path bit is updated, the most significant path bit or the start path bit of each bank of the updated path bits corresponds to the bank, respectively. Are stored in.

Each time the representative bit memories 520/1 to 520 / n provide the unit path bits to the comparator 510 in the write bank 410, they are provided in the traceback banks 420/1 to 420 / n. When the received representative bit is provided to the first multiplexer 530, the first multiplexer 530 may select any one of a plurality of representative bit memories 520/1 to 520 / n based on the count value of the counter 540. Provides a representative bit provided in the comparator 540. At this time, the counter 540 counts 1 to n for the plurality of representative bit memories 520/1 to 520 / n, and provides the count value to the first multiplexer 530.

As such, the comparator 510, which has received the path bits from the write bank 410 and the first multiplexer 530, respectively, is composed of the unit path bits provided from the write bank 410 of the surviving path memory 400 and the first path bits. The multiplexer 540 compares the representative bits provided from the representative bit memory 520/1 to 520 / n, and the information about the match or the inconsistency (for example, the match is determined according to the comparison result). '1' mismatch outputs '0') to the second multiplexer 570. That is, since the path bits are stored in the plurality of backtracking banks 420/1 to 420 / n in bit units preset by the serial-parallel transition memory 600, the representative bits and the path bits provided by the write bank 410 are provided. The operation of the comparator 510 for comparing the current path, which is currently being traced back for each predetermined section (hereinafter, referred to as 'current traceback path') and the traceback path previously stored backtracked (hereinafter, referred to as 'track trace path') Will be judged to match.

Meanwhile, the data decoded by the current traceback path is stored in the preliminary decryption bank 430, and the data decoded by the traceback path is stored in the decryption bank 440. The first and the other ends of the second multiplexer 570 are provided by the first and parallel serial transition memory 550 and the second parallel serial transition memory 560, so that the second multiplexer 570 is a comparator 510. Based on the comparison result of, the data provided at both ends is selectively output. That is, when the comparison result of the comparator 510 matches the current trace path and the current trace path, the decoded data is output by the trace path, and if the trace path and the current trace path do not match, the current path is output. The decoded data is output by backtracking by bit.

According to the present invention described above, by comparing the current backtracking path for each predetermined section of the backtracking path, if it matches, the data decoded by the backtracking path is output, and if it is mismatched, the decoding is performed by the current backtracking path. Therefore, the amount of computation and the computation time performed on the decoding of the current traceback path coinciding with the traceback path can be shortened.

Claims (3)

In a Viterbi decoder for tracing back original data from an added comparison selected path bit, A serial / parallel transition memory which receives the path bits in series by a predetermined number of bits, and converts the path bits in parallel; A plurality of pretrace path bits on which the previous traceback process was performed, a current trace path bit provided from the serial-parallel transition memory, data bits previously decoded by the trace track path bits, and the current trace track path bits. A memory in which data bits decoded by the memory are stored in bank units; The unit path bits of the current traceback path bits and the representative bits of the plurality of traceback path bits are compared, so that the path bits before the path bits of the current traceback path match with the representative bits are matched to the current path bits. And a back tracer for outputting the decoded data based on the output bit, and outputting the data bits decoded by the back trace path bits after the path bits of the current trace back path match with the representative bits. . The method of claim 1, wherein the memory, A write bank in which path bits provided in parallel in the serial to parallel memory are stored; A plurality of backtracking banks in which a plurality of path bits included in the backtracking path are stored in units of a predetermined number of bits; A preliminary decryption bank in which data bits decoded by the current traceback path are stored; And a decoding bank in which data decoded by the backtracking path is stored. The method of claim 2, wherein the backtracking unit, A plurality of representative bit memories for storing the representative bits corresponding to each of the plurality of traceback banks; A counter for counting from 1 to n (n = integer) for the plurality of representative bit memories; A first multiplexer for selectively outputting a representative bit provided in any one of the plurality of representative bit memories based on a count value of the counter; A comparator for comparing a representative bit output from the first multiplexer with a path bit provided from the write bank; A first parallel serial memory which receives data bits decoded by the current traceback path from the preliminary decoding bank in parallel and outputs them in series; A second parallel serial memory for receiving data decoded by the backtracking path in parallel from the decryption bank and outputting the data in parallel; Based on a comparison result of the comparator, if the representative bit output from the first multiplexer and the path bit provided from the write bank do not match, the data bit provided from the first parallel-transition memory is output; And a second multiplexer for outputting the data bits provided by the second parallel serial transition memory.