JPH01288939A - Weight state generator for centeral processor unit - Google Patents

Abstract

PURPOSE:To suitably extend the memory read signal and write signal of a CPU by using a BUSY signal provided for the use of an option device, and inserting a weight state (WT) among the four states of the CPU. CONSTITUTION:A command receiving signal 1 receives a memory read signal 8 and a memory write signal 9, and makes a signal 5 active. An address selector means 2 judges an address, and selectively makes a signal 6 active. When the weight state (TW) is prohibited to be inserted in such a case as a DMA transfer, the signal 6 is not made active. A counting means 3 counts the clock of the CPU, controls a BUSY signal output means 4, and a BUSY signal 12 is made active by the signals 5 and 6. When the CPU passes through the TW at a prescribed number, the signal 12 is made nonactive again by a signal 7. Then, the CPU completes a read cycle or a write cycle, and the signal 12 is made into a high impedance again by the signal 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a central processing system for inserting a desired number of wait states between T3 state and T4 state in the operating clock of a CPU of a personal computer.
The present invention relates to a wait state generator for a processor unit.

[Conventional technology]

80, which is conventionally used in personal computers.
The system CPU has four states, TIT2T3T4, but when accessing slow-operating optional devices (hard disks, floppy disks, printers, etc.), a wait state (hereinafter TIT2T3T4) is inserted between T3 and 'r4. W) is inserted. With this operation,
The CPU's read/write signals are routed, allowing the CPU to access slow-operating optional devices. This operation is performed when the optional device is
Triggered by issuing the SY signal. The optional device connector is provided with an interface for the optional device to send a BUSY signal to the CPU.

[Problem to be solved by the invention]

Recently, in order to increase the processing speed of personal computers, models with higher CPU operating clock frequencies have been introduced. However, there is a problem in that application software created for personal computers with conventional operating clock frequencies may not run on personal computers with high operating clock frequencies. One possible cause of such a phenomenon is that the portion of the application software where timing is determined by a loop instruction becomes shorter as the frequency of the operating clock increases. Therefore, in order to solve this conventional problem, the present invention uses the BtJSY signal provided for the optional device to generate TW even when the CPU accesses a predetermined memory. The object of the present invention is to obtain a wait state generator for a central processor unit that partially slows down the operation of the central processor unit and allows the application software to run.

[Means to solve the problem]

As shown in FIG. 1, the wait state generator for a central processor unit of the present invention comprises command receiving means 1 for receiving and receiving read/write signals from the CPU, address selection means 2, and a CPU operating clock. and a BUSY signal output hand Pi4 which is controlled by the command receiving means 1, address selection means 2, and counting means 3 and outputs a BUSY signal.

[For production]

A wait state generator for a central processor unit according to the present invention will be explained based on FIG. The command receiving means 1 receives the memory from the CPU through the optional device connector of the personal computer.
It receives the read signal 8 or the memory write signal 9 and makes the signal 5 active. The address selection means 2 is the CP
The address to be accessed by U is determined and signal 6 is selectively activated. The address is communicated to the address selection means 2 via an address bus 10.

There are cases, such as DMA transfer, where TW should not be inserted into the CPU state. The memory area used in DMA transfer is set in the address selection means 2, and when this address is accessed, the signal 6 will not become active.The counting means 3 counts the CPU operating clock and sends the BUSY signal through the signal 7. The generating means 4 is controlled. The BUSY signal generating means 4 outputs a BUSY signal 12. BtJS
The Y signal 12 is normally in a high impedance state,
The signal 5.6 makes the BUSY signal active.

After the CPU has passed through a predetermined number of TWs, the signal 7 makes the BUSY signal 12 non-active again. Then, the CPU ends the read cycle or write cycle, and the signal 5 causes the BUSY signal 12 to go into a high impedance state again.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A wait state generator for a central processor unit according to the present invention will be described below based on an embodiment. FIG. 2 is a diagram showing an embodiment of the present invention, in which an OR gate 13, an AND gate 14, a decoder 15, a 3-state gate 17, a read/write signal detection circuit 16, a counting circuit 18, an initial Consists of one value setting circuit. The BUSY signal 12, memory read signal 8, memory write signal 9, address bus 10, and CPU operating clock 11 are connected to an optional device connector of the personal computer. Memory read signal 8 and memory write signal 9 are received by OR gate 13 and transmitted via signal 20 to AND gate 14 and read/write signal detection circuit 16. Decoder 1
5 decodes the address bus 1O and tells the AND gate 14 via signal 21 whether a memory address that is allowed to insert 1'W is being accessed.

AND gate 14 controls three-state gate 17 via signal 22. The three-state gate 17 connects or disconnects the signal 23 and the BUSY signal based on the signal 22. The read/write signal detection circuit 16 activates the signal 23 at the same time that the signal 20 becomes active and starts the counting circuit 18 via the signal 24. Counting circuit 1
8 counts the operating clock 11 of the CPU, controls the read/write signal detection circuit 16 via the signal 25, and makes the signal 23 non-active. Then BUSY signal 1
2 also becomes non-active, the CPU finishes the memory read cycle or memory write cycle,
Along with this, the signals 20 and 22 also become non-active, and the signals 23 and BUSY signal 12 become the 3-state gate 17.
separated by The initial value setting circuit 19 sets the initial value of the counting circuit 18. TW to be inserted by this
The number of is determined. The correspondence between the block diagram in FIG. 1 and the circuit diagram in FIG. 2 is that the OR gate 13 and the AND gate 14
is the command receiving means, the decoder 15 is the address selection means 2, and the read/write signal detection circuits 16 and 3
The state gate 17 is the BUSY signal output means 4,
The counting circuit 18 and the initial value setting circuit 19 constitute the counting means 3.

〔Effect of the invention〕

As explained above, the wait state generator for the central processor unit of the present invention has optional features.
Using the BUSY signal provided for the device,
A TW is inserted between the four states of the CPU. By this operation, the CPU memory read signal, memory
Light signals can be stretched appropriately. This operation solves the problem that aggregation software does not operate normally on a personal computer with a high operating clock frequency due to the software timer being shortened due to a loop command or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a wait state generator for a central processor unit of the present invention. FIG. 2 is a circuit diagram of an embodiment of the present invention. 5...Signal 6...Signal 7...Signal 20...Signal 21...Signal 22...Signal 23...Signal 24...Signal 25...Signal and above Applicant Seiko Epson Agent Co., Ltd. Patent attorney Kizobe Suzuki (and 1 other person) Figure 1

Claims (1)

[Claims] A command receiving means for receiving a memory read signal and a memory write signal, an address selection means for selecting a memory address, and a central processor unit (
Hereinafter, it will be referred to as CPU. ), the command receiving means, the address selection means, and the counting means control the BUS.
It consists of a BUSY signal output means that outputs a Y signal, and the BU
A wait state generation device for a central processor unit, characterized in that it generates a wait state in a CPU by outputting a SY signal.