JPH01287945A - Manufacture of gate array system semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to constitute a logical circuit having different functions by a method wherein a master wafer, on which basic cells are regularly arranged, is formed in advance and a different wiring mask is used according to the kind of device by using said mask wafer in common. CONSTITUTION:Each unit 4, the surface of which is divided by a dicing line 2, is provided with an appropriate number of gate regions 6, a wiring region 8 is arranged between the gate regions 6, and these regions 6 and 8 are regularly arranged. On the gate region 6, the gate of an MOS transistor basic circuit is fixed regularly and arranged. Said master wafer is used common in a custom process, an one or a plurality of units 4 are used in accordance with the number of gates of the desired logical circuit. The dicing line 2a in lateral direction is used as a wiring region, for example, and the dicing line 2b in longitudinal direction is used in a wiring region and the region for a power source line. As a result, a semiconductor integrated circuit device, having different number of gates, can be manufactured.

Description

Detailed Description of the Invention (Technical Field) The present invention involves creating a master wafer in which basic cells are arranged regularly, using that mask wafer in common, and using a different wiring mask for each product to create different The present invention relates to a method of manufacturing a gate array type semiconductor integrated circuit device that constitutes a functional logic circuit.

(Prior art) In the gate array method, a master wafer in which basic cells are arranged regularly is manufactured in advance, regardless of the product type, until the diffusion step in the wafer manufacturing process, and a wiring mask that differs depending on the product type is used for the subsequent wiring steps. This method realizes semiconductor integrated circuit devices with different functions by performing the following steps. The gate array method is an advantageous method for shortening the design period and prototyping period, and responding to the production of a wide variety of products in small quantities.

However, the number of gates required varies depending on the type of product, and varies from several hundred gates to several hundred gates, for example. For this reason, master wafers with different numbers of gates are prepared by appropriately dividing the number of gates, for example, 2000 gates, 4000 gates, and 6000 gates. Therefore, the production quantity (inventory quantity) of several types of master wafers must be adjusted, and the feature of the gate array method, which is convenient for low-volume, high-mix production, cannot be fully utilized.

(Objective) An object of the present invention is to provide a method by which semiconductor integrated circuit devices having different numbers of gates can be manufactured by simply preparing one type of master wafer.

(Structure) In the present invention, a mounting wafer including a plurality of units in which basic circuits are regularly arranged in an area surrounded by a dicing line is formed, and one or more units of the basic circuit are arranged per chip after the wiring process. Configure logic circuits using units and wiring masks for each product type.

Examples will be specifically described below.

FIG. 1 shows a portion of a master wafer in one embodiment.

The wafer surface is divided by dicing lines 2 into regions 4 called units.

Each unit 4 includes an appropriate number of gate regions 6, as shown in FIG.

In the example of the unit 4 in FIG. 2, a wiring region 8 is arranged between the gate regions 6, and these regions 6, 8 are repeatedly arranged regularly. However, the wiring area 8 may not be provided in the unit 4, and gates may be spread over the entire surface.

In the gate region 6, gates of MOS transistor basic circuits are regularly fixed and arranged.

Unit 4 also does not have an I10 area for a bonding pad. However, for each unit 4 I
Ten areas may be provided.

This master wafer is commonly used in the customization process, and one
one or more units 4 are used. For example, as shown in FIG. 3, four units 4 constitute one chip, and for example, as shown in FIG.
The units 4 constitute one chip.

The area surrounded by chain lines in FIGS. 3 and 4 represents the size of one chip.

If one unit 4 includes, for example, 500 gates, a logic circuit of 2000 gates can be integrated with one chip shown in FIG. 3, and a logic circuit of 4500 gates can be integrated with one chip shown in FIG. be able to.

FIG. 5 shows an example in which a semiconductor integrated circuit device chip is formed using four units 4 as shown in FIG.

A bonding pad 10 is arranged inside the periphery of the chip. A bonding pad 10 is formed on the gate region 6. The turnout cover sofa circuit is constructed using the gates in the gate region 6.

Dicing lines outside the area including the four units 4 are used when dicing this chip. Inside the chip, dicing lines 2a in the horizontal direction (in the same direction as the column direction of the gate regions 6) and vertical dicing lines 2b remain in the figure. The horizontal dicing line 2a is used, for example, as a wiring area, and the vertical dicing line 2b
can be used, for example, as a wiring area and a power supply line area, and dicing lines inside the chip can be used effectively.

(Effects) In the present invention, a mounting wafer is formed that includes a plurality of units in which basic circuits are regularly arranged in an area surrounded by a dicing line, and one or more of the units per chip are formed after the wiring process. Since the logic circuit is configured using wiring masks for each type of wafer, it is only necessary to prepare one type of master wafer before performing the wiring process, and costs can be reduced due to mass production effects. becomes. In addition, production management (inventory management) does not require manpower.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing a part of a master wafer' of one embodiment, FIG. 2 is a schematic plan view showing one unit of the same wafer, and FIGS. 3 and 4 each show a chip area in the embodiment. Schematic Plan View FIG. 5 is a schematic plan view showing an example of one chip of an embodiment. 2... Dicing line, 4... Unit, 6... Gate area.

Claims (1)

[Claims] (1) A master wafer is formed that includes a plurality of units in which basic circuits are regularly arranged in an area surrounded by a dicing line, and one or more of the units are used for one chip in the wiring process and thereafter. , a method for manufacturing a gate array type semiconductor integrated circuit device that configures a logic circuit using wiring masks for each product type.