JPH01282843A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01282843A JPH01282843A JP11318288A JP11318288A JPH01282843A JP H01282843 A JPH01282843 A JP H01282843A JP 11318288 A JP11318288 A JP 11318288A JP 11318288 A JP11318288 A JP 11318288A JP H01282843 A JPH01282843 A JP H01282843A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- package
- gate
- semiconductor device
- accuracy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 33
- 239000011347 resin Substances 0.000 claims abstract description 33
- 239000008188 pellet Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 239000006185 dispersion Substances 0.000 abstract 2
- 239000000945 filler Substances 0.000 abstract 1
- 238000000465 moulding Methods 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置のパッケージ外形に関し、特に樹
脂注入口(ゲート)部の形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the outer shape of a package of a semiconductor device, and particularly to the shape of a resin injection port (gate).
従来、樹脂封止型半導体装置では、熱硬化性樹脂(エポ
キシ樹脂等)を射出成形するため、パッケージ側面の樹
脂面上にゲート部を配置している。Conventionally, in a resin-sealed semiconductor device, a gate portion is disposed on the resin surface of the side surface of the package because thermosetting resin (epoxy resin, etc.) is injection molded.
第3図に、従来の絶縁型半導体装置成形金型の縦断面図
を示す。第3図に示す通り、キャビティ9内に半導体ペ
レット6を載せた金属リード2が固定され、樹脂がゲー
ト3を通してキャビティ9内に射出成形される。第4図
(a)は、上記成形により完成したパッケージ外形を上
面より見た図で第4図(b)は、第4図(a)を矢印C
側より見たパッケージ外形図であり、ゲート3(斜線部
)がパッケージ側面5の樹脂面に配置されている。FIG. 3 shows a longitudinal cross-sectional view of a conventional insulated semiconductor device molding die. As shown in FIG. 3, the metal lead 2 carrying the semiconductor pellet 6 is fixed in the cavity 9, and resin is injection molded into the cavity 9 through the gate 3. Fig. 4(a) is a top view of the package outer shape completed by the above molding, and Fig. 4(b) shows the arrow C shown in Fig. 4(a).
This is an external view of the package seen from the side, and the gate 3 (shaded area) is arranged on the resin surface of the package side surface 5.
上述した従来の樹脂絶縁型半導体装置は、樹脂射出成形
後のゲート部切断時に樹脂残り8(第4図)がα=1〜
4mm程度発生してパッケージ外形寸法(図中1寸法)
のバラツキが大きくなり、寸法精度の低下を起すという
欠点がある。特に、近年、高密度実装化により、外形寸
法精度に関する要求は厳しくなっている。In the conventional resin insulated semiconductor device described above, when the gate portion is cut after resin injection molding, the remaining resin 8 (FIG. 4) is
Approximately 4mm is generated and the package external dimensions (dimension 1 in the diagram)
This has the disadvantage that the variation in size increases, resulting in a decrease in dimensional accuracy. In particular, in recent years, demands regarding external dimensional accuracy have become stricter due to high-density packaging.
本発明の半導体装置は、半導体ペレットを載せた金属製
リードを樹脂封止したモールド成形式絶縁型半導体装置
において、パッケージ側面に1〜5mmの段差を設けた
樹脂切欠き部に樹脂注入口(ゲート)を配置している。The semiconductor device of the present invention is a molded insulated semiconductor device in which a metal lead carrying a semiconductor pellet is sealed with resin. ) are placed.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)は本発明の一実施例のパッケージ上面図で
ある。樹脂1により半導体ペレット6を載せた金属リー
ド2が封止され、パッケージ側面(図中矢印A側)の樹
脂面より1〜5胴の段差を有した樹脂切欠き部4にゲー
ト3を配置している。FIG. 1(a) is a top view of a package according to an embodiment of the present invention. A metal lead 2 carrying a semiconductor pellet 6 is sealed with a resin 1, and a gate 3 is placed in a resin notch 4 having a height difference of 1 to 5 cylinders from the resin surface on the side of the package (arrow A side in the figure). ing.
また、矢印A側より見たパッケージ外形図(第1図(b
))は、ゲート3(斜線部)が樹脂切欠き部4に配置し
ていることを示す。In addition, the package outline as seen from the arrow A side (Fig. 1 (b)
)) indicates that the gate 3 (shaded area) is arranged in the resin cutout 4.
第2図(a)は本発明の他の実施例のパッケージ上面図
である。本実施例は、金属リード2の導出された樹脂側
面5の金属リード2間に2ケ所の樹脂切欠き部4を形成
し樹脂切欠き部4にゲート3を配置したものである。効
果は一実施例と同じく、パッケージ外形寸法(図中1寸
法)の精度を確保することが可能となる。FIG. 2(a) is a top view of a package of another embodiment of the present invention. In this embodiment, two resin notches 4 are formed between the metal leads 2 on the resin side surface 5 from which the metal leads 2 are led out, and gates 3 are arranged in the resin notches 4. As with the first embodiment, the effect is that the accuracy of the package external dimensions (dimension 1 in the figure) can be ensured.
〔発明の効果〕
以上説明した通り、本発明はゲート部を樹脂側面に対し
て1〜5mmの段差を有した樹脂切欠き部に配置するこ
とにより、ゲート樹脂残りによる寸′法バラツキの影響
を排除し、パッケージ寸法(図中では1寸法)の精度を
確保できる。[Effects of the Invention] As explained above, the present invention eliminates the influence of dimensional variations due to remaining gate resin by arranging the gate portion in a resin notch having a step of 1 to 5 mm from the resin side surface. The accuracy of the package dimensions (one dimension in the figure) can be ensured.
第1図(a)は本発明の一実施例のパッケージ上面図、
第1図(b)は第1図(a)図中矢印A側より見たパッ
ケージ外形図、第2図(a)は本発明の他の実施例のパ
ッケージ上面図、第2図(b)は第2図(a)中矢印B
側より見たパッケージ外形図、第3図は従来の絶縁型半
導体装置成形金型の縦断面図、第4図(a)は従来の絶
縁型半導体装置のパッケージ上面図、第4図(b)は第
4図(a)中矢印C側より見たパッケージ外形図である
。
1・・・・・・樹脂、2・・・・・・金属リード、3・
・・・・・ゲート、4・・・・・・樹脂切欠き部、5・
・・・・・樹脂側面、6・・・・・・ペレット、7・・
・・・・成形金型、8・・・・・・樹脂残り、9・・・
・・・キャビティ。
代理人 弁理士 内 原 晋
万1図
第Z回FIG. 1(a) is a top view of a package according to an embodiment of the present invention;
Fig. 1(b) is an external view of the package seen from the arrow A side in Fig. 1(a), Fig. 2(a) is a top view of a package of another embodiment of the present invention, and Fig. 2(b) is the middle arrow B in Fig. 2 (a)
3 is a vertical cross-sectional view of a conventional insulated semiconductor device molding die; FIG. 4(a) is a top view of a conventional insulated semiconductor device package; FIG. 4(b) 4(a) is a package external view seen from the arrow C side in FIG. 4(a). 1...Resin, 2...Metal lead, 3.
...Gate, 4...Resin notch, 5.
...Resin side, 6...Pellet, 7...
...Molding mold, 8... Resin remaining, 9...
···cavity. Agent Patent Attorney Shinman Uchihara Figure 1 No. Z
Claims (1)
モールド成形式絶縁型半導体装置において、パッケージ
側面に段差を設けた樹脂切欠き部に樹脂注入口部を配置
することを特徴とする半導体装置。1. A molded insulated semiconductor device in which a metal lead carrying a semiconductor pellet is sealed with resin, characterized in that a resin injection port is disposed in a resin notch with a step formed on a side surface of the package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11318288A JPH01282843A (en) | 1988-05-09 | 1988-05-09 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11318288A JPH01282843A (en) | 1988-05-09 | 1988-05-09 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01282843A true JPH01282843A (en) | 1989-11-14 |
Family
ID=14605630
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11318288A Pending JPH01282843A (en) | 1988-05-09 | 1988-05-09 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01282843A (en) |
-
1988
- 1988-05-09 JP JP11318288A patent/JPH01282843A/en active Pending
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