JPS6354222B2 - - Google Patents
Info
- Publication number
- JPS6354222B2 JPS6354222B2 JP57228953A JP22895382A JPS6354222B2 JP S6354222 B2 JPS6354222 B2 JP S6354222B2 JP 57228953 A JP57228953 A JP 57228953A JP 22895382 A JP22895382 A JP 22895382A JP S6354222 B2 JPS6354222 B2 JP S6354222B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- conductor pattern
- integrated circuit
- circuit element
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920005989 resin Polymers 0.000 claims description 25
- 239000011347 resin Substances 0.000 claims description 25
- 239000004020 conductor Substances 0.000 claims description 20
- 238000000465 moulding Methods 0.000 claims description 13
- 238000007789 sealing Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electric Clocks (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は回路ブロツクの樹脂封止構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed structure for a circuit block.
以下、腕時計用の回路ブロツクを中心に述べ
る。第２図ａは従来方式による樹脂封止構造の概
念図であり、第２図ｂは第２図ａの断面図であ
り、第３図ａは従来方式による他の樹脂封止構造
の概念図であり、第３図ｂは第３図ａの断面図で
ある。従来一般的に腕時計用の回路ブロツクにお
いては、その組み込まれた集積回路素子（以下
ICチツプと呼ぶ。）をエポキシ系樹脂にてモール
ドすることにより、その信頼性を確保しており、
回路基板にICチツプがフエースダウンボンデイ
ングされている場合、そのICチツプのモールド
方法は、第２図ａ，ｂに示すように、回路基板４
のICチツプ１の能動面に対向した部分に穴５を
設け、これを利用して樹脂を流し込み封止するも
のであつた。
Below, we will mainly discuss circuit blocks for wristwatches. Figure 2a is a conceptual diagram of a conventional resin sealing structure, Figure 2b is a sectional view of Figure 2a, and Figure 3a is a conceptual diagram of another conventional resin sealing structure. 3b is a sectional view of FIG. 3a. Conventionally, in circuit blocks for wristwatches, the integrated circuit elements (hereinafter referred to as
It is called an IC chip. ) is molded with epoxy resin to ensure its reliability.
When an IC chip is face-down bonded to a circuit board, the method for molding the IC chip is as shown in Figure 2a and b.
A hole 5 was provided in the part facing the active surface of the IC chip 1, and resin was poured into the hole 5 to seal it.
しかし前述の従来技術では、第２図ａ，ｂのよ
うな場合には問題ないが、第３図ａ，ｂに示すよ
う、ICチツプ１の能動面に対向した部分に、回
路導体パターン７が穴５を取り囲むように配置さ
れている場合には集積回路素子封止用樹脂６（以
下モールド用樹脂と呼ぶ）の流れがその導体パタ
ーンに妨げられて、IC表面全面にモールド用樹
脂６が流れ込まずに充填不足となる場合が発生す
るという問題点を有する。特にこの現象はフエー
スダウンボンデイング後、ICチツプ表面と導体
パターン３の空隙すなわちバンプ２の高さが小さ
い場合には顕著である。また、ICチツプの能動
面に対向した位置にあるオーバーハングしていな
い導体パターン７のようなICチツプの能動面に
対向した部分の導体パターン引き回しは、高密度
ICを実装する必要がある場合及び他の同種の商
品とICを共通に用いたい場合などに必然的に要
求される配置である。
However, with the above-mentioned prior art, there is no problem in the cases shown in FIGS. 2a and 2b, but as shown in FIGS. When the holes 5 are arranged so as to surround the holes 5, the flow of the integrated circuit element sealing resin 6 (hereinafter referred to as molding resin) is obstructed by the conductor pattern, and the molding resin 6 flows over the entire surface of the IC. However, there is a problem in that there are cases where insufficient filling occurs. This phenomenon is particularly noticeable after face-down bonding when the gap between the IC chip surface and the conductor pattern 3, that is, the height of the bump 2 is small. In addition, the conductor pattern routing in the portion facing the active surface of the IC chip, such as the non-overhanging conductor pattern 7 located opposite the active surface of the IC chip, is highly dense.
This arrangement is inevitably required when it is necessary to mount an IC or when it is desired to use the IC in common with other similar products.
そこで本発明はこのような問題点を解決するも
ので、その目的とするところは、前述のように
ICチツプの能動面に対向した部分に回路導体パ
ターンの引き回しがある場合でも、特にコストア
ツプすることなく、IC裏面、つまり能動面全域
に渡つてモールド用樹脂を流し込むことを可能に
できる回路ブロツクの樹脂封止構造を提供すると
ころにある。 Therefore, the present invention is intended to solve these problems, and its purpose is to
A circuit block resin that makes it possible to pour molding resin over the back side of the IC, that is, the entire active side, without increasing costs, even if the circuit conductor pattern is routed on the part facing the active side of the IC chip. It provides a sealing structure.
本発明の回路ブロツクの樹脂封止構造は、回路
基板の表面にフエースダウンボンデイングされた
集積回路素子を有する回路ブロツクの樹脂封止構
造において、前記集積回路素子の能動面に対向す
る位置の回路基板に、前記集積回路素子の外形よ
りは小さいモールド用穴が形成され、回路の導体
パターンが前記モールド用穴上に形成され、且つ
樹脂封止されることを特徴とする。
The resin-sealed structure of a circuit block of the present invention is a resin-sealed structure of a circuit block having an integrated circuit element face-down bonded to the surface of a circuit board, in which a circuit board at a position facing an active surface of the integrated circuit element is provided. A molding hole smaller than the outer shape of the integrated circuit element is formed, and a circuit conductor pattern is formed on the molding hole and sealed with resin.
以下本発明の実施例を図面に基づいて詳しく説
明する。第１図ａ，ｂは本発明による樹脂封止構
造の概念図である。第１図において、１はICチ
ツプであり、バンプ２により、回路基板４上に引
き回された回路導体パターン３及び８にフエース
ダウンボンデイングされている。８は本発明によ
る構造の回路導体パターンであり、モールド用樹
脂６の注入用の穴５の上をオーバーハング状に横
断している点に特徴がある。このような構造とす
ることにより、穴５よりモールド用樹脂６を注入
した際に、８の導体パターンを包み込む状態にて
樹脂がIC裏面（能動面）に向かつて流入するた
め、第３図ｂにて示すようにモールド用樹脂６が
導体パターン７にて妨げられて流れない、あるい
は流れにくくなるという現象は解消され、ICチ
ツプ１の能動面全域をモールド用樹脂６にて完全
に覆うことが可能となる。
Embodiments of the present invention will be described in detail below based on the drawings. FIGS. 1a and 1b are conceptual diagrams of a resin sealing structure according to the present invention. In FIG. 1, reference numeral 1 denotes an IC chip, which is face-down bonded to circuit conductor patterns 3 and 8 routed on a circuit board 4 through bumps 2. Reference numeral 8 denotes a circuit conductor pattern having a structure according to the present invention, which is characterized in that it crosses over the hole 5 for injection of the molding resin 6 in an overhanging manner. With this structure, when the molding resin 6 is injected through the hole 5, the resin flows toward the back surface (active surface) of the IC, enveloping the conductor pattern 8, as shown in Fig. 3b. As shown in , the phenomenon in which the molding resin 6 is blocked by the conductor pattern 7 and does not flow or becomes difficult to flow is eliminated, and the entire active surface of the IC chip 1 can be completely covered with the molding resin 6. It becomes possible.
具体例をあげると、穴５の大きさはφ1.3mm、導
体パターン８の厚みは35μ、幅60μ、IC１と導体
パターン８との間隔は15μである。 To give a specific example, the size of the hole 5 is 1.3 mm, the thickness of the conductor pattern 8 is 35μ, the width is 60μ, and the distance between the IC 1 and the conductor pattern 8 is 15μ.
以上述べたように本発明によれば、集積回路素
子の能動面に対向する位置の回路基板に、前記集
積回路素子の外形よりは小さいモヘルド用穴を形
成し、回路の導体パターンが前記モールド用穴上
に形成されることにより、前記集積回路素子封止
用樹脂を注入する際には、該樹脂は前記モールド
用穴上の前記導体パターンを包み込むようにして
前記集積回路素子の能動面に向かつて流入し、前
記集積回路素子の外周部に至る前記樹脂の流動距
離も短くなり、従来のように前記導体パターンに
よつて前記樹脂の流動が妨げられないので、前記
集積回路素子の能動面全域が充填不足になること
なく完全に覆うことができ、前記集積回路素子と
導体パターンが湿気、外部圧力等から保護され品
質の安定化が図れる。また集積回路素子の能動面
に対向したモールド穴用を含む部分には他の導体
パターンを引き回すことも可能であり、これによ
り高密度に集積回路素子が実装できるという効果
を有する。さらに、導体パターンの新構造部につ
いても基板製作上他のオーバハング部と同一工程
にて製造することができるので、コストアツプす
ることなく形成可能である。
As described above, according to the present invention, the mold hole, which is smaller than the outer diameter of the integrated circuit element, is formed in the circuit board at a position facing the active surface of the integrated circuit element, and the conductor pattern of the circuit is formed for the mold. By forming the resin over the hole, when injecting the integrated circuit element sealing resin, the resin is directed toward the active surface of the integrated circuit element so as to wrap around the conductor pattern on the mold hole. The flow distance of the resin that once flowed to the outer periphery of the integrated circuit element is also shortened, and the flow of the resin is not hindered by the conductive pattern as in the conventional case, so that the entire active surface of the integrated circuit element is covered. can be completely covered without becoming insufficiently filled, and the integrated circuit element and conductor pattern can be protected from moisture, external pressure, etc., and quality can be stabilized. Further, it is also possible to route other conductor patterns in the portion including the mold hole facing the active surface of the integrated circuit element, which has the effect of allowing integrated circuit elements to be mounted at high density. Furthermore, since the new structure of the conductor pattern can be manufactured in the same process as other overhang parts in manufacturing the board, it can be formed without increasing costs.
第１図ａは本発明による樹脂封止構造の概念
図。第１図ｂは第１図ａの断面図。第２図ａは従
来方式による樹脂封止構造の概念図。第２図ｂは
第２図ａの断面図。第３図ａは従来方式による他
の樹脂封止構造の概念図。第３図ｂは第３図ａの
断面図。
１…ICチツプ、２…バンプ、３…回路基板導
体パターン、４…回路基板、５…モールド用穴、
６…モールド用樹脂、７，８…導体パターン。
FIG. 1a is a conceptual diagram of a resin sealing structure according to the present invention. FIG. 1b is a sectional view of FIG. 1a. FIG. 2a is a conceptual diagram of a conventional resin sealing structure. FIG. 2b is a sectional view of FIG. 2a. FIG. 3a is a conceptual diagram of another conventional resin sealing structure. FIG. 3b is a sectional view of FIG. 3a. 1...IC chip, 2...bump, 3...circuit board conductor pattern, 4...circuit board, 5...mold hole,
6... Resin for molding, 7, 8... Conductor pattern.
Claims (1)
グされた集積回路素子を有する回路ブロツクの樹
脂封止構造において、前記集積回路素子の能動面
に対向する位置の回路基板に、前記集積回路素子
の外形よりは小さいモールド用穴が形成され、回
路の導体パターンが前記モールド用穴上に形成さ
れ、且つ樹脂封止されることを特徴とする回路ブ
ロツクの樹脂封止構造。1. In a resin-sealed structure of a circuit block having an integrated circuit element face-down bonded to the surface of a circuit board, a part of the circuit board at a position facing the active surface of the integrated circuit element is smaller than the outer diameter of the integrated circuit element. 1. A resin-sealed structure for a circuit block, characterized in that a molding hole is formed, a circuit conductor pattern is formed on the molding hole, and the circuit block is sealed with a resin.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57228953A JPS59120884A (en) | 1982-12-27 | 1982-12-27 | Resin sealing construction of circuit block for wrist watch |
| CH694183A CH660551GA3 (en) | 1982-12-27 | 1983-12-27 | |
| US06/891,084 US4644445A (en) | 1982-12-27 | 1986-07-31 | Resin mounting structure for an integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57228953A JPS59120884A (en) | 1982-12-27 | 1982-12-27 | Resin sealing construction of circuit block for wrist watch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59120884A JPS59120884A (en) | 1984-07-12 |
| JPS6354222B2 true JPS6354222B2 (en) | 1988-10-27 |
Family
ID=16884439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57228953A Granted JPS59120884A (en) | 1982-12-27 | 1982-12-27 | Resin sealing construction of circuit block for wrist watch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59120884A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62184494U (en) * | 1986-05-15 | 1987-11-24 | ||
| JPH0749433Y2 (en) * | 1987-10-02 | 1995-11-13 | セイコーエプソン株式会社 | Electronic clock circuit block |
| US5438216A (en) * | 1992-08-31 | 1995-08-01 | Motorola, Inc. | Light erasable multichip module |
| JP3683996B2 (en) * | 1996-07-30 | 2005-08-17 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
-
1982
- 1982-12-27 JP JP57228953A patent/JPS59120884A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59120884A (en) | 1984-07-12 |
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