CH660551GA3 - - Google Patents

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Publication number
CH660551GA3
CH660551GA3 CH694183A CH694183A CH660551GA3 CH 660551G A3 CH660551G A3 CH 660551GA3 CH 694183 A CH694183 A CH 694183A CH 694183 A CH694183 A CH 694183A CH 660551G A3 CH660551G A3 CH 660551GA3
Authority
CH
Switzerland
Prior art keywords
integrated circuit
circuit
substrate
chip
hole
Prior art date
Application number
CH694183A
Other languages
French (fr)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57228953A external-priority patent/JPS59120884A/en
Priority claimed from JP58179845A external-priority patent/JPS6071980A/en
Application filed filed Critical
Publication of CH660551GA3 publication Critical patent/CH660551GA3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

This invention describes an improved resin mounting structure for use with an integrated circuit. An integrated circuit chip is affixed to a circuit substrate which has a hole. Circuit patterns connect to the contact pads of the integrated circuit chip and are added along the circuit substrate. An epoxy resin material is gated through the hole to surround and enclose the integrated circuit chip. In this invention, circuit patterns which are added beneath the integrated circuit chip are positioned over the hole in the substrate to allow an unimpeded flow of resin material. In addition, conductive spacing pegs are provided at each integrated circuit contact pad to allow for a uniform spacing between the integrated circuit and the circuit substrate and to provide for a more electrically and mechanically secure connection between the IC chip and the circuit substrate. Also, the circuit substrate is formed from a flexible material to absorb the displacement caused by differential thermal expansion.
CH694183A 1982-12-27 1983-12-27 CH660551GA3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57228953A JPS59120884A (en) 1982-12-27 1982-12-27 Resin-sealed structure of circuit block
JP58179845A JPS6071980A (en) 1983-09-28 1983-09-28 Circuit mounting structure

Publications (1)

Publication Number Publication Date
CH660551GA3 true CH660551GA3 (en) 1987-05-15

Family

ID=26499576

Family Applications (1)

Application Number Title Priority Date Filing Date
CH694183A CH660551GA3 (en) 1982-12-27 1983-12-27

Country Status (2)

Country Link
US (1) US4644445A (en)
CH (1) CH660551GA3 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999699A (en) * 1990-03-14 1991-03-12 International Business Machines Corporation Solder interconnection structure and process for making
US5220726A (en) * 1991-06-26 1993-06-22 Xerox Corporation Method for manufacturing an electrically connectable module
EP0546285B1 (en) * 1991-12-11 1997-06-11 International Business Machines Corporation Electronic package assembly with protective encapsulant material
US5469333A (en) * 1993-05-05 1995-11-21 International Business Machines Corporation Electronic package assembly with protective encapsulant material on opposing sides not having conductive leads
EP0602298B1 (en) * 1992-12-15 1998-06-10 STMicroelectronics S.r.l. Support for a semiconductor package
US5386624A (en) * 1993-07-06 1995-02-07 Motorola, Inc. Method for underencapsulating components on circuit supporting substrates
JP3186925B2 (en) * 1994-08-04 2001-07-11 シャープ株式会社 Panel mounting structure, integrated circuit mounting tape and method of manufacturing the same
DE19810060B4 (en) * 1997-05-07 2005-10-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. A method of connecting a device to a substrate and an electrical circuit made therewith
DE19729073A1 (en) * 1997-07-08 1999-01-14 Bosch Gmbh Robert Method for producing an adhesive connection between an electronic component and a carrier substrate
US6324069B1 (en) 1997-10-29 2001-11-27 Hestia Technologies, Inc. Chip package with molded underfill
US6495083B2 (en) 1997-10-29 2002-12-17 Hestia Technologies, Inc. Method of underfilling an integrated circuit chip
EP1014776B1 (en) * 1998-12-24 2003-09-10 Nokia Corporation Method for mechanicaly fixing components on a board and device for applying this method
DE19954888C2 (en) * 1999-11-15 2002-01-10 Infineon Technologies Ag Packaging for a semiconductor chip
DE10016135A1 (en) * 2000-03-31 2001-10-18 Infineon Technologies Ag Housing assembly for an electronic component
DE102005054985A1 (en) * 2005-11-16 2007-05-24 Marker Völkl International GmbH Snow gliding board and shell component for a snow sliding board
DE102017204842A1 (en) 2017-03-22 2018-09-27 Robert Bosch Gmbh Contact configuration
CN109152211B (en) * 2018-08-22 2020-04-28 惠州市华星光电技术有限公司 Flip-chip light emitting diode packaging module and manufacturing method thereof
KR20230023834A (en) * 2020-12-09 2023-02-20 주식회사 솔루엠 Air-Pocket Prevention PCB, Air-Pocket Prevention PCB Module and Electrical Device having the Same and Manufacturing Method of the Electrical Device having the Same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4048438A (en) * 1974-10-23 1977-09-13 Amp Incorporated Conductor patterned substrate providing stress release during direct attachment of integrated circuit chips
US4065850A (en) * 1975-08-13 1978-01-03 Kollmorgen Technologies Corporation Method of making multi-wire electrical interconnecting member having a multi-wire matrix of insulated wires mechanically terminated thereon
US4143456A (en) * 1976-06-28 1979-03-13 Citizen Watch Commpany Ltd. Semiconductor device insulation method
DE3029667A1 (en) * 1980-08-05 1982-03-11 GAO Gesellschaft für Automation und Organisation mbH, 8000 München CARRIER ELEMENT FOR AN IC COMPONENT
US4396936A (en) * 1980-12-29 1983-08-02 Honeywell Information Systems, Inc. Integrated circuit chip package with improved cooling means
GB2097998B (en) * 1981-05-06 1985-05-30 Standard Telephones Cables Ltd Mounting of integrated circuits
JPS5850572A (en) * 1981-09-22 1983-03-25 株式会社東芝 Manufacture of display
US4435740A (en) * 1981-10-30 1984-03-06 International Business Machines Corporation Electric circuit packaging member
US4573105A (en) * 1983-02-16 1986-02-25 Rca Corporation Printed circuit board assembly and method for the manufacture thereof

Also Published As

Publication number Publication date
US4644445A (en) 1987-02-17

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PL Patent ceased