JPH01281762A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the required number of internal connection terminals and miniaturize a semiconductor device by mounting two diode chips on a common internal connection terminal, while making the vertical relations to the anode and cathode in respective diode chips have the opposite directions each other with respect to a pair of the diode chips which are adjacent each other in the same direction and in a sequential connection. CONSTITUTION:Out of three speed-up diode chips D1-D3 which are used for increasing a response rate, a diode chip D1 connects its cathode side to an electrode terminal for signals 4 and a diode chip D2 connects its anode side to an internal connection terminal 5 and then, a diode chip D3 connects its cathode side onto the internal connection terminal 5. In other words, the internal connection terminal 5 is used in common for a connection terminal in two diode chips D2 and D3 and then, the vertical relations to the anode and cathode in respective a pair of diode chips D2 and D3 have the opposite directions each other. Thus, the diode chips D2 and D3 have reverse characteristics each other in the state of these configurations. In this way, it is enough for this device to have only one internal connection terminal 5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor chip including a multi-stage Darlington transistor, and a structure in which the bases of the semiconductor chip are connected in the same direction and in order to increase the response speed of the multi-stage Darlington transistor. The present invention relates to a semiconductor device including speed-up diode chips connected in sequence.

[Conventional technology]

FIG. 3 is a plan view showing the internal wiring structure of a power transistor module, which is one of the conventional examples of this type of semiconductor device, and FIG. 4 is a circuit showing an equivalent circuit of the power transistor module. It is a diagram. In Figure 3,
The insulating substrate 1 is bonded to a heat dissipation base plate (not shown), and on the insulating substrate 1 are a semiconductor chip 2, a main current electrode terminal 3 and a signal electrode terminal 4 extending toward the outside of the module. and internal connection terminals 5 and 6, which are limited within the module, are joined. Although the detailed internal structure of the semiconductor chip 2 is not shown, this semiconductor chip 2 allows the four transistors Q1 . Q2. Q
3. A four-stage Darlington transistor consisting of Q4 is formed.

It is also connected between the bases of adjacent transistors,
Three speed-up diode chips used to increase the response speed of a four-stage Darlington transistor [)1.02. D3 connects each cathode side to a signal electrode terminal 4. They are connected to internal connection terminals 5a and 5b by soldering, respectively.

On the semiconductor chip 2 are bases B1 . Four pad areas b1.corresponding to B2.83.84. b2. b3. b4 is formed, the pad region b1 is connected to the signal electrode terminal 4 by the internal lead wire 7a made of aluminum wire, and the pad region b2 is connected to the anode side of the speed-up diode D1 by the internal lead wire 7b.
The pad region b3 is connected to the anode side of the speed-up diode D2 by the internal lead wire 7c.
are connected to the anode side of the speed-up diode D3 by the internal lead wire 7d, and the anode of the speed-up diode D1 is connected to the internal lead wire 7.
The anode of the speed-up diode D2 is connected to the internal lead 5 by e, and the anode of the speed-up diode D2 is connected to the internal lead [16 by internal lead 7f. Further, a portion 8 on the semiconductor chip 2 corresponds to the emitter E of the transistor Q4 in FIG. 4, and a pad region e formed in this portion 8 is connected to the main current electrode terminal 3 by an internal lead wire 7g. ing. Each transistor Q1~ in FIG.
A part of the semiconductor chip 2 corresponding to the collector C of Q4 is also
It is electrically connected to another main current electrode terminal (not shown).

Each of the above-mentioned members provided on the heat dissipation base plate is entirely surrounded by a resin case (not shown) provided separately on the heat dissipation base plate, and is sealed by injecting and solidifying epoxy resin into the resin case. Considered to be a transistor module.

In the internal wiring structure of the power transistor module described above, the pad region b4 is connected to the anode of the speed-up diode D3 via the internal lead wire 7d, and the cathode of the diode D3 is connected to the internal wiring terminal 6.
Internal lead wire 7f.

7C to pad region b3, transistor Q4.7C is connected to pad region b3 as shown in FIG. Q3 base 84. B
This means that the speed-up diode D is inserted at 3fll. Further, the pad region b3 is connected to the anode of the speed-up diode D2 via the internal lead wire 7C, and the cathode of the diode D2 is connected to the internal connection terminal 5. Since it is connected to the pad region b2 via the internal lead wires 7e and 7b, the transistor Q3
This means that the speed-up diode D2 is inserted between the bases 83 and 82 of Q2. Furthermore, pad area b
2 is connected to the anode of the speed-up diode D1 via the internal lead wire 7b, and the cathode of the diode D1 is connected to the signal electrode terminal 4 and the pad area b1 via the internal lead wire 7a. As shown in the figure, transistor Q2. This means that the speed-up diode D1 is inserted between the bases 82 and 81 of Ql.

On the other hand, the cathode of the speed-up diode D3 is connected to the internal connection terminal 6. It is connected to the anode of the speed-up diode D2 via the internal lead wire 7f, and the cathode of the diode D2 is connected to the internal connection terminal 5. Internal lead wire 7
Since it is connected to the anode of the speed-up diode D1 through E, the three speed-up diodes D1 to D3 are also connected in series in the same direction as shown in FIG.

Therefore, in the four-stage Darlington transistor shown in FIG. 4, when each of the transistors 01 to Q4 is turned off, the charge accumulated in the base B4 of the transistor Q4 flows up through the speed-up diode D3 as follows: The charge stored in the base B3 of the transistor Q3 flows through the speed-up diode D2 to a current of 12
, the charge accumulated on the base B2 of transistor Q2 flows through the speed-up diode D1 to a current 11
The signals are respectively handled as signal electrode terminals 4, and the response speed is increased.

[Problem to be solved by the invention]

However, in the semiconductor device having the above configuration, in order to connect the three speed-up diodes D1 to D3 to the four-stage Darlington transistor, two internal connection terminals 5 and 6 are required in addition to the signal electrode terminal 4. There was a problem in that the H position became large.

This invention was made in order to solve these problems, and it is a semiconductor that can miniaturize the device by reducing the number of internal connection terminals for connecting speed-up diodes to multi-stage Darlington transistors. The purpose is to obtain equipment.

[Means to solve the problem]

A semiconductor device according to the present invention includes a semiconductor chip including a multi-stage Darlington transistor having three or more stages, and a plurality of diodes sequentially connected in the same direction between base electrodes of each of the multi-stage Darlington transistors. In the semiconductor device, among the plurality of diode chips, pairs of diode chips adjacent to each other in the sequential connection are provided on a common internal connection terminal with their anodes and cathodes in opposite directions. This provides an electrical connection between the pair of diode chips.

[Effect]

In the present invention, the required number of internal wiring terminals is reduced by interconnecting adjacent diode chips in the sequential connection through a common internal wiring unit.

(Embodiment) FIG. 1 is a plan view showing the internal wiring structure of a power transistor module which is an embodiment of the semiconductor device according to the present invention, and FIG. 2 shows an equivalent circuit of the power transistor module. It is a circuit diagram. In Figure 1,
1-5.7Q, 8°b1-b3. e is exactly the same as the conventional device, and the four-stage Darlington transistor formed on the semiconductor chip 2 is also exactly the same as the conventional device as shown in FIG.

In this module, three speed-up diode chips D1, D2, . Among the diode D3, the cathode side of the diode D1 is soldered to the signal electrode terminal 4, the anode side of the diode D2 is soldered to the internal connection terminal 5, and the cathode side of the diode D3 is soldered to the internal connection terminal 5. It is connected. That is, the internal connection terminal 5 has two diodes D2. This diode chip pair D2. The vertical relationship between the anode and cathode in each of D3 is opposite to each other.

In other words, diode chip D2. D3 have opposite characteristics to each other in their arrangement state. Therefore, one internal connection terminal 5 is sufficient.

Then, four transistors Q1. of the four-stage Darlington transistor. Q2. Q3. Q4 base 81.82.
83. Each pad region b1. on the semiconductor chip 2 corresponding to B4. b2. b3. Of b4, the pad region b1 is connected to the signal electrode terminal 4 by an internal lead wire 9a made of aluminum wire, and the pad region b2 is connected to the anode side of the speed-up diode D1 by an internal lead wire 9b.
The pad region b3 is connected to the internal connection terminal 5 by an internal lead wire 9C, and the pad region b4 is connected to the anode side of the speed-up diode D3 by an internal lead wire 9d. Further speed-up diode D
The anode of No. 1 is connected to the cathode of the speed-up diode D2 by an internal lead wire 9e. The rest of the configuration is the same as that of the conventional device, and the explanation thereof will be omitted here.

In the internal wiring structure of the power transistor module described above, the pad region b4 is connected to the anode of the speed-up diode D3 via the internal lead wire 9d, and the cathode of the diode D3 is connected to the internal wiring terminal 5.
Since it is connected to the pad region b3 via the internal lead wire 9C, as shown in FIG. Speed-up diode D3 between bases 84 and 83 of Q3
has been inserted. Further, the pad region b3 is connected to the anode of the speed-up diode D2 via the internal lead wire 9G and the internal connection terminal 5, and the cathode of the diode D2 is connected to the pad region b2 via the internal lead wires 9e and 9b. Therefore, as shown in FIG. 2, a speed-up diode D2 is inserted between the bases 83 and 82 of the transistor Q3°Q2. Further, the pad region b2 is connected to the anode of the speed-up diode D1 via the internal lead wire 9b, and the cathode of the diode D1 is connected to the signal electrode terminal 4. Since it is connected to the pad area b1 via the internal lead wire 9a, the second
As shown in the figure, transistor Q2. Base of Q1 B2.
This means that the speed-up diode D1 is inserted between 81 and 81.

On the other hand, the cathode of the speed-up diode D3 is connected to the speed-up diode D2 via the internal connection terminal 5.
Since the cathode of the diode D2 is connected to the anode of the speed-up diode D1 via the internal lead wire 9e, the three speed-up diodes D1 to D3 are connected to each other as shown in FIG. This also means that they are connected in the same direction and in series.

Therefore, in the four-stage Darlington transistor shown in FIG. 2, when each of the transistors 01 to Q4 turns off, the charge accumulated in the base B4 of the transistor Q4 flows through the diode D3 as a current i3, as in the case of the conventional device. , the charge accumulated in the base B3 of the transistor Q3 flows as a current 12 through the diode D2,
The charge accumulated in the base B2 of the transistor Q2 is drawn out as a current 11 to the signal electrode terminal 4 through the diode D1, thereby increasing the response speed. The charge accumulated in the base B1 of the transistor Q1 is the electric charge flowing through the internal lead wire 9a shown in FIG. io and is pulled out to the signal electrode terminal 4 side.

In other words, while maintaining the same operation as the conventional example shown in FIG. 3, the number of internal connection terminals has been reduced.

〔Effect of the invention〕

As described above, according to the present invention, for pairs of diode chips adjacent to each other in the same direction and sequential connection,
Since the anodes and cathodes are arranged in opposite directions and are provided on a common internal connection terminal, the number of internal connection terminals required is reduced, and the semiconductor device can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an internal wiring structure of an embodiment of a semiconductor device according to the present invention, FIG. 2 is a circuit diagram showing an equivalent circuit of the semiconductor device, and FIG. 3 is a plan view showing an internal wiring structure of a conventional semiconductor device. The plan view shown in FIG. 4 is a circuit diagram showing an equivalent circuit of the semiconductor device. In the figure, 2 is a semiconductor chip, 4 is a signal electrode terminal,
5 and 6 are internal connection terminals, 9a to 9e are internal lead wires, D
1 to D3 are speed-up diodes (diode chips), and 01 to Q4 are transistors at each stage of the four-stage Darlington transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 Figure 2

Claims (1)

[Claims] (1) A semiconductor device comprising a semiconductor chip including a multi-stage Darlington transistor having three or more stages, and a plurality of diodes sequentially connected in the same direction between the base electrodes of each of the multi-stage Darlington transistors, Among the plurality of diode chips, pairs of diode chips that are adjacent to each other in the sequential connection are provided on a common internal connection terminal with their anodes and cathodes in opposite directions. A semiconductor device characterized in that an electrical connection is made between the two.