JPH01281748A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH01281748A
JPH01281748A JP11074588A JP11074588A JPH01281748A JP H01281748 A JPH01281748 A JP H01281748A JP 11074588 A JP11074588 A JP 11074588A JP 11074588 A JP11074588 A JP 11074588A JP H01281748 A JPH01281748 A JP H01281748A
Authority
JP
Japan
Prior art keywords
layer
film
carbon
oxidization
ashing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11074588A
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Japanese (ja)
Inventor
Koichi Hashimoto
浩一 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11074588A priority Critical patent/JPH01281748A/en
Publication of JPH01281748A publication Critical patent/JPH01281748A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To shorten a birds beak by forming a nitride silicon film pattern by anisotropic dry etching using a gas involving carbon, and thereafter subjecting the pattern to ashing, cold oxidization, and impregnation into an aqueous hydrofluoric acid solution to remove a carbon contaminated layer on the exposed semiconductor substrate surface. CONSTITUTION:After a layer A (silicon nitride film) is removed by ashing, a layer B (carbon contaminated layer) is completely converted to SiO2 by cold oxidization. Carbon atoms involved in the layer B are substantially entirely incorporated into the SiO2 by the cold oxidization. Accordingly, the involved carbon atoms can be removed by impregnating the SiO2 in an aqueous HF solution and removing the same. Thereafter, there are produced no defect layer due to carbon contamination and no increase of junction leakage, by selective thermal oxidization. Hereby, and birds beak can be shortened without leaving behind any defect layer which increases such junction leakage.

Description

【発明の詳細な説明】 〔発明の概要〕 半導体装置の製造方法に関し、 接合リークを増加させる欠陥層を残すことなくバーズビ
ーク短縮をはかった、微細幅の素子分離構造の製造方法
を提供することを目的とし、半導体基板の表面の少なく
とも一部に直接接触させてシリコン窒化膜を成長させ、
それを所定のパターンに成形して、前記半導体基板のう
ち窒化膜に覆われない部分を選択的に酸化して生じる酸
化膜を素子分離のために用いる半導体装置の製造方法に
おいて、炭素を含むガスを用いる異方性のドライエツチ
ングで前記シリコン窒化膜のパターン形成を行った後に
、次の熱酸化工程の前に、アッシングと低温酸化とフッ
化水素酸水溶液への浸漬をこの順序で行なって、シリコ
ン窒化膜を除かれて露出した半導体基板表面の炭素汚染
層除去を行なうよう構成する。
[Detailed Description of the Invention] [Summary of the Invention] It is an object of the present invention to provide a method for manufacturing a device isolation structure with a fine width, in which a bird's beak is shortened without leaving a defective layer that increases junction leakage. to grow a silicon nitride film in direct contact with at least a portion of the surface of a semiconductor substrate,
In a method of manufacturing a semiconductor device in which the oxide film formed by forming the oxide film into a predetermined pattern and selectively oxidizing the portions of the semiconductor substrate that are not covered with the nitride film is used for element isolation, a gas containing carbon is used. After forming a pattern on the silicon nitride film by anisotropic dry etching using a method, ashing, low-temperature oxidation, and immersion in a hydrofluoric acid aqueous solution are performed in this order before the next thermal oxidation step. The structure is such that the carbon contamination layer on the surface of the semiconductor substrate exposed after the silicon nitride film is removed is removed.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に関し、特に微細幅の素
子間分離構造を形成する製造方法に関する。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a device isolation structure with a fine width.

近年、半導体集積回路の規模は急速に増大しており、集
積度の向上が強(望まれている。そのためトランジスタ
に代表される能動素子のみならず、素子分離領域の微細
化が是非とも必要となっている。従来から用いられてい
る素子分離法は、シリコンLSIの場合、シリコンの選
択酸化によって形成する二酸化シリコン(SiOz)を
用いる誘電体分離法である。しかしこの方法では、いわ
ゆるバーズビークが発生して分離領域の幅を小さくする
ことに限界があり、能動領域幅の減少、集積度低下の問
題がある。
In recent years, the scale of semiconductor integrated circuits has been rapidly increasing, and there is a strong desire to improve the degree of integration.Therefore, it is absolutely necessary to miniaturize not only active elements such as transistors, but also element isolation regions. In the case of silicon LSI, the conventional element isolation method used is a dielectric isolation method using silicon dioxide (SiOz), which is formed by selective oxidation of silicon.However, with this method, so-called bird's beak occurs. There is a limit to how small the width of the isolation region can be, resulting in problems such as a decrease in the width of the active region and a decrease in the degree of integration.

バーズビークの生じる原因は、耐酸化マスクである窒化
シリコン(SisN4)パターンとシリコン基板の間に
応力を緩和して結晶欠陥を抑える目的で挿入されるパッ
ド5iOz層がオキシダントのパスになって、Si3N
、パターンの下まで酸化領域がもぐり込むことによる。
The cause of the bird's beak is that the pad 5iOz layer, which is inserted between the silicon nitride (SisN4) pattern that is an oxidation-resistant mask and the silicon substrate to relieve stress and suppress crystal defects, becomes a path for oxidants.
, due to the oxidized region penetrating beneath the pattern.

そこで、選択酸化法を用いつつ集積度の向上をはかる、
すなわちバーズビークを短縮する方法として、パッド5
iOz層および該層上に形成された選択酸化のマスクと
なるSi3N4膜の側壁を、パッド酸化膜を介さず直接
シリコン基板上に形成した第2の5i3Nn膜で囲って
フィールド酸化を行う方法が知られている。この方法に
よると、パッドSiO□へのオキシダント侵入を妨げる
ことができ、バーズビークを短縮できる。本発明はか\
る微細幅素子分離を行なう場合の善後処置に係るもので
ある。
Therefore, we aim to improve the degree of integration while using selective oxidation.
In other words, as a method of shortening the bird's beak, pad 5
A method is known in which field oxidation is performed by surrounding the sidewalls of the iOz layer and the Si3N4 film formed on the layer, which serves as a mask for selective oxidation, with a second 5i3Nn film formed directly on the silicon substrate without using a pad oxide film. It is being According to this method, it is possible to prevent oxidant from entering the pad SiO□, and the bird's beak can be shortened. What about this invention?
This paper relates to follow-up measures when performing fine-width element isolation.

〔従来の技術〕[Conventional technology]

第3図(a)(b)に微細幅素子間分離方法の要部を示
す。lOはシリコン基板、11は該基板上に形成された
パッドSiO□膜、12は該膜11上に形成された5i
3Ni膜、13はこれらの膜11.12の側壁を囲む第
2のS i 3 N a膜である。このような膜11.
12の側壁を囲む(目的はSiO□1ullの側壁部を
塞ぐ)SisNn膜13があると、熱酸化して露出面1
0aにフィールド酸化膜(素子間分離膜)を形成する時
に、Si3N4膜13がない場合のように5iOzll
llの側壁からのオキシダントの侵入(矢印で示す)が
ないから、フィールド酸化膜は点線のようになって、バ
ーズビークの発生が殆んどない。
FIGS. 3(a) and 3(b) show the main parts of the fine width element isolation method. 1O is a silicon substrate, 11 is a pad SiO□ film formed on the substrate, and 12 is a pad 5i formed on the film 11.
3Ni film, 13 is a second S i 3 Na film surrounding the sidewalls of these films 11 and 12. Such a membrane 11.
If there is a SisNn film 13 that surrounds the sidewalls of 12 (the purpose is to close the sidewalls of SiO□1ull), it will thermally oxidize and
When forming a field oxide film (element isolation film) on 0a, 5iOzll as in the case where there is no Si3N4 film 13.
Since there is no intrusion of oxidant (indicated by the arrow) from the sidewall of 1, the field oxide film looks like the dotted line and almost no bird's beak occurs.

第3図(a)の窒化膜13は、同図(e)(f)(g)
の工程で作ることができる。即ち、シリコン基板10上
に例えば熱酸化でSiO□膜11膜形1し、次いで例え
ばCVD法によりS i :+ N a膜12を成長さ
せ、次にレジストを塗布し、露光、現像してパターニン
グしたレジスト14を作り、これをマスクにSi3N4
膜12を、更にSiO2膜11をエツチングして(e)
の状態にする。次は(f)に示すようにレジスト14を
除いたのち第2の5i2N、膜15を成長させ、次いで
異方性エツチングを行なって5iiN4膜15を点線と
矢印で示すように減厚していく。やがては(局の如く、
膜11.12の側壁部にのみS i x N 4膜が残
り、こうして(g)つまり(a)の状態が得られる。
The nitride film 13 in FIG. 3(a) is shown in FIG. 3(e), (f), and (g).
It can be made using the process of That is, a SiO□ film 11 is formed on a silicon substrate 10 by, for example, thermal oxidation, and then a Si:+Na film 12 is grown by, for example, CVD, and then a resist is applied, exposed, developed, and patterned. Create a resist 14 with a 100% polyurethane, and use this as a mask to apply Si3N4.
Etching the film 12 and further the SiO2 film 11 (e)
state. Next, as shown in (f), after removing the resist 14, a second 5i2N film 15 is grown, and then anisotropic etching is performed to reduce the thickness of the 5iiN4 film 15 as shown by dotted lines and arrows. . Eventually (like a station,
The S i x N 4 film remains only on the side walls of the film 11.12, thus obtaining the state (g) or (a).

第2のSi3N、膜15は、一部は第1のS i 3 
N m膜12上にあるが、残部は基板10の露出面10
a上にある。従って露出面10a上の5i3Nn膜をエ
ツチングで除去する際、異方性エツチング(RlE:リ
アクティブイオンエツチング)のガスが直接露出面10
aに触れ、これを荒らす恐れがある。
The second Si3N film 15 is partially composed of the first Si3N film 15.
Nm is on the film 12, but the rest is on the exposed surface 10 of the substrate 10.
It's on a. Therefore, when removing the 5i3Nn film on the exposed surface 10a by etching, the anisotropic etching (RlE: reactive ion etching) gas is directly etched on the exposed surface 10a.
There is a risk of touching a and damaging it.

そこで第2の窒化11215の異方性エツチングはCF
4+H,またはCHF3 +CFaなどの炭素を含むガ
スを用いて行なわれる。
Therefore, the anisotropic etching of the second nitride 11215 is performed using CF
This is carried out using a carbon-containing gas such as 4+H or CHF3+CFa.

ところが、このようなエツチング条件でマクロな荒れは
生じなくしても、シリコン基板には、G。
However, even if macroscopic roughness does not occur under these etching conditions, G.

S、 0ehrleinがProc、 Symposi
um on Dry Processρp59.198
6で述べているように、第3図(C)に示すようなダメ
ージ層を生じる。AはC:Fポリマー層、Bはアモルフ
ァスSi :C層、Cは“H゛ダメージ層Dは完全結晶
層で、D以外は変質している。
S, 0ehrlein is Proc, Symposi
um on Dry Process p59.198
6, a damaged layer as shown in FIG. 3(C) is produced. A is a C:F polymer layer, B is an amorphous Si:C layer, and C is a "H" damaged layer. D is a completely crystalline layer, and the layers other than D are altered.

これらA−C層のうち、A層はエツチングガスから生じ
るフッ素を含む有機物ポリマーで、エツチング後にフォ
トレジストを除去するために行うアッシング処理により
除去できるが、エツチングプラズマ中で生じる炭素イオ
ンが打ち込まれたB層、水素イオンが打ち込まれたC層
はそのまま残留する。従って、従来の方法でフィールド
酸化以降の工程を行ってデバイスを形成すると、同図(
d)に示すように、フィールドSiO□ 16の下部に
B層による欠陥層(×印で示す)が残り、PN接合の逆
方向リーク電流が著しく増加してしまうという問題を生
じる。
Of these A-C layers, the A layer is an organic polymer containing fluorine generated from the etching gas, and can be removed by an ashing process performed to remove the photoresist after etching, but carbon ions generated in the etching plasma are implanted. The B layer and the C layer into which hydrogen ions have been implanted remain as they are. Therefore, if a device is formed by performing the steps after field oxidation using the conventional method, the same figure (
As shown in d), a defective layer (indicated by an x mark) due to the B layer remains under the field SiO□ 16, resulting in a problem that the reverse leakage current of the PN junction increases significantly.

(発明が解決しようとする課題〕 シリコン基板に直接接触するシリコン窒化膜に対し、炭
素を含むガスを用いる異方性エツチングを行なうと、基
板表面にマクロな荒れは生じなくても炭素イオンが打込
まれた層Bが生じ、その後の例えば600°C以上の高
温度での熱処理で該B層の炭素による欠陥が発生する。
(Problem to be solved by the invention) When performing anisotropic etching using a gas containing carbon on a silicon nitride film that is in direct contact with a silicon substrate, carbon ions are bombarded even though no macroscopic roughness occurs on the substrate surface. A layer B is formed, and defects due to carbon in the layer B are generated by subsequent heat treatment at a high temperature of, for example, 600° C. or higher.

本発明はこの点を改善し、接合リークを増加させる欠陥
層を残すことなくバーズビーク短縮をはかった、微細幅
の素子分離構造の製造方法を提供することを目的とする
An object of the present invention is to improve this point and provide a method for manufacturing a device isolation structure with a fine width, in which the bird's beak can be shortened without leaving a defective layer that increases junction leakage.

(課題を解決するための手段〕 第1図に本発明の製造方法の要部を示す。図示のように
本発明では、従来同様の異方性エツチングによるSi3
N、膜のエツチングを行った■後、次の熱酸化工程■に
進む前に、アッシング■と低温酸化■とHF水溶液漫漬
■をこの順序で行う。
(Means for Solving the Problems) Fig. 1 shows the main parts of the manufacturing method of the present invention.As shown in the figure, in the present invention, Si3
N. After etching the film (2), before proceeding to the next thermal oxidation step (2), ashing (2), low-temperature oxidation (2), and dipping in an HF aqueous solution (2) are performed in this order.

ここで言う低温酸化とは、B層の汚染物質である炭素(
C)がシリコン(Si)中をほとんど拡散しない、室温
ないし300°C程度の温度で行う酸化である。低温酸
化は、酸化性の溶液にシリコン基板を浸漬することによ
り行なうことができる。また前記アッシングと低温酸化
は、酸素プラズマにシリコン基板を所定時間晒すことに
より引続いて行なうことができる。
The low-temperature oxidation referred to here refers to carbon (
This is an oxidation process in which C) hardly diffuses in silicon (Si) at temperatures ranging from room temperature to about 300°C. Low-temperature oxidation can be performed by immersing the silicon substrate in an oxidizing solution. Further, the ashing and low-temperature oxidation can be performed successively by exposing the silicon substrate to oxygen plasma for a predetermined period of time.

〔作用〕[Effect]

本発明の方法によると、次のようにして前記問題を解決
できる。
According to the method of the present invention, the above problem can be solved as follows.

まず、A層をアッシングによって除去した後、低温酸化
によってB層の全体を5iOzに変換してしまう。この
低温酸化で、8層中にあった炭素はほぼすべてSiO□
中に取り込まれる。そこで、HF水溶液に浸漬してこの
SiO□層を除去することにより炭素も取り除くことが
できる。こうしておいてから選択熱酸化を行えば、炭素
汚染による欠陥層は生じず、接合リークが増加すること
はない。
First, after removing layer A by ashing, the entire layer B is converted to 5 iOz by low-temperature oxidation. Through this low-temperature oxidation, almost all the carbon in the 8 layers was converted into SiO□
taken inside. Therefore, by removing this SiO□ layer by immersing it in an HF aqueous solution, carbon can also be removed. If selective thermal oxidation is performed after this, a defective layer due to carbon contamination will not be generated and junction leakage will not increase.

このとき低温酸化でなく高温の熱酸化によってB層をS
iO□に変換すると、炭素は移動してC2D層へも入り
B層のSiO□中にすべては取り込まれないため、か−
るB層を酸化して除去してから、選択酸化を行っても接
合リークは残る。
At this time, the B layer is converted to S by high temperature thermal oxidation instead of low temperature oxidation.
When converted into iO
Even if selective oxidation is performed after the B layer is oxidized and removed, junction leakage remains.

また、0層までもSingに変換するほど厚く低温酸化
しなくても、接合リークは十分抑えられることを、実験
によって確認した。このことは、炭素汚染が接合リーク
につながる欠陥層形成に作用していて、水素は最終的に
は影響ないことを示すものである。
Furthermore, it was confirmed through experiments that junction leakage can be sufficiently suppressed even if the 0 layer is not oxidized at a low temperature so thick as to convert it to Sing. This indicates that carbon contamination plays a role in the formation of defective layers that lead to junction leakage, and that hydrogen ultimately has no effect.

〔実施例〕〔Example〕

上述のように、異方性エツチング時のシリコン基板への
炭素汚染が問題の主要因であるので、第2のSi3N、
膜13を用いず、第1のSi、N、膜12を異方性エツ
チングしてシリコン基板を露出させる場合にも、同様に
本発明を適用して同様な効果を得ることができる。
As mentioned above, carbon contamination of the silicon substrate during anisotropic etching is the main cause of the problem, so the second Si3N,
Even in the case where the first Si, N, film 12 is anisotropically etched to expose the silicon substrate without using the film 13, the present invention can be similarly applied to obtain the same effect.

そこで第1のSi3N、膜12のみを用いる場合につい
て、本発明の一実施例を説明する。第2図(a)に示す
ように(100) p型10Ωcmのシリコン基板10
を50人熱酸化して酸化膜11を作り、この上にCVD
法によりSi3N4を500人成長して窒化膜12を作
り、その上に所定の素子分離パターンのフォトレジスト
層14を形成する。次に、CHF3 +CF4  (1
: 1)ガスを用いる平行平板型プラズマエツチング装
置で、0.4 Torr+ IOW/cm2の条件で、
Si3N、膜12、SiO□膜11膜用1続いてエツチ
ングし除去した後、チャンネルストップ用のB゛イオン
基板露出部10aに打ち込む。
Therefore, an embodiment of the present invention will be described for a case where only the first Si3N film 12 is used. As shown in FIG. 2(a), a (100) p-type 10Ωcm silicon substrate 10
was thermally oxidized by 50 people to form an oxide film 11, and then CVD was applied on top of this.
A nitride film 12 is formed by growing 500 layers of Si3N4 by the method, and a photoresist layer 14 having a predetermined element isolation pattern is formed thereon. Next, CHF3 +CF4 (1
: 1) Parallel plate type plasma etching equipment using gas, under the conditions of 0.4 Torr + IOW/cm2,
After removing Si3N, film 12, and SiO□ film 11 by etching, B ions for channel stop are implanted into the exposed portion 10a of the substrate.

続いてアッシング処理によってフォトレジスト層14と
露出部10aのA層を除去した後、硫酸−+過酸化水素
水(100:2) 110°Cに10分間浸漬すること
により低温酸化を行い、水洗後、HF水溶液(5%)に
20秒浸漬して露出部10aのB層を除去する。その後
水洗、乾燥した後、露出部10aをフィールド酸化し、
以降通常の工程で所定のデバイスを形成した。第2図(
b)はこの状態を示し、16はフィールド酸化膜、17
は表面絶縁用のPSG膜、18は拡散層19に取付けた
電極、20はチャンネルストップ、そして21は導体層
である。19と21は例えばMOS PETのソースド
レインとゲート電極を構成する。
Subsequently, after removing the photoresist layer 14 and the A layer of the exposed portion 10a by ashing treatment, low-temperature oxidation was performed by immersing in sulfuric acid + hydrogen peroxide solution (100:2) at 110°C for 10 minutes, and after washing with water. , the exposed portion 10a of the B layer is removed by immersion in an HF aqueous solution (5%) for 20 seconds. After washing with water and drying, the exposed portion 10a is field oxidized,
Thereafter, a predetermined device was formed using normal steps. Figure 2 (
b) shows this state, 16 is the field oxide film, 17
18 is a PSG film for surface insulation, 18 is an electrode attached to the diffusion layer 19, 20 is a channel stop, and 21 is a conductor layer. 19 and 21 constitute, for example, a source drain and a gate electrode of a MOS PET.

上述の工程中、HF水溶液への浸漬を行ったものと行わ
なかったものについて、得られたデバイスのPN接合の
逆方向飽和電流を測定した結果を第2図(C)に示す。
FIG. 2(C) shows the results of measuring the reverse saturation current of the PN junction of the obtained devices with and without immersion in the HF aqueous solution during the above process.

HF処理したものはしないものに比べてリーク電流が約
1桁減少し、本発明によって、欠陥層が除去されること
が示された。
The leakage current was reduced by about one order of magnitude in the HF-treated sample compared to the non-HF-treated sample, indicating that the present invention removes defective layers.

この例では硫酸と過酸化水素水の混液で低温酸化したが
、エツチング条件によってはB層が厚くなりこの方法で
は酸化量が不足することがある。
In this example, low-temperature oxidation was performed using a mixture of sulfuric acid and hydrogen peroxide, but depending on the etching conditions, the B layer may become thick and the amount of oxidation may be insufficient with this method.

この場合は硝酸ボイルを追加すると良い結果が得られる
In this case, good results can be obtained by adding boiled nitric acid.

また、適当な条件で生成した酸素プラズマにさらすこと
によっても、低温で十分な量の酸化を行うことができた
。従って、酸素プラズマにさらすことによってアッシン
グに引き続いて低温酸化しても良好な結果が得られる。
Furthermore, by exposing the material to oxygen plasma generated under appropriate conditions, a sufficient amount of oxidation could be achieved at low temperatures. Therefore, good results can be obtained by ashing followed by low temperature oxidation by exposure to oxygen plasma.

第3図(f)の窒化膜15に対する異方性エツチングで
基板露出部にB層が発生するからこれを前記方法で除去
し、フィールド酸化後、今度は窒化膜12.15を除去
する必要が生じ、これも炭素を含むガスを用いたドライ
エツチングで除くならB層発生の問題がある。これに対
しても同様に、アッシング、低温酸化、フッ酸によるエ
ツチングを行なえばよい。
Since a B layer is generated in the exposed portion of the substrate by the anisotropic etching of the nitride film 15 in FIG. 3(f), it is necessary to remove this by the method described above, and then remove the nitride film 12.15 after field oxidation. If this is removed by dry etching using a carbon-containing gas, there is a problem of the formation of a B layer. For this purpose, ashing, low-temperature oxidation, and etching with hydrofluoric acid may be performed in the same manner.

〔発明の効果] 以上のように本発明によれば、バーズビークの短い、微
細幅の素子分離領域を、PN接合のリークを増大させる
ことなく形成することが可能となる。従って、本発明の
製造方法を用いれば、性能を劣化させることなく半導体
装置の集積度を向上させることができる。
[Effects of the Invention] As described above, according to the present invention, an element isolation region with a short bird's beak and a fine width can be formed without increasing leakage of the PN junction. Therefore, by using the manufacturing method of the present invention, it is possible to improve the degree of integration of a semiconductor device without deteriorating its performance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の製造方法の説明図、 第2図は本発明の詳細な説明する図、 第3図は従来方法の説明図である。 第2図、第3図で10は半導体基板、15はシリコン窒
化膜、16はフィールド酸化膜、Bはアモルファス5i
sC層である。
FIG. 1 is an explanatory diagram of the manufacturing method of the present invention, FIG. 2 is an explanatory diagram of the present invention in detail, and FIG. 3 is an explanatory diagram of the conventional method. In FIGS. 2 and 3, 10 is a semiconductor substrate, 15 is a silicon nitride film, 16 is a field oxide film, and B is an amorphous 5i
This is the sC layer.

Claims (1)

【特許請求の範囲】 1、半導体基板(10)の表面の少なくとも一部に直接
接触させてシリコン窒化膜(15)を成長させ、それを
所定のパターンに成形して、前記半導体基板のうち窒化
膜に覆われない部分(10a)を選択的に酸化して生じ
る酸化膜(16)を素子分離のために用いる半導体装置
の製造方法において、 炭素を含むガスを用いる異方性のドライエッチングで前
記シリコン窒化膜(15)のパターン形成を行った後に
、次の熱酸化工程の前に、アッシングと低温酸化とフッ
化水素酸水溶液への浸漬をこの順序で行なって、シリコ
ン窒化膜を除かれて露出した半導体基板表面(10a)
の炭素汚染層(B)除去を行なうことを特徴とする半導
体装置の製造方法。
[Claims] 1. A silicon nitride film (15) is grown in direct contact with at least a portion of the surface of the semiconductor substrate (10), and formed into a predetermined pattern to form a silicon nitride film (15) in direct contact with at least a portion of the surface of the semiconductor substrate (10). In a method of manufacturing a semiconductor device in which an oxide film (16) produced by selectively oxidizing a portion (10a) not covered by the film is used for element isolation, After patterning the silicon nitride film (15), ashing, low-temperature oxidation, and immersion in a hydrofluoric acid aqueous solution are performed in this order to remove the silicon nitride film before the next thermal oxidation step. Exposed semiconductor substrate surface (10a)
1. A method for manufacturing a semiconductor device, comprising removing a carbon contamination layer (B).
JP11074588A 1988-05-07 1988-05-07 Manufacture of semiconductor device Pending JPH01281748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11074588A JPH01281748A (en) 1988-05-07 1988-05-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11074588A JPH01281748A (en) 1988-05-07 1988-05-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01281748A true JPH01281748A (en) 1989-11-13

Family

ID=14543465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11074588A Pending JPH01281748A (en) 1988-05-07 1988-05-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01281748A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5651578A (en) * 1979-10-01 1981-05-09 Toshiba Corp Plasma etching method
JPS5651579A (en) * 1979-10-01 1981-05-09 Toshiba Corp Plasma etching method
JPS5687325A (en) * 1979-12-19 1981-07-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS62262441A (en) * 1986-05-09 1987-11-14 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5651578A (en) * 1979-10-01 1981-05-09 Toshiba Corp Plasma etching method
JPS5651579A (en) * 1979-10-01 1981-05-09 Toshiba Corp Plasma etching method
JPS5687325A (en) * 1979-12-19 1981-07-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS62262441A (en) * 1986-05-09 1987-11-14 Fujitsu Ltd Manufacture of semiconductor device

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