JPH01274195A - Crt display device - Google Patents

Abstract

PURPOSE:To reduce partial CRT screen burning by providing a timing adjusting circuit which varies the line display timing of a display part and a flip-flop circuit which controls whether the circuit is effective or ineffective between a vertical synchronizing signal generating circuit and a CRT display part. CONSTITUTION:The vertical synchronizing signal generated by a vertical synchronizing signal generating circuit 9 is inputted to the timing adjusting circuit 12 to determine whether or not the timing of the vertical synchronizing signal is adjusted by a flip-flop circuit 11 whose output value is inverted every time the power source is turned. When the timing is adjusted by the flip-flop circuit 11, the timing adjusting circuit 12 shifts the vertical synchronizing signal to n/m [where (n) and (m) are integer and (n)<(m)] times a display character line, i.e., a demultiple of one line, so the display line of CRT display 3 is shifted every time the power source is turned on. Consequently, display information is fixed and the same display part is made to illuminate, thereby reducing the screen burning at the display position.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a terminal of an information processing device or a CRT for monitoring.
Use as a display device. In particular, the present invention relates to a device for extending the life of a display screen of a CRT display device.

〔overview〕

The present invention is a CRT display device that can reduce partial CRT screen burn when the display position of characters such as letters is fixed by shifting the display line of the CRT each time the CRT display device is powered on. It is.

[Conventional technology]

Conventionally, CRT display devices used as terminals and display devices for information processing equipment, etc., have a rusk scan method or a bitmap method, but these methods are
Display information for one RT display screen is continuously prepared in the storage device, read out sequentially, and after reading the last display information, returns to the first memory address start address and displays the same readout again. The correspondence between the read address of the storage device and the display screen was fixed in a one-to-one correspondence.

[Problem that the invention seeks to solve]

In the conventional CRT display device described above, when the display information is fixed, for example, character display, the dot display position is the same display position determined by the character, so when used for a long time, the dot display position is fixed. CR at display position
T had the drawback of causing screen burn.

The present invention improves this and aims to provide a display device that can prevent burns from occurring at the same position.

[Means for solving problems]

The present invention provides a vertical synchronizing signal generation circuit for a CRT display device and a CRT display device.
A timing adjustment circuit is provided between the RT display unit and the timing adjustment circuit for changing the timing of this vertical synchronization signal to shift the display character line start position, and a flip-flop is provided for controlling the validity or invalidity of this timing adjustment circuit. It is characterized by This flip-flop circuit is inverted each time the power switch is opened or closed or by operation.

[Effect]

The vertical synchronization signal generated by the vertical synchronization signal generation circuit is manually input to the timing adjustment circuit. The timing adjustment circuit is
A flip-flop circuit whose output value is inverted each time the power is turned on determines whether or not to adjust the timing of the vertical synchronization signal. When performing timing adjustment using this flip-flop circuit, the timing adjustment circuit
The vertical synchronization signal is shifted by the timing adjustment circuit by n7m (n, m are integers, n<rn) of the display character rows, that is, by - lines or less, so the display rows on the CRT display can be shifted every time the power is turned on. can.

Therefore, screen burn at the display position, which occurs when the display information is fixed and only the same display portion is emitted, is reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a portion according to the invention of the configuration of a CRT display device according to an embodiment of the invention. This CRT display device includes a CR1 display section 8 and a storage device 7 for storing display contents given to the CR1 display section 8. This storage device 7 is used to read data and This is a configuration for writing. The read/write address to be given to the storage device 7 is given by the address selection circuit 6, and the write address 3 is given by the storage device write command signal 2. It is given from the display character line number counter 5.

The output of this display character line number counter 5 is the CR1 display section 8.
The vertical synchronizing signal generation circuit 9 that generates the vertical synchronizing signal 10 to be applied to A timing adjustment circuit 12 that provides a timing-adjusted vertical synchronization signal 13 to the CR1 display section 8
A flip-flop circuit 11 is provided to control whether the timing adjustment circuit 12 is enabled or disabled.

This flip-flop circuit 11 can be inverted each time the power is turned on, and its value can also be inverted by an operation by the operator of the CRT device.

Next, the operation of the apparatus according to the present invention will be explained.

A display character number counter 4 and a display character line number counter 5 are constantly counted and provide a refresh address to the storage device 7 via an address selection circuit 6. The output of the display character line number counter 5 is also given to a vertical synchronization signal generation circuit 9, and when the display character line number counter 5 starts counting again, a vertical synchronization signal 10 before timing adjustment is generated.

The address selection circuit 6 selects the address information 3 to be written into the storage device 7 from the outside and the address information from the display character number counter 4 and the display character line number counter 5 using the storage device write command signal 2, and writes the address information 3 to the storage device 7. Send the address information. For example, when the storage device write command signal 2 is “high”, the storage device 7 transfers the write information 1 from the outside to the address specified by the write address information 3 sent via the address selection circuit 6. When writing is "low", the storage device continuation information 14 at the address specified by the display character number counter 4 and the display character line number counter 5 is read out and sent to the CRT display section 8. After converting the information 14 into an analog signal, it is displayed as display information.

On the other hand, the flip-flop circuit 11 outputs "1" and "0" as output level values each time the CRT display device is powered on.
” are output alternately. The timing adjustment circuit 12 receives "1" which is alternately outputted from this flip-flop circuit 11.
, "0", the timing of the vertical synchronizing signal 10 from the vertical synchronizing signal generating circuit 9 is adjusted, and the vertical synchronizing signal 13 with the timing adjusted is supplied to the CRT display unit 8.

Next, the operation of this embodiment will be further explained with reference to FIG. 2 showing a flowchart after power is turned on to the CRT display device, and FIG. 3 showing a time chart corresponding to the output of the flip-flop circuit 11.

When the level value of the flip-flop circuit 11 is "1" when the power is turned on, the timing adjustment circuit 12 does not adjust the timing, so the vertical synchronization signal 10 and the vertical synchronization signal 1
3 is output at the same timing and the vertical synchronization signal 1
3, a signal shown as V Do in FIG. 3(a) is output. For this reason, a display character line number counter 5 is displayed on the display screen.
The contents of the storage device 7 when the count value is "1" are displayed on the first line, the displayed characters are sequentially counted, and the contents when the count value is N are displayed on the Nth line.

When the power is turned on next time, the level value of the flip-flop circuit 11 becomes "0", and at this time, the vertical synchronization signal is
The timing adjustment circuit 12 produces a signal whose timing is shifted by half a row, as shown by VD2 in FIG. 3(b). Therefore, on the display screen, the contents of the storage device 7 when the count value of the display character line number counter 5 is "0" are displayed on the 0.5th line, and the 1st line is displayed on the 1.5th line. , count value N
In this case, the character originally displayed on the Nth line is displayed on the (N-1)+0.5th line, and is displayed substantially half a line above.

Furthermore, when the power is turned on next time, the flip-flop circuit 11
Since the 0 level value is inverted to "1", the vertical synchronizing signal 13 shown in FIG. 7 is displayed on the first line.

Note that when the level value of the flip-flop circuit 11 is "0", instead of shifting the display line up by half a line as described above, it is also possible to shift the display line by half a numerator. That is, if the vertical synchronization signal 10 from the vertical synchronization signal generation circuit 9 is changed to the timing shown by VD2 in FIG. Storage device 7 when the count value is “2”
The contents are displayed on the 1.5th line. Whether the displayed character line is shifted upward by half a line or downward by half a line when the level of the flip-flop circuit 11 is "0" can be changed by setting the timing adjustment circuit.

The correspondence relationship between the display character number counter 4, the display character line number counter 5, and the storage device 7 for storing display screen information is explained in the fourth section.
As shown in the figure. FIG. 5(a) shows the correspondence between the storage device and the display screen when the level value of the flip-flop circuit 11 is "1", and when the level value of the flip-flop circuit 11 is "0", FIG. ) The correspondence relationship between the storage device and the display screen example is shown in FIG. 5(b), and the vertical synchronizing signal VD shown in FIG. 3(C) is output.
FIG. 5(C) shows the correspondence between the storage device and the display screen example when 2 is output.

In the above explanation, when the level of the flip-flop circuit 11 is "0", the count value of the display character line counter is shifted by half a line. Even if the character display position is shifted by 2/3 lines, the position of the character display changes each time the power is turned on, so that partial screen burn can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, in a CRT display device, a timing adjustment circuit for changing the line display timing of the display section is provided between the vertical synchronizing signal generation circuit and the CRT display section, and a timing adjustment circuit for changing the line display timing of the display section; By providing a flip-flop circuit to control the CRT screen, it is possible to shift the displayed character lines on the CRT screen, making it possible to reduce partial CRT screen burnout when the display position or display content is fixed. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a CRT display device according to an embodiment of the present invention. FIG. 2 is a flowchart showing the operation of the CRT display device after power is turned on. FIG. 3 is a time chart of vertical synchronization signals by the timing adjustment circuit of the embodiment. FIG. 4 is a diagram showing the correspondence relationship between the display character number counter, the display line number counter, and the storage device according to the embodiment. FIG. 5 is a diagram showing an example of a screen display corresponding to the output of the flip-flop of the embodiment. 1...Write information, 2...Storage device write command signal, 3
...Write address information, 4.Display character number counter, 5.Display character line number counter, 6.Address selection circuit, 7.Storage device, 8.CRT display unit, 9.
... Vertical synchronization signal generation circuit, 10.13 ... Vertical synchronization signal, 11 ... Flip-flop circuit, 12 ...
timing adjustment circuit.

Claims (1)

[Claims] (1) In a CRT display device comprising a CRT display section, a storage device for accumulating display contents given to the CRT display section, and a vertical synchronization signal generation circuit giving a vertical synchronization signal to the CRT display section, the vertical synchronization A timing adjustment circuit (12) for changing the timing of the vertical synchronization signal by n/m of character lines (n, m are integers, n<m) is provided between the signal generation circuit and the CRT display section. 1. A CRT display device comprising a flip-flop circuit (11) for controlling validity and invalidity of the timing adjustment circuit.