JPH01272230A - Semiconductor circuit device - Google Patents

Abstract

PURPOSE:TP increase the output operation speed of a semiconductor logic circuit by giving an intermediate potential, which exceeds a threshold voltage but does not reach a second power supply potential, to the gate of at least one transistor TR and extending the gate width of this TR. CONSTITUTION:The output of an intermediate potential generating circuit is inputted to the gate of at least one MOS TR 5 to keep the potential of this MOS TR 5 at an intermediate potential which does not reach the second power supply potential and is higher than the threshold voltage of the MOS TR 5. The gate width of a MOS TR 7 is so extended that a required current between the drain and the source is obtained. Consequently, a large current flows with the voltage between the drain and the source of the MOS TR 7 lower than conventional that. Thus, the operation of the logic circuit is quickly performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor circuit device including a logic circuit.

(Conventional technology).

As a conventionally used logic circuit, there is an inverter shown in FIG. 10, for example.

This inverter consists of a P-channel MOS transistor l whose source is connected to a positive power supply potential, whose gate is connected to a ground potential, and an output signal is output from the drain; It has an N-channel MO5 transistor 3 from which an output signal is output.

In this circuit, the P-channel Mos transistor 1 is normally on, but as semiconductor logic circuits have become faster, slow response has started to become a problem. In other words, in the voltage-current characteristics of MOS transistors, if the voltage between the drain and source of each MOS transistor is lower than a certain level, the current between the drain and source decreases rapidly, and the response of the output to the input is slow. It had become. In the input and output signal waveform diagram of this inverter circuit shown by dotted lines in FIG.
) to the 1st rubel (H), the waveform is slow.

(Problems to be Solved by the Invention) As described above, in conventional logic circuits, the response of output signals to input signals is slow, and in semiconductor devices that require high-speed operation, it is necessary to increase the operation speed of the logic circuit and the output operation. Inverter capable of speeding up N.

An object of the present invention is to provide a semiconductor device having logic circuits such as R and NAND.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor device according to the present invention connects an intermediate potential generation circuit to the gate of a MOS transistor in a logic circuit, and maintains a constant value even when the drain-source voltage is low. The gate width of the MOS transistor is set so that the above current flows between the drain and source, and an intermediate potential that exceeds the threshold voltage of this MOS transistor and does not reach the second power supply potential is input to the gate. do.

(Function) In the semiconductor device configured in this manner, the output of the intermediate potential generation circuit is input to the gate of at least one MOS transistor, and the potential of this MOS transistor is set to the second power supply potential (grounding =) 1:Rf potential) is maintained at an intermediate potential above the threshold voltage of this MOS transistor. Then, the gate width of the MOSt-transistor is increased so that the necessary drain-source current can be obtained. Therefore, the voltage between the drain and source of this MOS transistor is lower than that of the conventional one, and a large current flows, allowing the logic circuit to operate at high speed.

(Example) Hereinafter, the present invention will be described in detail based on the example shown in the drawings.

In the inverter circuit shown in FIG. 1, there is a first conductivity type (P channel) MOS transistor 5 whose source is connected to a first power supply potential (positive power supply potential), and this P channel M
An intermediate potential generation circuit is connected to the gate of the OS transistor 5, which outputs an intermediate potential whose source-to-gate voltage does not reach the second power supply potential (ground potential) and which is equal to or higher than the threshold voltage. Further, a second conductivity type (N-channel) MOS transistor F has a drain connected to the drain of the P-channel MO5 transistor 5, a source connected to a second power supply potential (ground potential), and an input signal input to the gate. There is. Furthermore, an output signal is output from the connection point between the drain of the P-channel MOS transistor 5 and one end of the N-channel MOS transistor 7.

Diagrams showing the states of input and output signals of the inverter circuit shown in FIG. 1 are shown in FIGS. 2(a) and 2(b). In FIG. 2(a), the vertical axis represents the potential of the human input signals 1 and 7 input to the gate of the second conductivity type (n-channel) MOS transistor 7, and the horizontal axis represents time. This figure 2 (a)
In this case, the input signal l is initially at the second power supply potential (ground potential) level, changes to the first power supply potential ('positive power supply potential) level, and then returns to the second power supply potential (ground potential) level. It's changing. The output signal core corresponding to this input signal is the first node Lebel (H) as shown in Figure 2(b).
The state changes to the second level (L), and then changes again to the second level (H) as shown by ■'. In this way, the change in the output signal is delayed in time with respect to the change in the input signal, and the change in the rising portion from the second level (L) to the second level (H) corresponds to the change in the potential level of the input signal. It was later in time compared to . The change in the rise is faster than in the conventional case.

FIG. 3 is a current and voltage characteristic diagram between the source and drain of the first conductivity type (P channel) MOS transistor 5 and the second conductivity type (N channel) MOS transistor 5, The characteristic when the gate potential of the P-channel MOSt-transistor 5 is kept at the second power supply voltage (ground potential) is shown by a broken line (■). Further, the characteristics when the gate potential of the second conductivity type (N channel) MOS transistor 7 is kept at the first power supply potential (positive power supply potential) are shown by the solid line ■
It is indicated by. The intersection point A between the broken line (■) and the solid line (■) indicates that the first conductivity type (P-channel) MOS transistor 5 and the second conductivity type (N-channel) MOS transistor 7 are both in a conductive state, and there is a difference from the power supply voltage. This is the through current of the path where the voltage at point A is applied. At point B, the second conductivity type (N channel) MOS transistor 5 is in a non-conducting state, the first conductivity type (P channel) MOS transistor 5 is in a conductive state, there is no potential difference between the source and the drain, and the drain, This shows a state in which no current flows between sources.

When the potential of the gate of the second conductivity type (n-channel) MOS transistor 7 changes from the first power supply potential (positive power supply potential) to the second power supply potential (ground potential), the voltage/current characteristics between the source and drain are as follows. A change occurs from point A to point B. The current flowing between the source and drain of the first conductivity type (P channel) MOS transistor 5 before moving from point A to point B is the charging current value accumulated in the wiring and the next stage MOS transistor. This charging current value is shown in Fig. 2(b).
This determines the rising speed of the output signal shown in . Further, the current value at point A is equal to the current value of the first conductivity type (P
Channel) is the current value flowing between the drain and source of the MOS transistor 5, and determines the output of the inverter circuit. Therefore, the first conductivity type (P channel) MOS
Even if the voltage between the source and drain of transistor 5 is at a level much lower than point A, a current almost the same as that at point A will flow between the source and drain, as shown by the solid line ■' in Figure 3. , this inverter circuit can operate accurately and can also operate at high speed.

To do this, first, the gate voltage of the first conductivity type (P channel) MOS transistor 5 is adjusted to OV, which is the second power supply potential (ground potential), as shown by the broken line ■ in FIG.
(The absolute value of the potential difference between the gate and source is 5V), but the gate voltage is Ov (the absolute value of the potential difference between the gate and source is 5V).
By maintaining the potential at an intermediate potential between V) and the threshold voltage, a characteristic state with a wide saturation region can be obtained.

Next, in order to make the characteristic curve indicated by the broken line ■ in FIG. Then, the characteristic curve is made to have a wide saturation region as indicated by the broken line (■), and a characteristic curve as indicated by the solid line (■') passing through point A is obtained. By doing as described above, it becomes possible to provide an inverter circuit with a fast response speed as shown by the solid line ■'9 in FIG. 2(b).

Here, the absolute value of the potential difference between the gate potential of the first conductivity type (P channel) MOS transistor 5 and the source side is set to the second power supply potential when the absolute value of the potential difference between the gate potential of the first conductivity type (P channel) MOS transistor 5 is equal to or higher than the threshold voltage of the first conductivity type (P channel) MOS transistor 5. (ground potential), and an appropriate current is set in consideration of the current-voltage characteristics of the (P-channel) MOS transistor 5 and the second conductivity type (N-channel) MOS transistor. Here, the first conductivity type (P channel) MOS
The current between the source and the drain of the transistor 5 is proportional to the square of the difference between the threshold voltage of this MOS transistor and the absolute value of the voltage between the gate and the source. Therefore, by applying an intermediate potential to the gate, the voltage between the gate and source decreases, and the current between the source and drain also decreases.

Also, since the current between the source and drain is proportional to the gate,
In order to obtain the source-drain current value when no intermediate potential is applied to the gate, the gate width is increased to obtain the desired current value.

In addition, in order to increase the electric potential between the source and the drain 5, the intermediate potential is given as a critical intermediate potential.
Although it is desirable that the voltage be near the threshold voltage of the OS transistor, the MOS transistor will not operate stably near the threshold voltage. Therefore, when the voltage is close to the threshold voltage and the MO
By setting the intermediate potential to a potential that is approximately twice the threshold voltage at which the S transistor can operate stably, the inverter can operate at high speed.

In this way, the first conductivity type (P channel) MOS transistor 5 is controlled so that the desired operating speed can be obtained when the voltage does not exceed the threshold voltage of the next stage MOS transistor.
By setting the gate width of , the operation becomes faster than before at the rise of the output signal.

As mentioned above, the effect of the first embodiment is that the operation of the output signal corresponding to the change in the input signal is faster than in the conventional case.

Incidentally, as a modification of the first embodiment, the intermediate potential generation circuit is not connected to the gate of the first conductivity type (P channel) MOS transistor 5, and the input signal is inputted,
There is also an inverter 5 to which the intermediate potential generation circuit is connected to the gate of the second conductivity type (N channel) MOS transistor 7.

In this inverter, unlike the first embodiment, the operating speed at the rising edge of the output signal is not improved, but the operating speed at the falling edge of the output signal is increased.

The intermediate potential generating circuit connected to the gate of the first conductivity type (P channel) MOS transistor 5 is shown in FIGS. 4(a) and 4(b).

(C) etc.

The one shown in FIG. 4(a) includes a first conductivity type (P channel) MOS transistor 9 whose source is connected to a first power supply potential (positive power supply) and whose gate is connected to an output end;
One end of a resistor 11 is connected to the drain of the first conductivity type (P channel) MOS transistor 9 . The other end of this resistor 11 is connected to a second power supply potential (ground potential). Further, since the gate of the first conductivity type (P channel) MOS transistor 9 is connected to the drain, the gate potential and the drain potential are kept at the same level, and the gate potential is the same as the first conductivity type (P channel) MOS transistor 9 in FIG. Conductivity type (P channel)
Since it adopts a current mirror configuration that serves as the gate potential of the MOS transistor 5, it is highly stable against fluctuations in the threshold voltage and drive current of the first conductivity type (P channel) MoS transistor 9 caused by errors in the manufacturing process. Demonstrate operation.

Furthermore, in order to reduce the DC path in this intermediate generation circuit, the gate width of this P channel MO5 transistor 9 is reduced.

The one shown in FIG. 4(b) is the one in which the resistor 11 in FIG. 4(a) is replaced with a transfer gate, and this transfer gate is connected to the gate drain.
A second first conductivity type (P channel) MOS transistor 13 whose other end is connected to a second power supply potential (ground potential), and whose gate is connected to a first power supply potential (positive power supply) and whose one end is connected to the a second conductivity type (N channel) MOS transistor 15 connected to the other end of the first conductivity type (P channel) MoS transistor 9 and having the other end connected to a second power supply potential (ground potential);
It has This intermediate potential generation circuit has a fourth circuit (a).
) The use of a transfer gate, which has the same effect as the circuit described above and is easier to manufacture than a resistor, has the effect of facilitating manufacture.

The third intermediate potential generation circuit shown in FIG.
The edge is 3i'! 111tg! (positive power supply),
a first conductivity type MOS transistor 1 whose other end is connected to the gate; one end connected to the other end of the first first conductivity type MOS transistor 17 and the other end connected to the back gate;
The gate is the first first conductivity type MOS transistor 17
a first second conductivity type MOS transistor 19 connected to the gate of the second conductivity type MOS transistor 19; one end connected to the first second conductivity type MOS transistor 19; one end connected to the second power supply potential; the first of
a load element 23 connected to the other end of the conductivity type MOS transistor 21; one end connected to a first power supply potential, and a gate connected to the first first conductivity type MOS transistor 17 and the first second conductivity A second type MOS transistor connected to the connection point of the type MOS transistor 19
a second conductivity type MOS transistor 25, one end connected to the other end of the second second conductivity type MOS transistor 25, and the other end connected to the second power supply potential;
The gate is the second first conductivity type MOS transistor 21
and a third first connected to the connection point of the load element 23.
A connection point between the third MOS transistor 27 of the first conductivity type and the second MO8 transistor 25 of the second conductivity type serves as an output end. The gate widths of the third MOS transistor 27 of the first conductivity type and the second MOS transistor 25 of the second conductivity type are the same as those of the first MO8 transistor 1 of the first conductivity type.
7. The gate width is set larger than the gate width of the first second conductivity type MOS transistor 19, the second first conductivity type MO8 transistor 21, and the load element 23, so that the driving force is large.

Therefore, the DC bus flows only through the first MO8 transistor 17 of the first conductivity type, the first MOS transistor 19 of the second conductivity type, the second MOS transistor 21 of the first conductivity type, and the load element 23. The amount is several μA, which is a value that can be ignored.

Next, a second embodiment of the present invention will be described. A second embodiment of the invention, shown in FIG. 5, is a NOR circuit. This NO
The R circuit is of a first conductivity type (
P-channel) MOS transistor 29, an intermediate potential generation circuit that outputs an intermediate potential that does not reach the second power supply potential and exceeds the threshold voltage, and a drain of the first conductivity type (P-channel) MOS transistor 29;
P channel) is connected to the drain of the MOS transistor 29, the source is connected to the second power supply potential (grounded),
A plurality of second conductivity type (N
channel) MOS transistor 31;
An output signal is output from a connection point between the drain of the conductivity type (P channel) MOS transistor 29 and the drain of the second conductivity type (N channel) MOS transistor 31.

Specifically, in order to increase the current between the source and the drain, it is desirable that the intermediate potential be around the threshold voltage of the MOS transistor to which the intermediate potential is applied, but stable operation of the MOS transistor is not possible near the threshold voltage. Not done. Therefore, by setting the intermediate potential to a potential that is approximately twice the threshold voltage, the NOR circuit can operate at high speed.

Furthermore, when a plurality of these NOR circuits are used in a semiconductor device, as shown in FIG. It is configured to be connected to each gate of the channel) MOS transistor 29/, and there is no need to provide a plurality of intermediate potential generation circuits (and the area of the semiconductor chip is not increased).

Next, a third embodiment shown in FIG. 7 will be described.

This embodiment is a NAND circuit, with one end connected to the second power supply potential (ground) and the gate connected to the intermediate potential generation circuit. a second conductivity type (n channel) MOS transistor 33, one end connected to the first power supply potential (positive power supply), and the other end connected to the other end of the second conductivity type (n channel) MOS transistor 33; A plurality of first conductivity type (P channel) MOS transistors 35 whose gates receive input signals, and whose output ends are the second conductivity type (n channel).
an intermediate potential generating circuit connected to the gate of the MOS transistor 37 to keep the voltage at the output terminal at an intermediate potential not reaching the second power supply potential and higher than the threshold voltage; P channel) MOS transistor 35
An output signal d is output from a connection point between the other end and one end of the second conductivity type (N channel) MOS transistor 33.

In this third embodiment, the second conductivity type (n channel)
Conventionally, a potential is applied to the gate of the MOS transistor 33 such that the absolute value of the potential difference obtained by subtracting the source potential from the gate potential exceeds the threshold voltage of this transistor, thereby applying the first power supply potential to the gate. N of
The response operation is faster than the AND circuit.

The intermediate potential generation circuit connected to the gate of the second conductivity type (n-channel) MOS transistor is shown in FIGS. 8(a) and 8(b).
, shown in (c). When such an intermediate potential generation circuit is connected to the gate of the second conductivity type MOS transistor, there is an effect that the operating speed at the fall of the output signal becomes faster.

The intermediate potential generation circuit shown in FIG. 8(a) includes a resistor 37 whose one end is connected to a first power supply potential (positive potential), a drain and a gate connected to the other end of this resistor 37, and this connection point. is the output terminal, and the source is connected to the second power supply potential (ground potential).
MOS transistor 39. Since the gate of this first second conductivity type (N channel) MOS transistor 39 is connected to the drain, the potential of the gate and the potential of the drain are kept at the same level. Highly stable operation is possible against fluctuations in the threshold voltage and drive current of the two-conductivity type (N-channel) MOS transistor 39.

Furthermore, by reducing the gate width of the first and second conductivity type (N-channel) MOS transistors 39, it is possible to reduce the DC path in this intermediate potential generation circuit.

The one shown in FIG. 8(b) is the one in which the resistor 37 in FIG. 8(a) is replaced with a transfer gate, the gate of which is connected to the second power supply potential (ground potential), One end is the first power supply potential (positive power supply potential)
and the other end is connected to the drain of the first second conductivity type (N channel) MOS transistor 39.
A conductivity type (P channel) MOS transistor 41, a gate and one end connected to a first power supply potential (positive power supply potential),
It has a second second conductivity type (N channel) MOS transistor 43 whose other end is connected to the drain of the first second conductivity type (N channel) MOS transistor 41 . This intermediate potential generation circuit has the same effect as the circuit shown in FIG. 8(a), and also has the advantage of being easy to manufacture by using a transfer gate, which is easier to manufacture than a resistor.

The intermediate potential generation circuit shown in FIG. 8(c) is
005108 specification, and has one end connected to a first power supply potential (positive power supply) and a gate connected to a second power supply potential (ground potential). ) MOS transistor 45 and a first second conductivity type (P channel) MOS transistor 45 whose one end and gate are connected to the other end of the first first conductivity type (P channel) MOS transistor 45 and whose other end is connected to the back gate. a second conductivity type (N-channel) MOS transistor 47, one end of which is connected to the other end of the first second conductivity type (N-channel MOS) transistor 47 and the back gate, and the other end of which is connected to the gate; The first conductivity type (P
One end and gate of the channel) MOS transistor 49 are connected to the other end and gate of the second first conductivity type (P channel) MOS transistor 49, and the other end is connected to a second power supply potential (ground potential). a second conductivity type (N channel) MOS transistor 51, one end of which is connected to the first 'Wi';
source, the potential (positive power supply potential), and the gate is connected to the first power supply potential (positive power supply potential).
a third second conductivity type (N channel) MOS transistor 53 connected to a connection point between the first conductivity type (P channel) MOS transistor 45 and the first second conductivity type (N channel) MOS transistor 49; , one end is connected to the other end of the third second conductivity type (N channel) MOS transistor 53, and the gate is connected to the second first conductivity type (P channel) MOS transistor 49 and the second second conductivity type (P channel) MOS transistor 53. a third first conductivity type (P channel) MOS transistor 55 connected to the connection point of the conductivity type (N channel) MOS transistor 49 and having the other end connected to the second power supply potential (ground potential); the third second conductivity type (N channel) MOS transistor 53 and the third first conductivity type (N channel) MOS transistor 53;
The connection point of the P-channel) MOS transistor 55 serves as an output end.

Then, the third MOS transistor 55 of the first conductivity type
The gate width of the third MOS transistor 53 of the second conductivity type is equal to that of the first MOS transistor 4 of the first conductivity type.
5. The gate width is set larger than the gate width of the first second conductivity type MOS transistor 47, the second first conductivity type MOS transistor 49, and the second second conductivity type MOS transistor 51, and the driving force is is getting bigger.

Therefore, the DC path includes the first MO8 transistor 45 of the first conductivity type, the first MO8 transistor 47 of the second conductivity type, and the second MOS transistor 47 of the first conductivity type.
9 and the second second conductivity type MOS transistor 51, the amount is several μA, which is a negligible value.

Furthermore, since the gates and other ends of the second first conductivity type MOS transistor 49 and the second second conductivity type MoS transistor 51 are connected, the threshold values of these MOS transistors 49 and 51 are fluctuated. It shows high stability against. In this way, the output potential of this intermediate potential generation circuit becomes a stable potential that does not depend on fluctuations in the power supply.

Next, a fourth embodiment is shown in FIG. This fourth embodiment is an exclusive OR circuit, and includes a first conductivity type (P channel) MOS transistor whose one end is connected to a first power supply potential (positive power supply potential) and whose gate is connected to an intermediate potential generation circuit. There are 57.

Further, this exclusive OR circuit includes an intermediate potential generation circuit that sets the voltage between the source and the gate to a potential that does not reach the second power supply potential (ground potential) and is equal to or higher than the threshold voltage;
a first second conductivity type (N channel) MOS transistor 59 whose end is connected to the other end of the first conductivity type (P channel) MOS transistor 57 and whose gate receives the input signal A; A second conductive type (N-channel) MOS transistor whose one end is connected to the other end of the second conductive type (N channel) MOS transistor 59, whose gate receives the human power signal B, and whose other end is connected to the second power supply potential (ground). (N channel) MOS transistor RO 1, and one end is the first conductivity type (P channel) MO
A third second conductivity type (N channel>MOS transistor RO 3) connected to the other end of the S transistor 57 and having its gate inputted with an input signal A having an inverted potential of the input signal λ.
and one end is the third second conductivity type (N channel) MOS
A fourth second conductivity type transistor (4) is connected to the other end of the transistor 63, has its gate inputted with an input signal B having an inverted potential of the input signal B, and has the other end connected to a second power supply potential (ground potential). N-channel) MOS transistor 65, and one end of which is the first conductivity type (P-channel) MOS transistor 57.
a fifth second conductivity type (N channel) MOS transistor 67 connected to the other end and having the input signal C input to the gate;
and one end is the fifth second conductivity type (N channel) MOS
a sixth second conductivity type (N-channel) MOS transistor 9 connected to the other end of the transistor 67, having its gate input with an input signal and having the other end connected to a second power supply potential (ground potential); One end is the first conductivity type (P channel) MO
a seventh second transistor connected to the other end of the S transistor 57 and having a gate inputted with C having an inverted potential of the input signal C;
A conductivity type (N-channel) MOS transistor 71 is connected at one end to the seventh second conductivity type (N-channel) MOS transistor 71, and a core having an inverted potential of the input signal is input to the gate, Eighth second conductivity type (N channel) M whose other end is connected to the second power supply potential (grounded type 1st position)
It is equipped with an OS transistor 3. Further, this circuit includes the first conductivity type (P channel) MOS transistor 57.
the other end of the second conductive type MOS transistor 59, the third second conductive type MOS transistor 63,
The connection point of the one end of the fifth second conductivity type MOS transistor 67 and the seventh second conductivity type MOS transistor 71 is the output end.In this way, the intermediate potential generation circuit is connected to the first conductivity type MOS transistor 67. By being connected to the gate of a type MOS transistor, there is an effect that the operation is faster than an exclusive OR circuit in which a second power supply potential (ground potential) is conventionally applied to the gate.

The present invention is based on the first aspect explained above. Second. Third. The present invention is not limited to the fourth embodiment, and can be applied to other logic circuits that require high-speed operation. Also, the intermediate potential generation circuit is the fourth
Figures (a), (b), (c) and Figure 8 (a), (b),
It is not shown in (c), and any circuit that outputs a stable intermediate potential may be used.

In particular, in logic circuits that require multiple inputs, the resistance of series-connected MOS transistors increases, resulting in slow response operations, so the application of the present invention is highly effective.

In addition, when an intermediate generation circuit is connected to the gate of the first conductivity type transistor in the logic circuit, the operation when the output signal that withstands the human input signal rises from the second level (L) to the first level (H) This has the effect of making it faster than before. In addition, when an intermediate potential generation circuit is connected to the gate of the second conductivity type MOS transistor in the logic circuit, the operation when the output signal rises from the second level (H) to the second level (L) with respect to the input signal This has the effect of making it faster than before. In this way, by connecting the intermediate potential generation circuit to the gate of the first conductivity type MO5 transistor or the second conductivity type MOS transistor in the logic circuit, the rising or falling operation of the output signal becomes faster. Depending on the purpose, an intermediate potential generation circuit may be connected to the gate of the first conductivity type MOS transistor or the second conductivity type MOS transistor.

[Effects of the Invention] As explained above, the present invention provides a semiconductor logic circuit in which an intermediate potential that exceeds the threshold voltage and does not reach the second power supply potential is applied to the gate of at least one transistor. By increasing the gate width of the semiconductor logic circuit, it is possible to speed up the output operation of this semiconductor logic circuit.

4. Detailed Description of the Invention Fig. 1 is a block diagram showing the first embodiment of the present invention, Fig. 2 is an operational waveform diagram of the first embodiment of the present invention and the conventional example, and Fig. 3 is a diagram showing the configuration of the first embodiment of the present invention. FIG. 4 is a static characteristic diagram of the first conductivity type MOS transistor of the first embodiment, FIG. 4 is a circuit diagram of the intermediate potential generation circuit connected to the gate of the first conductivity type MOS transistor, and FIG. 6 is a block diagram showing a modification of the second embodiment of the present invention, FIG. 7 is a block diagram showing a third embodiment of the present invention, and FIG. 8 is a block diagram showing the third embodiment of the present invention. Second conductivity type MO
FIG. 9 is a circuit diagram of an intermediate potential generation circuit connected to the gate of the S transistor, FIG. 9 is a configuration diagram showing a fourth embodiment of the present invention, and FIG. 10 is a circuit diagram of a conventional semiconductor circuit device.

1.5, 9.15, 17.21.27.29°35.4
1.45.49.55.57...first conductivity type MOS transistor, 3,7,13,19°23.25,31.
33,39,43,47゜51.53,59.61,6
3,65.67゜69.71.73...Second conductivity type M
OS transistor.

Claims (4)

[Claims] (1) A first conductivity type MO whose one end is connected to the first power supply potential, whose source-to-gate voltage is higher than the threshold voltage, and which is connected to an intermediate level potential that does not reach the second power supply potential.
an intermediate potential generation circuit whose output end is connected to the gate side of the first conductivity type MOS transistor and which maintains the gate side of the first conductivity type MOS transistor at the intermediate level potential; and the first conductivity type MOS transistor. One end is connected to the other end of the MOS transistor, an input signal is input to the gate side, and the other end is connected to the second end.
A semiconductor circuit device comprising: a second conductivity type MOS transistor connected to a power supply potential. (2) The intermediate potential generation circuit is a first conductivity type MO whose one end is connected to the first power supply potential and the other end is connected to the gate.
an S transistor; and a resistor, one end of which is connected to the second power supply potential and the other end of which is connected to the other end of the first conductivity type MOS transistor, and the first conductivity type MOS transistor and the resistor are 2. The semiconductor circuit device according to claim 1, wherein the connection point is the output end. (3) The intermediate potential generation circuit includes a first first conductivity type MOS transistor having one end connected to the first power supply potential and the other end connected to a gate, and one end connected to the second power supply potential. a second first conductivity type M, whose other end is connected to the other end of the first first conductivity type MOS transistor, and whose gate is connected to the second power supply potential;
an OS transistor; a second conductive transistor having one end connected to the second power supply potential, the other end connected to the other end of the first conductivity type MOS transistor, and a gate connected to the first power supply potential; MOS transistor, and a connection point between the first MOS transistor of the first conductivity type, the second MOS transistor of the first conductivity type, and the MOS transistor of the second conductivity type is the output terminal. The semiconductor circuit device according to claim (1). (4) The intermediate potential generation circuit includes a first conductivity type MOS transistor having one end connected to the first power supply potential and the other end connected to a gate; a first second conductivity type MOS transistor connected to the other end of the conductivity type MOS transistor, the other end connected to a back gate, and a gate connected to the gate of the first first conductivity type MOS transistor; a second first whose one end is connected to the other end of the first second conductivity type MOS transistor and whose other end is connected to the gate;
a conductivity type MOS transistor; a load element having one end connected to a second power supply potential and the other end connected to the other end of the second first conductivity type MOS transistor; one end connected to the first power supply potential; a second second conductivity type MOS transistor whose gate is connected to the connection point of the first first conductivity type MOS transistor and the first second conductivity type MOS transistor; a second conductivity type MOS transistor, the other end is connected to the second power supply potential, and a gate is connected to a connection point between the second first conductivity type MOS transistor and the load element. 3 MOS transistors of the first conductivity type, and a connection point between the third MOS transistor of the first conductivity type and the second MOS transistor of the second conductivity type is the output terminal. (1) The semiconductor circuit device described.