JP2545995B2 - Logic circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit using complementary MIS (metal insulating film semiconductor) FETs, and more particularly to a logic circuit configured by a ratio circuit.

[Prior Art] Conventional NOR composed of a CMOS integrated circuit
As the circuit, the circuit shown in FIG. 5 is known. This circuit includes P-channel MOSFETs MP ₁₁ , MP ₁₂ , ..., MP _1n connected in series between a power supply V _DD and an output terminal, and an N-channel MOSFET MN connected in parallel between the output terminal and the ground. ₁₁ , MN ₁₂ ,
, MN _1n and the input signals S ₁ , S ₂ , ..., S _n are input to the gates of these MOSFETs, and the output signal S ₀ which is the NOR result is output from the output end. ing.

However, in this circuit, P-channel MO with n output terminals is used.
Since it is connected to the power supply V _DD through SFETMP ₁₁ , MP ₁₂ , ..., MP _1n , there is a problem that it takes time for the signal to rise.

Therefore, as a solution to this drawback, a CMOS / NOR circuit using a ratio circuit as shown in FIG. 6 is known. In this circuit, instead of the n P-channel MOSFETs MP ₁₁ , MP ₁₂ , ..., MP _1n in the ratioless circuit described above, a P-channel MOSF as a load whose gate is grounded is used.
The ETMP ₁ is connected between the power supply V _DD and the output terminal so that the N-channel MOSFETs MN ₁₁ , MN ₁₂ , ..., MN _1n connected in parallel function as a driver for driving the P-channel MOSFET MP _1. There is.

According to this circuit, since only one FET is connected between the power supply V _DD and the output terminal, the rise time of the output is short and the circuit can be speeded up. This effect appears as a remarkable effect as the number of inputs increases.

Further, according to this circuit, since the gate width of the P-channel MOSFET can be reduced, it is possible to reduce the drain junction capacitance of the P-channel MOSFET, and the gate capacitance does not become a load in the preceding stage. Not only the time but also the fall time can be shortened.

Similarly, FIG. 7 shows a conventional ratioless NAND circuit, FIG.
The figure is a diagram showing each NAND circuit by the ratio circuit.

In FIG. 7, n P-channel MOSFETs MP ₃₁ , MP ₃₂ , ..., MP _3n are connected in parallel between the power supply V _DD and the output terminal, and n pieces are provided between the output terminal and the ground. N-channel MOSFET
MN ₂₁ , MN ₂₂ , ..., MN _2n are connected in series. On the other hand, in the circuit of FIG.
_21, MN _22, ......, instead of MN _2n, N-channel MOSFETMN ₂ as a load whose gate is biased to the supply voltage V _DD is connected.

Also in this NAND circuit, the latter ratio circuit can speed up the circuit operation because there is no FET connected in series.

[Problems to be Solved by the Invention] However, in the logic circuit using the conventional ratio circuit described above, although the speed can be increased as compared with the normal ratioless circuit as described above, the direct current supplied between the power supply and the ground is used. Since a current flows, a low current is an important issue in this type of circuit. Especially load
Since the power supply voltage is directly applied between the gate and source of the FET, if the operating power supply voltage range is wide, the target operating speed must be guaranteed at the lower limit of the operating power supply voltage. If it is high, there is a problem that an unnecessarily large current flows into the circuit.

The present invention has been made in view of the above problems, and can prevent an unnecessarily large current from flowing even when the power supply voltage becomes high, and simultaneously achieves high speed and low power consumption. An object of the present invention is to provide a logic circuit that can be designed.

[Means for Solving the Problem] A logic circuit according to the present invention includes a load including a first FET of a first conductivity type connected between a first power supply and an output terminal,
A plurality of second conductivity type second transistors connected in parallel between the output terminal and the second power source and inputting input signals to their respective gates.
A driver including an FET and a bias circuit for applying a gate bias voltage to the gate of the first FET, and the bias circuit is a resistor connected between the bias output terminal and the second power supply. And a first conductive type third FET that is connected between the bias output terminal and the first power supply, receives a feedback signal from the resistance at the gate, and has a threshold value different from that of the first FET. , The resistance value of the resistor is set to 1/2000 to 1/5 of the resistance value when the gate of the third FET is biased to its threshold value.
The threshold value of the FET is set to a value at which the voltage at the bias output terminal becomes equal to the threshold voltage of the third FET when the lower limit value of the operating power supply voltage range is given as the power supply voltage. It is characterized by being.

[Operation] According to the present invention, the gate bias voltage of the first FET as a load connected between the first power supply and the output end is
It is given from the bias circuit. The third FET that constitutes the bias circuit changes the power supply voltage applied to it,
When the voltage between the gate and the source changes, the drain current changes accordingly. Therefore, the feedback of the resistance is applied to the gate of the third FET, and the third FET is
The bias output acts to maintain a constant bias voltage.

On the other hand, the threshold value of the third FET and the resistance value of the same resistor forming the bias circuit are such that when the lower limit value of the operating power supply voltage range is given as the power supply voltage, the voltage at the bias output terminal is the third value. It is set to a value that is equivalent to the threshold voltage of the FET.

Therefore, even when the power supply voltage is small, a sufficiently high speed operation is possible, and even when the power supply voltage becomes large, the first
Since the fluctuation of the gate bias voltage of the FET is small, it is possible to prevent the direct current from increasing more than necessary.

[Embodiment] A logic circuit according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a CMOS ratio NOR according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a circuit. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals, and the duplicated description will be omitted.

The circuit of this embodiment is different from the conventional circuit shown in FIG. 6 in that a bias circuit 1 is newly provided and a P-channel MOSFET MP ₁ for a load connected between a power supply V _DD and an output terminal is provided.
Is that the gate voltage is applied from the bias output terminal of the bias circuit 1.

The bias circuit 1 is composed of an enhancement type P-channel MOSFET MP ₂ and a resistor R ₁ which are connected in series between a power source V _DD and ground. The gate and drain of MOSFET MP ₂ are connected, and this connection point is connected to the gate of MOSFET P ₁ as a bias output terminal.

The MOSFET MP ₂ is set so that its threshold value is approximately equal to the lower limit value of the operating power supply voltage range, and the resistor R ₁ is a resistor when the gate of the MOSFET MP ₂ is biased to that threshold value. 1/2000 to 1/5 of resistance (= V _DS / I _DS is drain-source voltage, I _DS is drain-source current)
Is set to

With this setting, due to the steep I _DS -V _DS characteristics near the threshold power supply, at the lower limit of the operating power supply voltage, the output of this bias circuit becomes almost the ground potential, and the output shown in FIG. A rising characteristic similar to the example can be obtained. On the other hand, when the power supply voltage is high, the bias output potential A of the bias circuit 1 rises, so P
The current value of the channel MOSFET MP ₁ does not increase more than necessary, and the current can be reduced.

Next, in order to achieve the above actions and effects, the operating power supply voltage range is 1.8 to 3.6.
The case of V will be specifically described.

The operating power supply voltage range of 1.8 to 3.6V is currently mainly used in 3V system. In this case, the lower limit of the operating power supply voltage from a 1.8V, for setting the threshold voltage of MOSFETMP ₂ to -1.8 V. In the current 1-2 μm rule silicon gate CMOS integrated circuit process, the P-channel MOSFET having a threshold voltage of this level performs general ion implantation to the gate portion for threshold adjustment. It can be obtained by not having.

The measured values of the current characteristics of the P-channel MOSFET MP ₂ thus obtained are shown in FIG. This figure shows Vt (=
M represented by the absolute value of the threshold voltage of MOSFET MP ₂ )
The gate-source voltage of OSFETMP2 is taken and the vertical axis is MOSFET
The current characteristics are shown by taking the current value (relative current value) between the source and drain in the state where the drain of the same P-channel MOSFET MP as MP ₂ is connected to the gate. Here, the relative current value is a value obtained by normalizing the source-drain current of the P-channel MOSFET by the source-drain current when the gate-source voltage is a threshold voltage. is there. However, this vertical axis is represented by a logarithmic scale. As is well known, the source-drain current is
In the region where the gate-source voltage is lower than Vt, the gate
It exhibits an exponential change with respect to the source-to-source voltage, and exhibits a squared characteristic when the gate-source voltage increases.

FIG. 3 shows the MOSFET MP of FIG. 1 based on the characteristics of FIG.
The characteristic of the voltage V _BB of the bias output A of the bias circuit 1 composed of ₂ and the resistor R ₁ is V _{DD on} the horizontal axis and (V _DD −
V _BB ), and the relative resistance value of R _{1 to} MOSFET MP ₂ is expressed as a parameter. Here MOSFETMP The relative resistance of the resistor R ₁ for _2, the resistance value when the gate and drain of MOSFETMP ₂ is biased to the threshold
Vt / I _DS (I _DS : source-drain current). Also,
V _DD -V _BB represents the gate-source voltage itself of the load MOSFET MP ₁ forming the n-input NOR.

As is clear from FIG. 3, the relative resistance value is 1/181
Then, at the minimum operating voltage of 1.8V, V _DD −V _BB = 1.799V
Thus, a gate-source voltage similar to that of the conventional example shown in FIG. 5 in which the gate of the MOSFET MP ₁ is grounded is obtained, the capability of the MOSFET MP ₁ is similar to that of the conventional circuit, and a high rising speed can be obtained.

On the other hand, when V _DD = 3 V, V _DD −V _BB ≈2.28 V, and when V _DD = 3.6 V, V _DD −V _BB ≈2.40 V, which means that M
Since the gate bias applied to the OSFETMP ₁ is suppressed, the performance of the MOSFET MP ₁ is suppressed from being increased more than necessary, and the current consumption can be reduced. By the way, when the threshold voltage of the MOSFET MP ₁ is −0.7 V and the low-level output voltage S ₀ of the n-input NOR circuit is ₀ V, the effect of reducing the current of the circuit of this embodiment at the time of low-level output is calculated as follows: Voltage is 3V
At times it looks like this:

^{(2.28-0.7) 2 /(3.0-0.7) 2 ≒} 0.472 The power supply voltage is 3.6V sometimes as follows.

^{(2.4-0.7) 2 /(3.6-0.7) 2 ≒} 0.344 As apparent from the above calculation results, about 1 / 2.1 of the conventional for the former, also about 1 / 2.9 for the latter conventional
In addition, the current is reduced.

As is apparent from FIG. 3, such a current reducing effect is expected up to a relative resistance value of the resistance R ₁ of about 1/2000 when V _DD = 3V. If the relative resistance value of the resistor R ₁ is increased,
Although the effect of lowering the current becomes even greater, V _DD -V _BB at the lower limit of 1.8 V of the operating power supply voltage range becomes smaller, so it is necessary to pay attention to the decrease in the rising speed. By the way, V _DD =
At 1.8V, R _{1 has} a relative resistance value of 1/19 and V _DD −V _BB ≈1.73
The relative resistance value of V and R ₁ is 1/10 and V _DD −V _BB ≈ 1.66V.

Therefore, the resistance R ₁ has a relative resistance value of 1/2000 to 1 /
It is desirable to set the resistance value to be 10.

Next, in this embodiment, the threshold value of the MOSFET MP ₂ is set to −1.8.
The case of shifting from V will be described.

When the threshold value is further shifted in the − direction, it corresponds to the parallel displacement of each curve in FIG. 3 to the upper right, substantially parallel to the straight line of V _BB = 0V. At this time, if the threshold value has an absolute value larger than the upper limit of the operating power supply voltage range,
It is necessary to pay attention to this point because the effect of reducing the current is completely lost.

On the other hand, when the threshold value is shifted in the + direction, when the relative resistance value of R ₁ is 1/181, 0.5 × (1.8V-Vt) to (1.8V
It is necessary to pay attention to this point because the value of V _DD -V _BB at 1.8 V becomes smaller by -Vt) and the rising speed decreases.

FIG. 4 is a circuit diagram showing an n-input CMOS ratio NOR circuit according to the second embodiment of the present invention. In FIG. 4, the same parts as those in FIGS. 1 and 6 are designated by the same reference numerals,
A description of the overlapping parts will be omitted.

The circuit of this embodiment differs from the circuit of the first embodiment shown in FIG. 1 in the configuration of the bias circuit. The bias circuit 2 in this embodiment is an enhancement type P-channel MOSFET connected between the power supply V _DD and the bias output terminal.
MP ₃ and, a resistor R ₂ connected between ground and the bias output terminal, resistor R ₃ which gives the divided output is connected between the power supply V _DD and the bias output to the gate of MOSFETMP ₃ , R ₄
And a voltage dividing circuit. That is, the second embodiment is different from the first embodiment in that the gate of the MOSFET MP ₃ is not directly connected to the bias output terminal, but the power supply V _DD to bias voltage is divided and applied. The resistance
The resistance value of R ₃ + resistance value of resistance R ₄ is set sufficiently higher than the resistance value of resistance R ₂ . This voltage division ratio is set so as to substantially match the threshold value of MOSFET MP ₃ when V _DD is the lower limit value of the operating power supply voltage range, as in the embodiment of FIG.

According to this embodiment, a large P-channel MOSF is provided so that the absolute value of the threshold value substantially matches the lower limit value of the power supply voltage range.
Even if ET is not used, by dividing the output voltage with resistors R ₃ and R ₄ , MOSFET MP ₄ whose absolute threshold value is smaller than the lower limit value of the power supply voltage range can be biased near the threshold value. it can. However, it should be noted that the amount of feedback is reduced by the voltage division ratio of the resistors R ₃ and R ₄ , so that the current reduction effect is less than that in the first embodiment. Even with P-channel MOSFETs having different threshold values, the gate voltage represented by the threshold value Vt substantially agrees with the characteristics shown in FIG.

In each of the above embodiments, the n-input NOR circuit having the P-channel MOSFE as a load has been described.
It goes without saying that the present invention can be applied to an n-input NAND gate having an OSFET as a load.

Further, the present invention is applicable not only to a CMOS logic circuit but also to a ratio logic circuit using another complementary MISFET using a nitride film gate.

[Effects of the Invention] As described above, according to the present invention, when the lower limit value of the operating power supply voltage range is given as the power supply voltage, a bias equivalent to the threshold voltage of the first FET, which is a load, is applied. A bias circuit that outputs a voltage and whose bias voltage does not change much even when the power supply voltage changes is provided, and the output of this bias circuit is applied to the gate of the first FET. Therefore, even when the power supply voltage is small, a sufficiently high-speed operation is possible, and even when the power supply voltage is large, the fluctuation of the gate bias voltage of the first FET is small, so that the DC current is prevented from increasing more than necessary. It is possible to provide a logic circuit that can be prevented and that has high speed and low power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a CMOS ratio NOR circuit according to the first embodiment of the present invention, FIG. 2 is a graph showing current characteristics of a P-channel MOSFET when a gate and a drain are connected, and FIG. FIG. 4 is a graph showing the bias voltage characteristic with respect to the power supply voltage of the bias circuit in the embodiment, and FIG.
5 is a circuit diagram of a CMOS ratio NOR circuit according to the embodiment of the present invention, FIG. 5 is a circuit diagram of a conventional CMOS ratioless NOR circuit, FIG. 6 is a circuit diagram of a conventional CMOS ratio NOR circuit, and FIG. 7 is a conventional CMOS ratioless NAND circuit. Circuit diagram of the circuit, Figure 8 shows the conventional CMOS ratio
It is a circuit diagram of a NAND circuit. 1,2; Bias circuit, MP ₁ , MP ₂ , MP ₃ , MP _{11 to} MP _1n , MP _{31 to} MP
_3n ; P-channel MOSFET, MN _{11 to} MN _1n , MN ₂ , MN _{21 to} MN _2n ; N-channel MOSFET, S _{1 to} S _n ; Input signal, S _O ; Output signal, R ₁ , R ₂ ,
R ₃ , R ₄ ; Resistance

Claims (1)

(57) [Claims] 1. A load composed of a first FET of a first conductivity type connected between a first power supply and an output end, and a load connected in parallel between the output end and a second power supply, respectively. A driver including a plurality of second FETs of the second conductivity type for inputting an input signal to the gate of the first FET, and a bias circuit for applying a gate bias voltage to the gate of the first FET. A resistor connected between the bias output terminal and the second power source, and a resistor connected between the bias output terminal and the first power source, the feedback signal being input to the resistor, and 1st with different threshold from 1st FET
A conductive type third FET, wherein the resistance value of the resistor is set to 1/2000 to 1/5 of the resistance value when the gate of the third FET is biased to the threshold value, The threshold value of the third FET is set to a value at which the voltage of the bias output terminal becomes a voltage equivalent to the threshold voltage of the third FET when the lower limit value of the operating power supply voltage range is given as the power supply voltage. A logic circuit characterized by being set.