JP2012119941A - Inverting voltage output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for outputting a voltage inverting between a non-ground voltage and a ground voltage of a DC power supply in response to changes in an input signal which suppresses voltage fluctuations on a power line connected to a non-ground terminal.SOLUTION: A current limiting element 14 and a switching circuit 16 are connected in series, and a voltage at a midpoint 22 between the current limiting element and the switching circuit is output. A current flowing through the switching circuit when the switching circuit is turned on is limited by the current limiting element. Voltage fluctuations on a power line 12 connected to the non-ground terminal of the DC power supply are suppressed and the operation of an analog circuit or the like connected to the power line 12 is stabilized.

Description

  The present invention relates to a circuit that outputs a voltage that is inverted between a ground voltage and a non-ground voltage of a DC power supply in accordance with a change in an input signal. The present invention also relates to a clock signal output circuit using the inverted voltage output circuit. Further, the present invention relates to an analog circuit using the clock signal output circuit and an analog / digital mixed circuit.

As shown in FIG. 1A, a cMOS logic circuit 1 that outputs an inverted voltage in accordance with a change in an input signal is known. In this circuit 1, a series circuit of a pMOS transistor 4 and an nMOS transistor 6 is connected to a DC power supply 2. The pMOS transistor 4 is connected to the non-ground terminal 2 a of the DC power supply 2, and the nMOS transistor 6 is connected to the ground terminal 2 b of the DC power supply 2. The potential of the non-ground terminal 2a (non-ground voltage V _DD ) is positive with respect to the potential of the ground terminal 2b (ground voltage).

As shown in FIG. 1B, the high voltage higher than the threshold voltage of the pMOS transistor 4 and the nMOS transistor 6 and the low voltage lower than the threshold are applied to the gates of the pMOS transistor 4 and the nMOS transistor 6 over time. When the gate voltage V _G that is inverted between the voltages is applied, the pMOS transistor 4 is in a non-conductive state and the nMOS transistor 6 is in a conductive state while the gate voltage V _G is at a high voltage. V _OUT is equal to the ground voltage of the DC power supply 2. Since the pMOS transistor 4 is conductive and the nMOS transistor 6 is nonconductive while the gate voltage V _G is low, the voltage V _OUT output to the terminal 10 is equal to the non-ground voltage V _DD of the DC power supply 2. Will be equal. As shown in FIG. 1C, the voltage V _OUT output from the terminal 10 is inverted between the ground voltage of the DC power supply 2 and the non-ground voltage V _DD according to the change of the input signal. When the gate voltage V _G is inverted between the ground voltage of the DC power supply 2 and the non-ground voltage V _DD , the cMOS logic circuit of FIG. 1 becomes a NOT circuit. The cMOS logic circuit in FIG. 1 is one application example of the cMOS logic circuit, and the application example is not limited to the NOT circuit. Various inverted voltage output circuits that output a voltage that is inverted between the ground voltage and the non-ground voltage of the DC power supply according to the change of the input signal are configured.

When the inverted voltage output circuit is configured by the cMOS logic circuit, there is a time zone in which both the pMOS transistor 4 and the nMOS transistor 6 are conductive when the gate voltage V _G is inverted between the high voltage and the low voltage, and a large through current is generated. A time zone will flow.
Reference numeral 8 in the figure denotes a power supply terminal (non-grounded side) for supplying the non-grounded voltage of the DC power supply 2 to another electric circuit. The non-ground voltage Vs generated at the power supply terminal 8 is affected by a through current that flows repeatedly only for a short time, and fluctuates as illustrated in FIG. The non-ground voltage Vs generated at the power supply terminal 8 is obtained by superimposing noise on the power supply voltage V _DD . Since noise is superimposed, the operation of the electric circuit connected to the power supply terminal 8 becomes unstable. When an analog circuit or an analog / digital mixed circuit is connected to the power supply terminal 8, fluctuation (noise) occurs in the voltage of the power line 12, so that the output result of the analog circuit or analog / digital mixed circuit is affected by noise. Will appear. In particular, when the inverted voltage output circuit, analog circuit, etc. and the power supply circuit that supplies power to them are integrated, the output impedance of the power supply circuit is not zero, so fluctuations in the power supply voltage (noise) may occur in the analog circuit, etc. It will have a noticeable effect.
In this specification, the wiring connecting the non-ground terminal 2a of the DC power source 2 and the non-ground side power terminal 8 is referred to as a power line 12, the non-ground side power terminal 8 is abbreviated as the power terminal 8, and the power line 12 Or the voltage of the power supply terminal 8 is called a power supply voltage or a non-ground voltage. On the other hand, the wiring connected to the ground terminal 2b of the DC power supply 2 is referred to as a ground line 13, and the voltage is referred to as a ground voltage.

  In order to prevent a through current from flowing, the technique of Patent Document 1 has been proposed. In the technique of Patent Document 1, a relationship is used in which the delay circuit is used, the pMOS transistor 4 is turned on after the nMOS transistor 6 is turned off, and the nMOS transistor 6 is turned on after the pMOS transistor 4 is turned off. obtain. According to this technique, the time zone in which both the pMOS transistor 4 and the nMOS transistor 6 are conductive can be eliminated, and the through current can be prevented from flowing.

JP-A-5-145385

An inverted voltage output circuit that outputs a voltage that is inverted between the ground voltage and non-ground voltage of a DC power supply is often combined to form a clock signal generation circuit or a logic circuit, and is one of the inverted voltage output circuits. If one delay circuit is provided, the circuit group for outputting the inversion voltage becomes large.
The present specification discloses an inverted voltage output circuit that can significantly reduce the influence of a through current without increasing the circuit scale.

  In the present specification, the idea of realizing a circuit in which no through current flows is changed to a circuit in which a through current flows, thereby succeeding in significantly reducing the influence of the inverted voltage output circuit on the power supply voltage.

  The inverted voltage output circuit disclosed in this specification is used by being connected to a DC power source. In the inverted voltage output circuit, the current limiting element and the switching circuit are connected in series, and the voltage at the midpoint between the current limiting element and the switching circuit is output.

  In the above inverted voltage output circuit, when the switching circuit switches between conducting and non-conducting according to the change of the input signal, the voltage at the midpoint between the current limiting element and the switching circuit follows the DC power supply ground. Inverts between voltage and ungrounded voltage. While the switching circuit is conductive, a current flows through the switching circuit, but the current value is limited by the current limiting element. The through current value flowing through the switching circuit is suppressed to be small. A through current flowing through the inverted voltage output circuit does not become excessive, and a phenomenon in which an excessive through current flows and affects the power supply voltage can be reduced.

Since the above inverted voltage output circuit is not provided with a switching element which is paired with the switching circuit and which is non-conductive when the switching circuit is conductive, a current flows through the switching circuit while the switching circuit is conductive. to continue. There is a problem of large current consumption.
However, according to the study by the present inventors, the problem that the current continues to flow in the switching circuit while the switching circuit is conducting can be suppressed to an acceptable level by limiting the current value by the current limiting element. It has been found that the benefits obtained by being able to suppress the effect of large through currents on the supply voltage may have more significance. Depending on the application of the inverting voltage output circuit, using a current limiting element instead of the switching element paired with the switching circuit has the disadvantage that the power consumption increases, and the power line voltage is stable. We have found that the advantage of not generating noise in the line is of greater value. The above inverted voltage output circuit has been realized by obtaining the above knowledge.

  When the negative terminal of the DC power supply is grounded, a pMOS transistor can be connected to the positive terminal (non-ground terminal) to form a current limiting element. When a constant voltage is applied to the gate of the pMOS transistor, the upper limit value of the current flowing through the pMOS transistor is limited to the saturation current. The magnitude of the saturation current is not affected by the drain-source voltage and is defined by the gate voltage. When a pMOS transistor having a constant voltage applied to the gate is used, the through current is limited and an excessive through current is prevented from flowing. In this inverted voltage output circuit, one or a plurality of nMOS transistors constitute a switching circuit. This switching circuit is used while being grounded. The voltage at the midpoint between the pMOS transistor and the switching circuit is inverted between a state approximately equal to the non-ground voltage and a state approximately equal to the ground voltage.

The switching circuit may be composed of one nMOS transistor, and a signal that is inverted between a high voltage and a low voltage may be applied to the gate of the nMOS transistor.
According to the above circuit, while the switching circuit composed of nMOS transistors is non-conductive, the non-ground voltage of the DC power supply is generated at an intermediate point, and while the switching circuit composed of nMOS transistors is conductive, The ground voltage of the DC power supply is generated at the intermediate point. A voltage that is inverted between the non-ground voltage and the ground voltage is output. According to the above circuit, a circuit that outputs a voltage obtained by inverting the input signal is configured. Note that the inverted voltage output circuit in this specification is not limited to a circuit that outputs a voltage obtained by inverting an input signal, but means a circuit that outputs a voltage that is inverted over time. A circuit that outputs a high voltage if the input signal is a high voltage and outputs a low voltage if the input signal is a low voltage is not a circuit that outputs a voltage obtained by inverting the input signal. Since the inversion voltage is output, it is included in the inversion voltage output circuit here.
Since the current flows through the series circuit of the pMOS transistor and the nMOS transistor while the nMOS transistor is conducting, the voltage generated at the intermediate point does not coincide with the ground voltage. A voltage that deviates from the ground voltage by a value obtained by multiplying the current flowing through the nMOS transistor by the resistance of the nMOS transistor during conduction. However, the deviation can be limited to a small value by limiting the current value flowing through the nMOS transistor by the pMOS transistor. The expression that the ground voltage is output includes a case where a voltage slightly deviated from the ground voltage (which can be sufficiently distinguished from the non-ground voltage) is output.

  The above inverted voltage output circuit can be used for a logic circuit, but is useful for a clock signal output circuit. In particular, it is useful when configuring a clock signal output circuit that is used by being connected to the same power supply circuit together with an analog circuit that uses a clock signal for processing. When the analog circuit and the clock signal output circuit are connected to the same power supply circuit, it is particularly necessary to suppress the fluctuation of the power supply line voltage due to the operation of the clock signal output circuit. The present invention often compensates for the disadvantage of increasing the current consumption and can enjoy the extra effect.

A clock signal output circuit can be configured by connecting a series circuit of a pMOS transistor and an nMOS transistor in parallel over a plurality of stages. In this case, the current flowing through the pMOS transistor is limited to the saturation current by applying a constant voltage to the gate of the pMOS transistor. In addition, the intermediate point in the previous stage is connected to the gate of the nMOS transistor in the subsequent stage, and the intermediate point in the final stage is connected to the gate of the nMOS transistor in the first stage.
As a result, a ring oscillator type clock signal output circuit or a clock signal output circuit using a CR oscillation circuit can be configured.
When configuring a ring oscillator type clock signal output circuit, the intermediate point of the previous stage is connected to the gate and capacitor of the nMOS transistor of the subsequent stage, and the intermediate point of the final stage is connected to the gate and capacitor of the first stage nMOS transistor. A connected configuration is assumed. Then, a gate voltage that repeatedly changes from a low voltage to a high voltage and then returns to the low voltage is applied to the gate of the nMOS transistor at each stage.
In this case, when the preceding nMOS transistor becomes non-conductive, the latter capacitor starts charging, and when the charging voltage rises to a predetermined value, the succeeding nMOS transistor becomes conductive, and the succeeding nMOS transistor becomes conductive. As a result, the capacitor in the subsequent stage is discharged and the nMOS transistor in the subsequent stage becomes non-conductive. Since a phenomenon in which the above chain of phenomena is autonomously repeated is obtained, a circuit that outputs a voltage that is inverted at a predetermined frequency, that is, a clock signal output circuit can be obtained.

  Various accessory circuits can be provided in the clock signal output circuit. For example, a frequency dividing circuit mainly including a flip-flop circuit can be provided. The frequency dividing circuit is also preferably configured by combining an inverted voltage output circuit in which a current limiting element and a switching circuit are connected in series. The entire circuit of the clock signal output circuit and the frequency dividing circuit can be considered as a substantial clock signal output circuit. When a frequency dividing circuit is configured by combining an inverted voltage output circuit in which a current limiting element and a switching circuit are connected in series, it is possible to suppress fluctuations in the power supply voltage due to a substantial clock signal output circuit.

  The clock signal output circuit described above is particularly effective when used with an analog circuit that operates in synchronization with the clock signal and is connected to the same power source as the clock signal output circuit. In this case, if the clock signal output circuit causes fluctuations in the power supply voltage, the operation of the analog circuit becomes unstable. By utilizing the present invention, the clock signal output circuit does not generate a large noise in the power supply line, so that the operation of the analog circuit is stabilized. It is possible to prevent the power line voltage noise from affecting the analog circuit.

  A combination of the above clock signal output circuit and an analog / digital mixed circuit that operates in synchronization with the clock signal output from the clock signal output circuit and is connected to the same power source as the clock signal output circuit is also effective. . In this case, it is more effective to provide a time difference between the execution timing of the analog / digital conversion processing and the execution timing of the digital processing. According to the clock signal output circuit described above, fluctuations in the power supply line voltage of the analog / digital conversion circuit due to the operation of the clock signal output circuit can be suppressed. Further, by shifting the execution timing of the analog / digital conversion processing from the execution timing of the digital processing, it is possible to prevent the fluctuation of the power supply line voltage caused by the digital processing from affecting the analog / digital conversion processing.

  According to the technology disclosed in this specification, voltage fluctuations that occur in the power supply line connected to the inverted voltage output circuit can be suppressed without increasing the circuit scale of the inverted voltage output circuit. When an analog circuit or an analog / digital mixed circuit is connected to the same power line, the operation of the analog circuit or the analog / digital mixed circuit can be prevented from becoming unstable due to fluctuations in the power supply voltage. Alternatively, noise can be prevented from affecting the output of the analog circuit or analog / digital circuit. There are many opportunities to enjoy the extra benefits to compensate for the disadvantage of increased power consumption.

(A) shows the conventional inversion voltage output circuit comprised by the cMOS logic circuit, (b)-(d) shows the timing chart explaining the operation | movement. (A) shows the inversion voltage output circuit of Example 1, (b)-(e) shows the timing chart explaining the operation | movement. The measurement result of a power supply voltage is shown. (A) shows the inversion voltage output circuit of Example 2, (b)-(e) shows the timing chart explaining the operation | movement. Example 1 of a clock signal output circuit will be described. 6 is a timing chart illustrating the operation of FIG. Example 2 of the clock signal output circuit will be described. 8 is a timing chart for explaining the operation of the circuit of FIG. The circuit of the Example which implement | achieves a NOT circuit. The circuit of the Example which implement | achieves 2 input NAND circuit. The circuit of the Example which implement | achieves 3 input NAND circuit. The circuit of the Example which implement | achieves T type FF (TFF1). The circuit of the Example which implement | achieves 2 input NOR circuit. The circuit of the Example which implement | achieves 3 input NOR circuit. The circuit of the Example which implement | achieves T type FF (TFF2). The circuit in which the clock signal output circuit of the embodiment and the analog circuit are mixed is shown. The circuit in which the clock signal output circuit of the embodiment and the analog / digital mixed circuit are mixed is shown. 18 is a timing chart for explaining the operation of the circuit of FIG.

The main features of the embodiments described below are exemplified below.
(Feature 1) When the negative terminal of the DC power supply is grounded, a pMOS transistor is used as the current limiting element. A constant voltage is applied to the gate of the pMOS transistor. A pMOS transistor in which a constant voltage is applied to the gate does not pass a current equal to or higher than the saturation current defined by the gate voltage even if the drain-source voltage rises. That is, it is limited to the saturation current or less.
(Feature 1-2) The switching circuit connected in series with the current limiting element is composed of an nMOS transistor.
(Feature 1-3) A pMOS transistor is connected between the positive potential power line and the inverted voltage output terminal, and a switching circuit is connected between the inverted voltage output terminal and the ground line. (Feature 2) When the positive terminal of the DC power supply is grounded, an nMOS transistor is used as the current limiting element. A constant voltage is applied to the gate of the nMOS transistor. An nMOS transistor in which a constant voltage is applied to the gate does not pass a current equal to or higher than the saturation current defined by the gate voltage even if the drain-source voltage rises. That is, it is limited to the saturation current or less.
(Feature 2-2) The switching circuit connected in series with the current limiting element is composed of a pMOS transistor.
(Feature 2-3) An nMOS transistor is connected between the negative potential power line and the inverted voltage output terminal, and a switching circuit is connected between the inverted voltage output terminal and the ground line.
(Feature 3) The switching circuit connected in series with the current limiting element constitutes a logic circuit.
(Feature 4) A clock signal output circuit is realized by using a combination in which the output of the preceding inverted voltage output circuit is used as the input of the succeeding inverted voltage output circuit.
(Feature 4-1) A clock signal output circuit using a CR oscillation circuit is realized.
(Feature 4-2) A clock signal output circuit using a ring oscillator circuit is realized.
(Feature 4-3) When a clock signal output circuit is configured with a cMOS logic circuit, a value obtained by integrating a through current repeatedly flowing in synchronization with a clock signal over a unit time and an inverted voltage output circuit using a current limiting element The value obtained by integrating the current flowing over the unit time when the clock signal output circuit is configured in the same order is the same order, and an increase in power consumption due to not using an element that prohibits the flow of current can be ignored.
(Feature 5) The analog / digital mixed circuit includes an analog / digital conversion circuit and a digital processing circuit. The digital processing circuit is composed of a cMOS logic circuit, and fluctuates the power supply line voltage due to the through current. Since the execution timings of the analog / digital conversion process and the digital process are shifted, the power supply line voltage during the analog / digital conversion process does not vary depending on the digital processing circuit.

(Example 1 of an inverted voltage output circuit)
The inversion voltage output circuit 11 shown in FIG. 2 is used by being connected to the DC power supply 2 and includes a series circuit of a pMOS transistor 14 and a switching circuit 16. The voltage at the intermediate point 22 between the pMOS transistor 14 and the switching circuit 16 is output to the output terminal 10. The pMOS transistor 14 is connected to the power supply line 12 of the DC power supply 2, and the switching circuit 16 is connected to the ground line 13 of the DC power supply 2. In this embodiment, the non-ground voltage V _DD of the DC power supply 2 is a positive voltage with respect to the ground voltage.
The voltage at the output terminal 10 is inverted between the non-ground voltage V _DD of the DC power supply 2 and the ground voltage. The power supply line 12 of the DC power supply 2 supplies a positive voltage from the power supply terminal 8 to another electric circuit. The positive voltage of the power supply terminal 8 needs to be stable and is preferably not affected by noise.

The switching circuit 16 receives n input signals IN _{1 to} IN _n and switches between conduction and non-conduction between the intermediate point 22 and the ground line 13 in accordance with the input signals. The number n of input signals can be any number greater than or equal to one. The switching circuit 16 is composed of one or a plurality of nMOS transistors.
The voltage of the output terminal 10 is inverted between the non-ground voltage V _DD of the DC power supply 2 and the ground voltage in response to the switching circuit 16 switching between conduction and non-conduction between the intermediate point 22 and the ground line 13. While the switching circuit 16 is conducting between the intermediate point 22 and the ground line 13, a current flows through the series circuit of the pMOS transistor 14 and the switching circuit 16. If this current value is large, the potential of the power supply terminal 8 becomes unstable. If the value of the current flowing through the series circuit is kept small, the potential of the power supply terminal 8 can be prevented from becoming unstable, and noise superimposed on the power supply line 12 can be reduced. In this embodiment, since the current value flowing through the series circuit of the pMOS transistor 14 is limited to the saturation current value or less, the current flowing through the series circuit does not become excessive, and the potential of the power supply terminal 8 becomes unstable. Can be prevented, and noise superimposed on the power supply line 12 can be reduced.

The constant voltage V _G1 (shown in FIG. 2B) applied to the gate of the pMOS transistor 14 is adjusted to a voltage that limits the current flowing through the pMOS transistor 14 to be equal to or less than the allowable current value. As a result, the current value flowing between the source and drain of the pMOS transistor 14 is limited to the allowable current value or less, and no more current flows.

  FIGS. 2C to 2E show the behavior when the switching circuit 16 is composed of one nMOS transistor. As will be described later with reference to FIG. 9, when the switching circuit 16 is constituted by one nMOS transistor, a NOT circuit is constituted by a series circuit of a pMOS transistor and an nMOS transistor.

FIG. 2C shows an input signal to the switching circuit 16 composed of one nMOS transistor. As shown in FIG. 2 (d), while the input voltage IN ₁ (in this case, 1 input, IN ₂ etc. is not used) is a low voltage, the switching circuit 16 composed of an nMOS transistor is in a non-conductive state, and the output The voltage at the terminal 10 becomes the non-ground voltage of the DC power supply 2. While the input voltage IN ₁ is at a high voltage, the switching circuit 16 composed of an nMOS transistor becomes conductive, and the voltage at the output terminal 10 becomes equal to the ground voltage of the DC power supply 2. Here, the low voltage means a voltage lower than the threshold voltage of the nMOS transistor, and the high voltage means a voltage higher than the threshold voltage of the nMOS transistor. The high voltage may be the non-ground voltage V _DD of the DC power supply 2. To be precise, the voltage at the output terminal 10 while the switching circuit 16 is conducting is:
The voltage is obtained by adding the voltage drop of the nMOS transistor constituting the switching circuit 16 to the ground voltage of the DC power supply 2, but the current value flowing through the switching circuit 16 is suppressed to a small value by the pMOS transistor 14. The voltage drop of the nMOS transistor that constitutes is small. The voltage of the output terminal 10 when the switching circuit 16 is conductive is substantially equal to the ground voltage of the DC power supply 2. The voltage of the output terminal 10 in synchronization with the input voltage IN ₁ inverted, reversed between the positive voltage and zero voltage of the DC power supply 2. When comparing the input voltage IN ₁ and the output voltage, if the former is low voltage latter is high voltage, the latter has a low voltage if the former is high voltage. Circuit 11 has a NOT circuit for outputting a voltage obtained by inverting the input voltage IN _1.

  In the case of the circuit of FIG. 2, the through current flowing through the series circuit of the pMOS transistor 14 and the switching circuit 16 cannot be made zero when the switching circuit 16 is conductive. Therefore, power consumption is expected to increase as compared with an inverted voltage output circuit using a cMOS logic circuit. On the other hand, the through current can be suppressed by the current limiting function of the pMOS transistor 14.

In the case of a conventional inversion voltage output circuit using a cMOS logic circuit, a large through current flows even for a short time, so that a large noise is generated at the power supply terminal 8 in synchronization with the inversion of the voltage at the output terminal 10 ( (Refer FIG.1 (d)). On the other hand, in the case of FIG. 2, although the through current cannot be prohibited, the magnitude of the through current is small, and therefore the magnitude of noise generated at the power supply terminal 8 in synchronization with the inversion of the voltage at the output terminal 10. Can be suppressed to a low level (see FIG. 2E).
Figure 3 shows the actual measurement result of the supply voltage V _S generated in the power supply terminal 8, (a) shows the case of using the cMOS logic circuits, as by (b) the circuit of FIG. 2 Show. According to the circuit of FIG. 2, it is confirmed that the influence of noise generated on the power supply voltage can be suppressed low.

(Example 2 of inverted voltage output circuit)
FIG. 4 shows an inverted voltage output circuit 21 used when the positive terminal 2 a of the DC power supply 2 is grounded and a negative voltage is applied to the power supply line 12. In this case, a series circuit of a switching circuit 26 constituted by a pMOS transistor and a current limiting element 24 constituted by an nMOS transistor is provided, and a voltage at an intermediate point between the switching circuit 26 and the current limiting element 24 is obtained. Output to the output terminal 10. Switching circuit 26 is connected to ground line 13, and current limiting element 24 is connected to power supply line 12. The power supply voltage is negative with respect to the ground voltage.
The constant voltage V _G2 (shown in FIG. 4B) applied to the gate of the nMOS transistor that constitutes the current limiting element 24 is adjusted to a voltage that limits the current flowing through the nMOS transistor 24 to be equal to or less than the allowable current value. The value of the current flowing between the source and drain of the nMOS transistor 24 is limited to the allowable current value of the series circuit or less, and no more current flows.
FIGS. 4C to 4E show the behavior when the switching circuit 26 is configured by one pMOS transistor. FIG. 4C shows an input signal to the switching circuit 26 composed of one pMOS transistor. As shown in FIG. 4D, the input voltage IN ₂ (in this case, one input is used, and IN ₁ etc. is not used) is a low voltage (in this case, a negative voltage) from the absolute value of the threshold voltage of the pMOS transistor. The voltage having a small absolute value), the switching circuit 26 made of a pMOS transistor becomes conductive, and the voltage at the output terminal 10 becomes the ground voltage. Between the input voltage IN ₂ is at high voltage (negative voltage having a larger absolute value than the absolute value of the threshold voltage of the pMOS transistor where a negative voltage), the switching circuit 26 includes a pMOS transistor becomes nonconductive, an output terminal The voltage of 10 is equal to the negative voltage of the DC power supply 2.
According to the inverted voltage output circuit 21 of FIG. 4, the value of the current flowing through the series circuit of the switching circuit 26 made of a pMOS transistor and the current limiting element 24 made of an nMOS transistor is limited to the saturation current of the nMOS transistor, and an excessive through current is connected in series. The circuit can be prevented from flowing, the potential of the power supply terminal 8 can be prevented from becoming unstable, and noise superimposed on the power supply line 12 can be reduced.

(Embodiment 1 of clock signal output circuit)
5 connects three of the series circuits of FIG. 2 in parallel, and connects the intermediate point M1 of the first stage to the gate of the switching element D2 of the second stage and the capacitor C2 of the second stage. Is connected to the gate of the third-stage switching element D3 and the third-stage capacitor C3, and the third-stage intermediate point M3 is connected to the gate of the first-stage switching element D1 and the first-stage capacitor C1. 1 shows a circuit configured to output a clock signal when connected. U1, U2 and U3 in the figure are pMOS transistors constituting a current limiting element, and the constant voltage V _G1 described with reference to FIG. 2B is applied to each gate. Each of U1, U2, and U3 functions as a current limiting element. D1, D2, and D3 are nMOS transistors that function as switching elements that are turned on when the gate voltage becomes high and non-conductive when the gate voltage becomes low.

The circuit of FIG. 5 is well known as a ring oscillator circuit, and the process of oscillating at a constant period is well known. Therefore, only a brief explanation will be given. The description starts from the timing at which the voltage of the capacitor C1 rises and the transistor D1 becomes conductive (t1 in FIG. 6).
1) When the transistor D1 is turned on, the capacitor C2 is discharged, and the transistor D2 is turned off (timing t1).
2) When the transistor D2 becomes non-conductive, the capacitor C3 starts to be charged (timing t1).
3) When the voltage of the capacitor C3 rises and reaches the threshold voltage, the transistor D3 becomes conductive (timing t2).
4) When the transistor D3 is turned on, the capacitor C1 is discharged, and the transistor D1 is turned off (timing t2).
5) When the transistor D1 becomes non-conductive, the capacitor C2 starts to be charged (timing t2).
6) When the voltage of the capacitor C2 rises and reaches the threshold voltage, the transistor D2 becomes conductive (timing t3).
4) When the transistor D2 is turned on, the capacitor C3 is discharged, and the transistor D3 is turned off (timing t3).
5) When the transistor D3 becomes non-conductive, the capacitor C1 starts to be charged (timing t3).
6) When the voltage of the capacitor C1 rises and reaches the threshold voltage, the transistor D1 becomes conductive (returns to timing t1).
As described above, the initial state is restored, and the above cycle is repeated.
As a result, a cycle of “transistor D1 conducting (timing t1) → transistor D3 conducting (timing t2) → transistor D2 conducting (timing t3) → transistor D1 conducting (timing t1)” is repeated. The number of cycles is determined by the capacitances of the capacitors C1, C2, and C3.

The voltage of the capacitor C1 is input to an inverted voltage output circuit configured by a series circuit of a pMOS transistor U4 that constitutes a current limiting element and an nMOS transistor D4 that functions as a switching element. The voltage of the capacitor C1 is applied to the gate of the nMOS transistor D4. As described with reference to FIG. 2, the series circuit of the pMOS transistor U4 and the nMOS transistor D4 outputs a voltage obtained by inverting the input voltage. That is, while the voltage of the capacitor C1 is equal to or higher than the threshold voltage of the nMOS transistor D4, the nMOS transistor D4 becomes conductive and the voltage of the clock terminal (CLK1) becomes the ground voltage. While the voltage of the capacitor C1 is lower than the threshold voltage of the nMOS transistor D4, the nMOS transistor D4 becomes nonconductive and the voltage of the clock terminal (CLK1) becomes a positive voltage. The clock signal shown in FIG. 6D is output to the clock terminal (CLK1). The clock signal CLK1 becomes a ground voltage when the charging voltage of the capacitor C1 exceeds the threshold voltage of the nMOS transistor D4 (timing t1), and becomes a positive voltage when the transistor D3 is turned on and the capacitor C1 is discharged (timing t2). Invert. The clock signal CLK1 has a ground voltage period and a positive voltage period of 1: 2.
The voltage at the clock terminal (CLK1) is input to the frequency divider circuit. The frequency divider circuit 42 is a flip-flop circuit described later with reference to FIG. 12, and inverts the clock signal CLK2 in synchronization with the timing at which the clock signal CLK1 switches from the ground voltage to the positive voltage. As a result, the clock signal CLK2 has a period of 3: 3 as a ground voltage and a period of a positive voltage. The clock signal CLK2 is a clock signal with a duty ratio of 50% that is inverted at a predetermined cycle.
As will be described later with reference to FIG. 12, the flip-flop circuit 42 is composed of an inverted voltage output circuit composed of a series circuit of a current limiting element and a switching circuit, and the current flowing through the series circuit is a current limiting element. Limited by. The entire circuit including the inverting circuit composed of the pMOS transistor U4 and the nMOS transistor D4 and the frequency dividing circuit (flip-flop circuit) 42 (which can be called a substantial clock output circuit) is composed of the current limiting element and the switching circuit. The circuit includes an inverted voltage output circuit configured by a series circuit, and a current flowing through the series circuit is limited by a current limiting element. The voltage fluctuation generated at the power supply terminal 8 is small, and noise hardly occurs on the power supply line 12.

(Embodiment 2 of clock signal output circuit)
FIG. 7 shows a second embodiment in which a clock signal output circuit is constituted by an inverted voltage output circuit comprising a series circuit of a current limiting element and a switching circuit. The circuit of FIG. 7 outputs a clock signal having a predetermined frequency by utilizing a phenomenon that a capacitor of the CR circuit is charged and discharged. (1) in FIG. 8 shows the clock signal CLK1 output from the circuit in FIG. 7, (2) shows the current value flowing through the DC power supply 2 , and (3) shows the voltage change of the power supply terminal 8. . Since the current limiting elements U1, U2, U3, U4 are used, the noise level generated in the power supply line 12 can be kept low. If the series circuit of U and D shown in FIG. 7 is configured with a cMOS logic circuit, a large amount of noise is duplicated on the power supply line 12.

  5 and 7, a clock signal output circuit is constituted by a series circuit of a current limiting element and a switching element. Digital logic management can be configured by the series circuit. FIG. 9 illustrates a case where an inverting circuit is realized (explained that a voltage OUT obtained by inverting the input voltage IN is output with reference to FIG. 5), and FIG. 10 illustrates a case where a 2-input NAND circuit is realized. 11 shows a case where a 3-input NAND circuit is realized, FIG. 12 shows a case where a T-type FF (TFF1) is realized, FIG. 13 shows a case where a 2-input NOR circuit is realized, and FIG. When the circuit is realized, FIG. 15 shows a case where a T-type FF (TFF2) is realized. In any case, since a current limiting element is inserted in series with the switching circuit, an excessive through current does not flow when the switching circuit is inverted, and a large noise is not generated in the power supply line. In order to operate the circuit normally until the power supply voltage drops, that is, to reduce the operating voltage range of the circuit, it is effective to configure a logic circuit by combining NOR type circuits.

(Clock signal output circuit and analog circuit with common power line)
FIG. 16 shows a circuit in which the clock signal output circuit 40 and the analog circuit 62 in FIG. 5 are mixed. The clock signal output circuit 40 and the analog circuit 62 are connected to a common power line 64.
Reference numeral 63 in the figure denotes a power supply circuit that outputs a voltage V _DD . In the figure, reference numeral 40 denotes the clock signal output circuit shown in FIG. 5, which outputs the clock signal CLK2. In the figure, reference numeral 66 denotes a detection element, and reference numeral 65 in the figure denotes a drive circuit that applies a drive voltage to the detection element 66. The detection element 66 changes the resistance value according to the state of the detection target. The detection element 66 outputs a voltage, and the output voltage is amplified by the amplifier circuit 67. The amplifier circuit 67 is a chopper amplifier that amplifies using the clock signal CLK2. In the figure, reference numeral 68 denotes a circuit for removing ripples from the voltage amplified by the chopper amplifier 67 (the ripple corresponding to the clock signal CLK2 is superimposed). Output to _OUT . The analog circuit 62 including the drive circuit 65, the detection element 66, the amplifier circuit 67, the ripple removal circuit 68, and the like uses the power supply line 64 that is common to the clock signal output circuit 40, and the clock signal output circuit 40 outputs it. Operates in synchronization with the clock signal CLK2.
As shown in FIG. 3, when the clock signal output circuit 40 is configured by a cMOS logic circuit, a large voltage fluctuation (noise) occurs in the power supply line 64, so that noise is output to the output voltage _VOUT via the analog circuit 62. The effect appears. In this embodiment, the clock signal output circuit 40 is configured by a circuit using a current limiting element, and the fluctuation of the power supply voltage of the power supply line 64 is small. Noise does not affect the output voltage _VOUT of the analog circuit 62.

(Clock signal output circuit with common power line and analog / digital mixed circuit)
FIG. 17 shows a circuit in which the clock signal output circuit 40 and the analog / digital mixed circuit 72 of FIG. 5 are mixed. Reference numeral 63 in the figure denotes a power supply circuit that outputs a voltage V _DD . In the figure, reference numeral 40 denotes a clock signal output circuit, which outputs clock signals CLK3, CLK4, and CLK5 generated from the clock signal. The relationship between the clock signals CLK3, CLK4, and CLK5 is shown in FIG. In the figure, reference numeral 76 denotes a detection element, and reference numeral 75 in the figure denotes a drive circuit that applies a drive voltage to the detection element 76. A clock signal CLK3 is input to the drive circuit 75, and a pulse voltage is applied to the detection element 76 in synchronization with the inversion cycle of the clock signal CLK3. The detection element 76 is, for example, an electrostatic capacitance type, and changes to a stable voltage after inputting a pulse voltage. The stable voltage value corresponds to the observed quantity. The amplifier circuit 77 amplifies the voltage output from the detection element 76.

  In the figure, reference numeral 78 denotes an A / D conversion circuit that converts the analog amplification voltage VA output from the amplification circuit 77 into a digital value, and includes a counter circuit. At the timing when the clock signal CLK4 changes from the high voltage to the low voltage, if the value obtained by converting the counter value of the counter circuit to the analog voltage is larger than the analog amplified voltage VA, the counter value is decreased, and the counter value of the counter circuit is changed to the analog voltage. If the converted value is smaller than the analog amplified voltage VA, the counter value is increased. By repeating this operation, the value obtained by converting the counter value of the counter circuit into an analog voltage matches the analog amplified voltage VA. The analog amplified voltage VA is converted into a counter value.

  Reference numeral 79 in the figure denotes a digital signal processing circuit, which includes a large number of cMOS logic circuits. The digital signal processing circuit 79 includes a large number of logic circuits, and is configured with a cMOS logic circuit instead of the circuit of FIG. 2 because it is necessary to reduce power consumption. As a result, when the digital signal processing circuit 79 is activated, a through current flows during switching, the voltage of the power line 74 fluctuates, noise is generated in the power line of the analog / digital mixed circuit 72, and the A / D conversion circuit 78 is driven. Noise is added to the input analog voltage.

The digital signal processing circuit 79 starts the processing when the clock signal CLK5 is inverted from the low voltage to the high voltage, and ends the processing until the clock signal CLK5 is maintained at the high voltage. Reference numeral 81 in FIG. 18 schematically shows noise generated by the influence of the through current that flows when the cMOS logic circuit constituting the digital signal processing circuit 79 is inverted.
Obviously, at the timing T when the digital value is converted by the A / D conversion circuit 78, the digital signal processing circuit 79 does not add noise to the output voltage of the detection element 76 and the amplified voltage VA by the amplifier circuit 77, and the A / D The power supply voltage does not fluctuate while the conversion circuit 78 operates. Since the timing T for conversion to a digital value by the A / D conversion circuit 78 and the period during which the digital signal processing circuit 79 operates are separated, the digital processing circuit 79 in the analog / digital mixed circuit 72 of FIG. The fluctuation of the power supply voltage caused by the operation of the built-in cMOS logic circuit does not adversely affect the measurement.

  If the clock signal output circuit 40 is composed of a cMOS logic circuit, the power supply voltage fluctuates at the inversion timing of the clock signal CLK2. Even if the timing T in which the A / D conversion circuit 78 converts the digital value and the period during which the digital signal processing circuit 79 operates is separated, the clock signal is output to the analog voltage when the A / D conversion circuit 78 converts the digital value. The voltage fluctuation due to the circuit 40 is affected. When the clock signal output circuit 40 is constituted by the circuit of FIG. 2 and the digital signal processing circuit 79 is constituted by the cMOS logic circuit, the timing T and the digital signal processing circuit 79 which are converted into digital values by the A / D conversion circuit 78. It is very effective to separate the period during which the device operates.

The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.
The technical scope of the claims described below is not limited to the examples. The examples are merely illustrative. For example, the switching circuit is not necessarily composed of one transistor. Two or more input terminals may be provided, and conduction / non-conduction between the current limiting element and the ground line may be switched depending on the input pattern. The switching circuit may be composed of a combination of a plurality of elements, and may constitute a logic circuit.
By using the technique of the embodiment, the circuit scale can be reduced as compared with the case of using the CMOS logic circuit. For example, in the case of the multi-input NAND circuit or NOR circuit shown in FIGS. 10, 11, 13, and 14, the logic circuit can be configured with a smaller number of transistors than in the case of the CMOS logic circuit. In addition, a logic circuit can be configured with only a NAND circuit configured with an nMOS current limiting element and a pMOS switch, or a NOR circuit configured with a pMOS current limiting element and an nMOS switch. The power supply voltage range in which the circuit operates normally can be reduced. A logic circuit that operates with a low power supply voltage or a logic circuit with high resistance against power supply drop can be configured.

1: conventional inverted voltage output circuit 2 using a cMOS logic circuit 2: DC power supply 2a: ungrounded terminal 2b: ground terminal 4: pMOS transistor 6: nMOS transistor 8: power supply terminal 10: output terminal 12: power supply line 13: ground Line 11: Inverted voltage output circuit 14 of the first embodiment: pMOS transistor 16: Switching circuit 21: Inverted voltage output circuit 24 of the second embodiment: nMOS transistor 26: Switching circuit

Claims (8)

It is an inverted voltage output circuit used by connecting to a DC power supply,
A current limiting element and a switching circuit are connected in series,
An inversion voltage output circuit that outputs a voltage at an intermediate point between the current limiting element and the switching circuit. The current limiting element is a pMOS transistor that is connected to the positive terminal of the DC power supply and a constant voltage is applied to the gate,
2. The inverted voltage output circuit according to claim 1, wherein the switching circuit comprises an nMOS transistor in which a voltage that is inverted between a high voltage and a low voltage with the passage of time is applied to the gate.   3. The inverted voltage output circuit according to claim 2, wherein the switching circuit is composed of one nMOS transistor. The series circuit of the pMOS transistor and the nMOS transistor according to claim 3 is connected in parallel over a plurality of stages,
The middle point of the front stage is connected to the gate of the nMOS transistor of the rear stage,
A clock signal output circuit characterized in that the intermediate point of the final stage is connected to the gate of the first stage nMOS transistor. The middle point of the front stage is connected to the gate and capacitor of the nMOS transistor of the rear stage,
5. The clock signal output circuit according to claim 4, wherein an intermediate point of the final stage is connected to a gate and a capacitor of the nMOS transistor of the first stage. A frequency dividing circuit for adding and dividing the clock signal output from the clock signal output circuit according to claim 4 is added,
4. A clock signal output circuit, characterized in that the frequency dividing circuit comprises the inverted voltage output circuit according to claim 1. An analog circuit that operates in synchronization with a clock signal output by the clock signal output circuit according to any one of claims 4 to 6,
An analog circuit connected to the same DC power supply as the DC power supply to which the clock signal output circuit is connected. An analog / digital mixed circuit that operates in synchronization with a clock signal output by the clock signal output circuit according to any one of claims 4 to 6,
It is connected to the same DC power supply as the DC power supply to which the clock signal output circuit is connected,
An analog / digital mixed circuit, wherein a time difference is provided between an execution timing of analog / digital conversion processing and an execution timing of digital processing.

Images