JPH04315895A - Reference voltage generation circuit - Google Patents

Abstract

PURPOSE:To stably obtain constant reference voltage at all times by determining the current of plural constatn current source driving plural FETs which determines output voltage only with the FET of an identical conductive type. CONSTITUTION:Current I6 flowing through an MOS transistor(Tr) N is determined by a current mirror circuit 7 designed so that MOS transistors(Tr) N1 and N2 at a channel N can shown an identical Tr characteristics. Accordingly, the current equal in intensity to the current I7 flowing through an MOSTrP7 at a channel P always flows through the TrN1. If it is assumed that the gsate width of an MOSTrP1 is twice the gate width of the TrP7, current I1 flowing through the TrP and current I7 flowing through the TrP7 are determined by output voltage V04 of a bias generation citrcuit 4 and the following formura stands up: I1=2.I7. Thus, as to current I2 flowing through MOSTrP2 at a channel P, the following formulas stand up: I2=I1-I6 =2.I7-I6, I2=2.I7-I6=I6, and so the current flowing thorugh the TrP2 always equals to current MOSTrP6 at a channel P.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit used in a semiconductor integrated circuit.

0002

2. Description of the Related Art A circuit diagram of an example of this type of reference voltage generating circuit is shown in FIG. As shown in the figure, this circuit consists of a P-channel MOS field effect transistor (hereinafter referred to as PMOS transistor) P1 connected between a high-level power supply terminal 1 and an output terminal 2, and a P-channel MOS field effect transistor (hereinafter referred to as a PMOS transistor) connected between the output terminal 2 and the ground terminal 3. It consists of a PMOS transistor P2 which is diode-connected between them, and a bias generation circuit 4.

The bias generation circuit 4 includes three diode-connected PMOS transistors P3, P4, and P5 connected in series between the high-level power supply terminal 1 and the ground terminal 3.
Consisting of This bias generation circuit 4 is a circuit for applying a gate bias voltage that is less dependent on the power supply voltage to the PMOS transistor P1.
MOS transistor P1 functions almost as a constant current source. At this time, the output terminal 2 is connected to a PMOS transistor P.
A reference voltage VREF having a value equal to the gate-source voltage required for the PMOS transistor P1 to flow the determined current value is outputted.

FIG. 4(a) shows the above bias generation circuit 4.
FIG. 3 is a current-voltage characteristic diagram for explaining the operation of the device. Here, the PMOS transistor P5 is a transistor with an extremely long channel length. Bias generation circuit 4
The operating point of PMOS transistor P5 is the current-voltage characteristic curve (P5) shown in FIG.
This is the intersection point with the current-voltage characteristic curve (P3+P4) of the series circuit of transistors P3 and P4, and the output voltage VO4
Almost (VCC-2・VTP) (however, VCC
is the high-level power supply voltage, and VTP is the threshold voltage of the PMOS transistor). Therefore, regarding the PMOS transistor P1 in the output stage, a constant voltage of -2·VTP is always applied between the gate and source of this MOS transistor even if the high-level power supply voltage VCC fluctuates. Current I1 flowing through the transistor
There is no change in the size of

Next, FIG. 4(b) shows the current-voltage characteristics of each of the output stage PMOS transistors P1 and P2. According to FIG. 4(b), the operating point of the output stage is the intersection of the current-voltage characteristic curve (P1) of the PMOS transistor P1 and the current-voltage characteristic curve (P2) of the PMOS transistor P2, and As can be seen, even if the high-level power supply voltage VCC fluctuates, the current I1 flowing through the PMOS transistor P1 is kept constant, so that a constant reference voltage VREF can be obtained as the output voltage VOUT.

However, this reference voltage generation circuit has a major drawback in that the output reference voltage VREF is determined by the transistor characteristics of the PMOS transistor P2 itself, and the temperature dependence of the transistor characteristics itself is reflected in the reference voltage VREF. ing.

A circuit that improves the above-mentioned drawbacks is a reference voltage generation circuit shown in FIG. The difference between this circuit and the reference voltage generation circuit shown in FIG. 3 is that the PMOS transistor P1
A point where a PMOS transistor P6 diode-connected and an N-channel MOS field effect transistor (hereinafter referred to as an NMOS transistor) N1 are connected in series between the node 5 connected to P2 and the ground terminal 3, and this NMOS The difference is that a bias generation circuit 6 is provided to control the gate voltage of the transistor N1.

The bias generation circuit 6 has a structure in which a PMOS transistor P7 and two diode-connected NMOS transistors N2 and N3 are connected in series between the high-level power supply terminal 1 and the ground terminal 3. The output voltage VO4 of the bias generation circuit 4 is applied to the gate of the PMOS transistor P7. This bias generation circuit 6
The output voltage VO7 is set to 2·VTN (however, VTN
generates the threshold voltage of NMOS transistors N2 and N3). Therefore, bias generation circuit 6 and NMO
By combining it with the S transistor N1, a constant current I6 can be obtained, similar to the combination of the bias generating circuit 4 and the PMOS transistor P1 described above. That is, in this reference voltage generation circuit, the combination of bias generation circuit 4 and PMOS transistor P1,
and bias generation circuit 6 and NMOS transistor N1
The combinations may be considered to constitute constant current sources.

Output voltage VOUT of this reference voltage generation circuit
In other words, a constant voltage VREF is output from the potential VO2 at the node 5 by the gate-source voltage necessary for the PMOS transistor P6 to flow the current I6 determined by the NMOS transistor N1. Therefore, the current I flowing through the PMOS transistor P1
1 and the current I flowing through the PMOS transistor P6
6 is set to a small value such as 1 μA, the output voltage is VREF = VTP2 − VTP6 (
However, VTP2 is the threshold voltage of PMOS transistor P2, and VTP6 is PMOS transistor P6.
threshold voltage). According to the reference voltage generation circuit shown in FIG. 5, the output reference voltage VREF
Because it is in the form of a difference in the characteristic values of two MOS transistors,
The effect of temperature dependence is canceled out and favorable characteristics are obtained.

0010

[Problem to be Solved by the Invention] As mentioned above, FIG.
In the conventional reference voltage generation circuit shown in Figure 1, the output reference voltage VREF is determined by the current I2 flowing through the PMOS transistor P2 and the PMOS transistor P2.
6, but the current I2 is PM
Current I1 and current I6 flowing through OS transistor P1
Therefore, it can be considered that the reference voltage is actually determined by the current I1 and the current I6. The current value I1 is determined by the transistor characteristics of the PMOS transistors P3, P4, and P1, and the current value I6 is determined by the transistor characteristics of the NMOS transistors P3, P4, and P1.
These are transistor characteristics of S transistors N2, N3 and N1. However, these characteristics can change completely independently when factors that determine transistor characteristics, such as circuit design, element layout design, or manufacturing conditions, change, which can cause the reference voltage generation circuit to malfunction. Sometimes I end up doing it.

[0011] The reference voltage generating circuit is often always in an active state due to its use and purpose, and it accounts for a large proportion of the power consumption in the standby state of the integrated circuit.
Each current I1 and I6 is required to be set as small as possible. Specifically, these currents are 1μ
Although it is about A, PMOS transistors P2 and P
6, the gate-source voltage is set near the threshold voltage, so if these set current values fluctuate independently, the output reference voltage VREF will change significantly. For example, if current I6 becomes large, current I2 becomes I2 = I
1 −I6, so in the extreme case the current I2
becomes almost 0, and the PMOS transistor P2 becomes almost non-conductive. For this reason, it may happen that the desired reference voltage cannot be obtained at all.

0012

[Means for Solving the Problems] The reference voltage generation circuit of the present invention is such that the currents of two constant current sources that drive two field-effect transistors that determine the output voltage respond to fluctuations in factors that determine transistor characteristics. change in conjunction with each other,
It is characterized in that the ratio of the two currents remains constant.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The difference between this embodiment and the conventional reference voltage generation circuit shown in FIG. 5 is that NMOS transistors N1 and N2
are designed to exhibit the same transistor characteristics, forming a current mirror circuit 7. That is, in this embodiment, the NMOS transistor N1
Since the current I6 flowing through the NMOS transistor N1 (and therefore the PMOS
A current of the same magnitude as the current flowing through the PMOS transistor P7 always flows through the transistor P6.

This embodiment operates as follows. Now P
Assume that the gate width of MOS transistor P1 is twice that of PMOS transistor P7. P.M.O.
Current I1 flowing through S transistor P1 and PMO
The current I7 flowing through the S transistor P7 is determined by the output voltage VO4 of the bias generation circuit 4, and I1 = 2.
・It is I7.

Therefore, the current I2 flowing through the PMOS transistor P2 is: I2 = I1 - I6 = 2.I7 - I6

(1).

On the other hand, as described above, the current I6 flowing through the PMOS transistor P6 is
7 is equal to the current I7 flowing through I7, so equation (1) is
2 = 2・I7 - I6 = I6, so the PMOS transistor P2 always has PM
A current of the same magnitude as the current flowing through the OS transistor P6 flows. Moreover, all these current values are PMOS
Since it is determined by the characteristics of the transistor, the characteristics of the MOS transistor may vary due to fluctuations in manufacturing conditions.
Even if the transistor characteristics change due to changes in usage environmental conditions such as temperature, or changes in circuit conditions such as power supply voltage or back gate voltage, each current value changes in conjunction. That is, even if the MOS transistor characteristics change, the current I2 and the current I6 are reliably kept equal. Therefore, the output reference voltage is always P
MOS transistor P2 and PMOS transistor P6
The voltage difference with the characteristics is stably output. As for the NMOS transistors N1 and N2, it is only necessary that their characteristic values match, and their absolute values have no influence at all.

In the above explanation, the current flowing from the constant current source constituted by the PMOS transistor P1 and
Although the case has been described in which the ratio of the current to the current of the current mirror circuit 7 caused by the PMOS transistor P7 is 2:1, as is clear from the above description, the present invention is not limited to this. It can be any value.

Next, a second embodiment of the present invention will be explained. FIG. 2 is a circuit diagram of a second embodiment of the invention. The difference between this embodiment and the first embodiment shown in FIG. 1 is that the PMOS transistor P1 as a constant current source that drives the P-channel PMOS transistor P2 is composed of two PMOS transistors P11 and P12 connected in parallel. This is the point. The three PMOS transistors P11, P12, and P7 have all the elements that affect transistor characteristics such as channel length, channel width, and layout direction on the chip.

[0020]This embodiment is different from the first embodiment in that each MO
This has the effect of further improving the uniformity of the characteristics of the S transistors and increasing the degree of freedom in the layout of the MOS transistors.

[0021]

As explained above, in the reference voltage generating circuit of the present invention, the currents of the two constant current sources that drive the two field effect transistors that determine the output voltage are all connected to the field effect transistors of the same conductivity type. It can be decided only by Therefore, the two currents change in conjunction with changes in factors that determine transistor characteristics, such as manufacturing conditions, usage environmental conditions, or circuit conditions, and the ratio of the two currents always maintains a constant value.

Therefore, the output voltage is always equal to the above two
The voltage difference between the characteristics of the two field effect transistors is stably output. Furthermore, since stable current setting is performed as described above, malfunction does not occur even if the current value of each constant current source is set to a small value, and power consumption can be reduced. This is a great advantage in reducing the power consumption of the entire integrated circuit. Further, since there is a large tolerance to circuit conditions and manufacturing conditions, circuit design becomes easy and manufacturing yield can be improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

FIG. 3 is a circuit diagram of an example of a conventional reference voltage generation circuit.

4 is a current-voltage characteristic diagram of a MOS transistor for explaining the operation of the reference voltage generation circuit shown in FIG. 3. FIG.

FIG. 5 is a circuit diagram of another example of a conventional reference voltage generation circuit.

[Explanation of symbols]

1 High-level power supply terminal 2 Output terminal 3 Ground terminal 4,6 Bias generation circuit 5 Node 7 Current mirror circuit

Claims (6)

[Claims] 1. A first field effect transistor and a second field effect transistor of the same conductivity type, a first constant current source that drives the first field effect transistor, and the second field effect transistor. a second constant current source to drive, and whose output voltage is a difference voltage between the threshold voltage of the first field effect transistor and the threshold voltage of the second field effect transistor. In the generating circuit, the current value of the first constant current source and the current value of the second constant current source maintain a constant current ratio with respect to changes in physical quantities related to determination of the two current values. A reference voltage generation circuit characterized by holding and changing. 2. A first constant current source provided between a first power terminal and a first node, and a diode-connected constant current source provided between the first node and a second power source terminal. a first field effect transistor of a first conductivity type; a second field effect transistor of a first conductivity type diode-connected between the first node and an output node; and a second field effect transistor of the first conductivity type and the output node and the second power source. a second constant current source provided between the terminal and the second constant current source, and the current value of the first constant current source and the current value of the second constant current source are used to determine the two current values. A reference voltage generation circuit characterized in that it changes while maintaining a constant current ratio in response to changes in related physical quantities. 3. The current value of the first constant current source and the second constant current source is determined only by a field effect transistor of one conductivity type.
Or the reference voltage generation circuit according to claim 2. 4. The reference voltage generating circuit according to claim 3, wherein the reference voltage generating circuit is constituted by a MOS type field effect transistor. 5. A P-channel type first circuit whose source is connected to a high-level power supply terminal and whose gate is inputted with an external voltage.
a MOS type field effect transistor whose source is said first
a P-channel type second MOS type field effect transistor whose gate and drain are connected to the drain of the MOS type field effect transistor and whose source is connected to the drain of the second MOS type field effect transistor; A third P-channel MOS field effect transistor is connected to the source and has its gate and drain connected to the output terminal, and the source is connected to the high-level power supply terminal and the external voltage is input to the gate. a P-channel type fourth MOS type field effect transistor, and a fifth N-channel type MOS type field effect transistor, whose gate and drain are connected to the drain of the fourth MOS type field effect transistor, and whose source is connected to the ground terminal. a MOS type field effect transistor; a gate is connected to the gate of the fifth MOS type field effect transistor, a drain is connected to the output terminal, and a source is connected to the ground terminal; N that constitutes a transistor and current mirror circuit
1. A reference voltage generation circuit comprising: a sixth channel type MOS field effect transistor. 6. The reference voltage generating circuit according to claim 5, wherein the first P-channel MOS field-effect transistor comprises a plurality of P-channel MOS field-effect transistors having the same electrical characteristics connected in parallel. A reference voltage generation circuit characterized by having a structure.