JPH01270152A - Interruption circuit - Google Patents

Abstract

PURPOSE:To obtain an interruption circuit with high accuracy to record a time for the generation of an interruption request without any delay by controlling the storage of reference time data directly by an interruption request signal. CONSTITUTION:A reference time clock circuit 110 generates reference time data to find an interruption request generating time, and time holding circuits 104-106 store time data outputted from the reference time clock circuit 110 by a data interruption request signal. When the interruption request signal is inputted to input terminals 101-103, the time holding circuits 104-106 corresponding to each of the input terminals 101-103 store the data outputted from the reference time clock circuit 110. In such a way, it is possible to obtain the interruption circuit which holds an interruption generating time with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt circuit, and more particularly to an interrupt circuit that maintains the time of occurrence of an interrupt with high precision.

[Conventional technology]

A conventional example of this type of interrupt circuit is shown in FIG. 2, and a processing flow of the conventional example of FIG. 2 is shown in FIG.

When the CPU 204 receives an interrupt request signal from the input terminals 201, 202, 203, it interrupts the process currently being executed and starts executing the interrupt request with the highest priority among the input interrupt requests. The interrupt request generation time is recorded by the CPU 20 in the process of this interrupt request.
4 takes in the time output from the reference time clock circuit and holds it in time holding circuits 206, 207, and 208.

[Problem to be solved by the invention]

The conventional interrupt circuit described above records the interrupt request generation time when the CPU executes processing based on the interrupt request, so the recorded interrupt request generation time data is delayed from the time when the interrupt request actually occurs. There is a drawback.

Also, when multiple interrupt requests occur at the same time, processing by the interrupt requests is executed one by one in order.
Since the interrupt request generation time is recorded, there is a drawback that multiple interrupt request generation times that occur simultaneously cannot be recorded as the same time.

[Means to solve the problem]

The interrupt circuit of the present invention includes a reference time clock circuit that generates reference time data, and a time storage circuit that receives the output of the reference time clock circuit as an input and stores the time data output from the reference time clock circuit in response to an interrupt request signal. The number of interrupt request signals is equal to the number of interrupt request signals.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. 10
1, 102, and 103 are input terminals into which an interrupt request signal is input. A reference time clock circuit 110 generates reference time data for determining the time when an interrupt request occurs. 10
Reference numerals 4, 105, and 106 are time holding circuits that store time data output from the reference time clock circuit 110 in response to an interrupt request signal. When an interrupt request signal is input to the input terminals 101, 102, 103, the time holding circuits 104, 105, 106 corresponding to each input terminal store the time data output from the reference time clock circuit 110. Therefore, this embodiment has a function of recording the generation time of the interrupt request signal.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which storage of reference time data is directly controlled by an interrupt request signal, so that when an interrupt request signal is input, the time of occurrence of the interrupt request is recorded without delay. A highly accurate interrupt circuit can be provided. Furthermore, when a plurality of interrupt requests occur at the same time, recording of the respective interrupt and request generation times is processed independently of each other, so that the plurality of interrupt request generation times that occur simultaneously can be recorded as the same time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a conventional example of an interrupt circuit, and FIG. 3 is a diagram showing a processing flow in the conventional example of FIG. 101.102,103,201,202゜203...
...Input terminal, 104, 105, 106°206.
207, 208... Time holding circuit, 11o. 205...Reference time clock circuit, 107, 204
...CPU. Agent Patent Attorney Susumu Uchihara 2nd Eye 3 Figure

Claims (1)

[Claims] A reference time clock circuit that generates reference time data, and a time memory circuit that receives the output of the reference time clock circuit as an input and stores time data output from the reference time clock circuit in response to an interrupt request signal, the number of which is equal to the number of interrupt request signals. An interrupt circuit characterized by: