JPS6013216B2 - complex computing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a compound computer in which an input processing device is shared by a plurality of computing devices.

With the advent of microprocessors, computing devices with distributed functions using dedicated microprocessors for each control function have begun to be realized due to their features such as high reliability and system flexibility.

A feature of this complex computer system consisting of a plurality of microprocessors is that the functional range of the microprocessors is limited, but this results in the need for the same input to be used by the plurality of microprocessors. Providing input processing for each microprocessor increases costs, so a system is often adopted in which the input processing device is shared by a plurality of microprocessors. Conventionally, methods such as those shown in FIGS. 1 and 2 have been used. (An example of Fig. 2 is (Tokukan Sho 52-209, Samurai Seki Sho 52-7424, Hakama Seki 52-74243).)
0 and 30 each consist of a microprocessor 21, an input control circuit 22, and an inter-device interface 23, and a microprocessor 31 and an inter-device interface 33, and the computing devices are coupled via the inter-device interfaces 23 and 33. . The input processing device 10 is controlled by the input control circuit 22 of one of the computing devices, and transmits necessary data to the microprocessor 21 at the necessary timing. Information necessary for the microprocessor 31 from among the information of the input processing device 10 is transferred between the computing devices via the inter-device interfaces 22 and 23. In this method, one calculation device A (in the case of Figure 1, calculation device A) collects the information necessary for another calculation device B, so if this calculation device A breaks down, other calculation devices There is also the disadvantage that the calculation results of device B may also be abnormal. The method shown in Figure 2 is based on the input control circuit 2 for both computing devices.
2 and 32 are provided, an interlock is established between the input control circuits 22 and 32, and only one of the microprocessors inputs information from the input processing device 10. This method has a long life in which a failure of one microprocessor does not affect other microprocessors, but when there are many microprocessors or when the input processing device is slow, input requests from multiple microprocessors may occur simultaneously. During this time, all microprocessors other than one are kept on standby, resulting in slow processing. Furthermore, there are also disadvantages in that the interlocks between input control circuits become complicated, and the interlocks cannot be determined unless the number of microprocessors and the division of functions are determined, resulting in less flexibility of the system. The present invention has been made in view of this current situation, and its purpose is to provide a complex computing device that is highly flexible and can be used commonly as an input processing device by providing a scan control circuit in the input processing device.

Embodiments of the present invention will be described in detail below with reference to FIGS. 3 to 7.

First, the configuration of the present invention will be explained using FIG. FIG. 3 shows an example in which an input processing device is shared by two microprocessors.
35, and is coupled to the input processing device 10 via buffer circuits 25, 35.

The scan control circuit 11' outputs a selection signal of information to be given to the calculation device to the input processing device 10 and each buffer circuit 25, 35. In the present invention, as shown in FIG.
0 to the buffer circuits 25, 35 of each computing device 20, 30
Each microprocessor 21, 31 can take in the input information only when the input information is necessary.

Next, the scanning control circuit 11, which is one of the features of the present invention, will be explained using FIG. 4 showing an embodiment. As shown in FIG. 4, the output of the oscillator 113 is input to the power counter 112, the count-up output of the counter 112 is input to the shift register 111, and the count value output of the counter 112 and the status output of the shift register 111 are input to the decoder. 1
14, and the output of the decoder 114 is connected to the input processing device as an input information selection signal. The output of the shift register 111 is input to the OR gates 115 and 1161, and the output of the OR gates 115 and 116 is sent to the buffer circuit as a selection signal indicating that the input information necessary for each calculation device is input to the buffer circuit. Connected. The operation shown in FIG. 4 will be explained using the time chart shown in FIG.

However, in order to simplify the explanation, we will assume a system in which the input processing device 10 is shared by the two calculation devices A, B, 20, and 30 shown in FIG. 4 words, the number of data used only by computing device A is 2
The following explanation assumes that the number of words and data used only by computing device B is three words. The counter 112 is a down counter with an initial value of 3, and the count value is updated at the fall of the output of the oscillator 113, so every fall of 3, 2, 1, 0
, 3, 2, and so on.

The shift register 111 receives the down pulse of the counter 112 (the pulse generated when the count value changes from 0 to the initial value 3), and outputs Q, , Q as the pulse is input.
2 and Q3 become level "1" in order. Shift register output Q. , Q2, and Q3 mean the common input for both computing devices, the input for computing device A, and the input for computing device 8, respectively, so the decoder selects the corresponding word of the input processing device from Q・, Q, and Q and the count values. It is possible to generate a signal that Also, the outputs SELA, S of OR gates 1 15, 1 16
ELB is each Q or Q2 is "1", Q or Q is "I"
When J, it becomes "1", so computing device A is equal to "1" and S
When ELA = "1", the information from the input processing device 10 can be taken into the buffer circuit 25.
When SELB="1", information from the input processing device 10 can be taken into the buffer circuit 35. Next, details of the buffer circuit 25 will be explained using FIG.

The register 251 is for buffering input information and receives the output of the input processing device, and the output is input to the microprocessor. The flip-flop 253 outputs one of the shift register outputs (
Q) is connected to the clock terminal CLK, and the input enable signal, which is a control signal from the microprocessor, is connected to the data terminal D. The oscillator output J of the control circuit 11 and the selection signal SELA are connected to the AND gate 25.
2 is input. Since the output of the AND gate 252 becomes "1" when input information can be taken in, it is connected to the clock terminal of the register 251 and is also connected to the microprocessor as a status signal or an interrupt request signal.
The buffer circuit 25 in FIG. 5 receives input information cyclically input at a period determined by the oscillator period of the scan control circuit 11, the value of the counter, and the number of output stages of the shift register when the input permission signal becomes "1". Only the input information after Q, is "
It is possible to input data to the microprocessor in order from the timing when the data becomes "1". In order to prevent the microprocessor from inputting useless input information, the input permission signal rl is applied only when input information is required. As explained above, in FIGS. 4 and 5, since the input information of the input processing device is repeatedly input at a constant period, each microprocessor is different from the other. Setsa is the other mic. It is possible to input only the input information necessary for oneself at the necessary timing, regardless of the processor. In the case of Figure 4, each output of the shift register...
Since the initial count value for Q2, . . . is constant, if the input information is not uniform, a wasteful operation is performed.

In the example used to explain Fig. 4, 4 counts are required for Q, 2 for Q2, and 3 counts for Q3, so there are 2 counts for Q2 and 1 count for Q, and a word that does not exist in the input processing device. will be selected. FIG. 6 is an improvement on this point, in which a setter 117 consisting of a group of setting circuits corresponding to the number of output stages of the shift register 111 is added, and the output of the setter is used as the initial value of the counter 112. However, the plurality of setting circuit groups are selected by the output of the shift register 11, and only one corresponding initial value is input to the counter 112. In the case of FIG. 6, the count value matches the number of input information, so unnecessary operations are omitted. In the case of FIG. 5, the timing shift between the input device and the microprocessor is only allowed by one input information.

That is, once the input information is taken into the register, the microprocessor needs to take in that input information until the next input information is taken in. Figure 7 shows an improved version of this point, using FiGtlnFirstO as a buffer for input information.
utmemory (hereinafter referred to as FIFO memory) 255
A monostable circuit 256 is added to the data input terminal of the flip-flop 253. FIFO memory 2
Reference numeral 55 is a memory whose input and output can be controlled independently and outputs the stored contents in the order in which they are input.The memory capacity can be arbitrarily selected from several tens of words, so the operation between the input processing device and the microprocessor can be easily controlled. The timing deviation is allowed by the storage capacity of F'0 memory. Therefore, regardless of whether the input processing device operates slowly or quickly, input information can be taken in at the timing and processing speed of the microprocessor.

Furthermore, by adding the monostable circuit 256, even if the reset of the input request signal is delayed, the flip-flop 253 can maintain the Q
, is "1" only during one period between the rising edge of , and the next rising edge.
Therefore, it is possible to import input information in a fixed order without duplication. As explained above, according to the present invention, in a system in which an input processing device is shared by multiple computing devices, by adding a simple scan control circuit to the input side, all information of the input processing device can be cyclically transmitted to all computing devices. Since the independence between each computing device is maintained, and even if the amount of input information or the purpose of the input information changes, each computing device does not change, so reliability is high and the amount of input information can be reduced. Input information processing that can be easily changed is realized.

Moreover, by providing a simple buffer circuit on each computing device side, it is possible to prevent unnecessary input information from being taken in, which improves the operating efficiency of each computing device.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams showing the slave device, FIG. 3 is a block diagram showing the present invention, and FIGS. 4 and 5 are examples of the scan control circuit and buffer circuit used in the present invention, respectively. 6 and 7 are detailed block diagrams of other examples of the scan control circuit and buffer circuit, and FIG. 8 is a time chart for the present invention. 10... Input processing device, 11... Scanning control circuit, 20, 30... Computing device, 21, 3
1...Microprocessor, 23,33...
...Device interface, 111...Shift register, 112... ... Counter, 113 ... Oscillator, 114 ... Decoder, 115, 116 ...
OR gate, 117...setting device, 251...register,
252. ．．・...AND gate, 253...Flip-flop. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1 In a compound computing device formed by combining a plurality of computing devices that perform various calculations based on information from an input processing device,
A scanning control circuit for specifying and selecting information necessary for each computing device from among the information from the input processing device, and a scanning control circuit provided in each computing device to temporarily store information specified and selected by the scanning control circuit. a buffer circuit provided in each of the computing devices for outputting an output permission signal to the buffer circuit, confirming the specified selection of the scanning control circuit, and retrieving the information stored in the buffer circuit; A complex computing device consisting of a setsa.