JPH01266753A - Semiconductor device module package - Google Patents
Semiconductor device module packageInfo
- Publication number
- JPH01266753A JPH01266753A JP63095920A JP9592088A JPH01266753A JP H01266753 A JPH01266753 A JP H01266753A JP 63095920 A JP63095920 A JP 63095920A JP 9592088 A JP9592088 A JP 9592088A JP H01266753 A JPH01266753 A JP H01266753A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor devices
- adjacent
- leads
- module package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 abstract 4
- 238000009413 insulation Methods 0.000 abstract 3
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置モジュールパッケージに関し、特に
半導体装置間に絶縁分離体を有するパッケージに関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device module package, and more particularly to a package having an insulating separator between semiconductor devices.
従来、この種の半導体装置モジュールパッケージは、実
装面が平面である回路基板上に半導体装置を搭載するた
め隣接する他の半導体装置のリードとの間隔を保つこと
は非常にむずかしいものであった。Conventionally, in this type of semiconductor device module package, since the semiconductor device is mounted on a circuit board with a flat mounting surface, it has been extremely difficult to maintain a distance from the leads of other adjacent semiconductor devices.
上述した従来の半導体装置モジュールパッケージは、半
導体装置を搭載する回路基板上の実装面が平面となって
いるので、回路基板上に高密度に半導体装置を搭載した
場合、半導体装置のリードが近接した他の半導体装置の
リードと接触してしまうという欠点がある。In the conventional semiconductor device module package described above, the mounting surface on the circuit board on which the semiconductor devices are mounted is flat, so when the semiconductor devices are mounted on the circuit board at high density, the leads of the semiconductor devices are close together. There is a drawback that it comes into contact with the leads of other semiconductor devices.
本発明の半導体装置モジュールパッケージは、回路基板
上に搭載する半導体装置間に絶縁分離体を有している。The semiconductor device module package of the present invention has an insulating separator between semiconductor devices mounted on a circuit board.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)は本発明の一実施例の断面図であり、第1
図(b)はその平面図である。この半導体装置モジュー
ルパッケージは回路基板1の上に搭載された半導体装置
3のリード4と隣接した半導体装置5のリード6の間の
回路基板1上に絶縁分離体2を形成する。この絶縁分離
体2を形成することにより搭載した半導体装置がずれた
場合でも隣接した半導体装置のリードが接触することは
ない。FIG. 1(a) is a sectional view of one embodiment of the present invention, and the first
Figure (b) is a plan view thereof. In this semiconductor device module package, an insulating separator 2 is formed on a circuit board 1 between leads 4 of a semiconductor device 3 mounted on the circuit board 1 and leads 6 of an adjacent semiconductor device 5. By forming this insulating separator 2, even if the mounted semiconductor devices are shifted, the leads of adjacent semiconductor devices will not come into contact with each other.
第2図(a)は本発明の実施例2の断面図であり、第2
図(b)はその平面図である。FIG. 2(a) is a sectional view of Embodiment 2 of the present invention.
Figure (b) is a plan view thereof.
この半導体装置モジュールパッケージは回路基板1の上
に搭載された半導体装置3と隣接した半導体装置5の間
に絶縁分離体2を形成する。この絶縁分離体2を形成す
ることにより、搭載した半導体装置間の間隔は常に一定
に保たれるため隣接した半導体装置のリードが接触する
ことはない。This semiconductor device module package forms an insulating separator 2 between a semiconductor device 3 mounted on a circuit board 1 and an adjacent semiconductor device 5. By forming the insulating separator 2, the distance between the mounted semiconductor devices is always kept constant, so that the leads of adjacent semiconductor devices do not come into contact with each other.
以上説明したように本発明は、回路基板上の半導体装置
間に絶縁分離体を形成することにより、回路基板と、回
路基板上に搭載する半導体装置間に位置のずれが生じず
、また位置のずれが生じた場合でも隣接する他の半導体
装置のリードに接触しないという効果がある。As explained above, the present invention prevents positional deviation between the circuit board and the semiconductor device mounted on the circuit board by forming an insulating separator between the semiconductor devices on the circuit board, and prevents positional deviation between the circuit board and the semiconductor device mounted on the circuit board. Even if misalignment occurs, there is an effect that the leads of other adjacent semiconductor devices will not come into contact with each other.
第1図(a)は本発明の実施例1の半導体装置モジュー
ルパッケージの断面図、第1図(b)はその平面図であ
る。第2図(a)は実施例2の断面図、第2図(b)は
その平面図である。
1・・・・・・回路基板、2・・・・・・絶縁体突起、
3゜5・・・・・・半導体装置、4,6・・・・・・リ
ード。
代理人 弁理士 内 原 音
(b)
第1図
第2図FIG. 1(a) is a sectional view of a semiconductor device module package according to a first embodiment of the present invention, and FIG. 1(b) is a plan view thereof. FIG. 2(a) is a sectional view of Example 2, and FIG. 2(b) is a plan view thereof. 1... Circuit board, 2... Insulator protrusion,
3゜5...Semiconductor device, 4,6...Lead. Agent Patent Attorney Oto Hara (b) Figure 1 Figure 2
Claims (1)
することを特徴とする半導体装置モジュールパッケージ
。A semiconductor device module package characterized by having an insulating separator between semiconductor devices mounted on a circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63095920A JPH01266753A (en) | 1988-04-18 | 1988-04-18 | Semiconductor device module package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63095920A JPH01266753A (en) | 1988-04-18 | 1988-04-18 | Semiconductor device module package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01266753A true JPH01266753A (en) | 1989-10-24 |
Family
ID=14150716
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63095920A Pending JPH01266753A (en) | 1988-04-18 | 1988-04-18 | Semiconductor device module package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01266753A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103042576A (en) * | 2012-11-30 | 2013-04-17 | 张家铭 | Composite board of solid wood or bark-peeled single baseboard with grooves |
-
1988
- 1988-04-18 JP JP63095920A patent/JPH01266753A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103042576A (en) * | 2012-11-30 | 2013-04-17 | 张家铭 | Composite board of solid wood or bark-peeled single baseboard with grooves |
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