JPH01261027A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To decrease the frequency setting interval of an output signal of a voltage controlled oscillator without lowering a phase comparison frequency by providing a multiplier between two programmable counters. CONSTITUTION:A multiplier 11 whose multiple factor is (m) is interposed between a frequency divider 3 and two programmable counters 5, 6. Thus, the setting value of an output signal frequency of a voltage controlled oscillator 4 is set minutely by the number of multiplications of the multiplier 11 than the phase comparison frequency and it is not required to lower the phase comparison frequency. Thus, superimposition of noise on an output signal of the voltage controlled oscillator 4 or a prolonged time required for stabilizing the frequency is evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frequency synthesizer device that obtains a signal with a frequency determined by an external signal by controlling a voltage controlled oscillator.

Prior Art FIG. 2 is a block diagram showing the configuration of a conventional frequency synthesizer device. In FIG. 2, 21 is a reference signal oscillator, the output of which is input to a fixed frequency divider 22. 23 is a divider that selects one of two division ratios, 1/(p+n) and 1/p, according to a control signal, and voltage controlled oscillator 24
The output of is input. 25 and 26 are programmable counters that determine the frequency division ratio based on external signals, and the respective outputs are input to the control circuit 27 and sent to the frequency divider 23 as a control signal for switching the frequency division ratio. 28 is a phase comparator, which includes a fixed frequency divider 22 and a programmable counter 25.
The switch circuit 29 is controlled by the phase difference between the output signals.

The output of the switch circuit 29 is applied as a control signal to the voltage controlled oscillator 24 through a filter circuit 30.

Next, the operation of the above conventional example will be explained. In FIG. 2, when the phases of the two signals applied to the phase comparator 28 match, the output of the switch circuit 29 is open; however, when the phase of the signal on the fixed frequency divider 22 side is early, If the phase of the signal on the programmable counter 25 side is earlier than the positive potential, connect it to the negative potential or ground. As a result, the oscillation frequency of the voltage controlled oscillator 24 is controlled such that the phase difference between the two signals input to the phase comparator 28 always matches. On the other hand, the control circuit 27 to which the outputs of the programmable counters 25 and 26 are inputted receives the output of the programmable counter 26 and sets the frequency division ratio of the frequency divider 23 to 1/(p+n
) sends out a control signal to change the ratio to 1/p.

Furthermore, when the output of the programmable counter 25 is obtained, the frequency division ratio is returned to 1/(p+n), and the programmable counters 25 and 26 are preset.

Here, the set values N and A of the programmable counters 25 and 26 always have a relationship of N≧A. Therefore, the conditions for the input signals of the phase comparator 28 to match and become stable from each frequency division ratio shown in FIG. If the value is r and the oscillation frequency of the voltage controlled oscillator 24 is fvco, then the following is true. Therefore, the oscillation frequency f v of the voltage controlled oscillator 24
oo is R fvco= (P N+ n A)-. In this way, in the conventional frequency synthesizer device described above, by setting the values of N and A to R using an external signal, a signal of a desired frequency can be obtained based on the phase comparison frequency -.

Problems to be Solved by the Invention However, in the conventional frequency synthesizer device described above, the output signal frequency of the voltage controlled oscillator is limited to an integral multiple of the phase comparison frequency. Therefore, if you try to reduce the setting interval of the output signal frequency of the voltage controlled oscillator, the frequency of the noise generated in the switch circuit will also decrease in order to lower the phase comparison frequency, and the amount of noise passing through the filter circuit will increase. There was a problem in that noise was superimposed on the output signal of the voltage controlled oscillator. On the other hand, if the cutoff frequency of the filter circuit is lowered in order to block this noise, the response speed of the entire system will decrease, causing the problem that it will take longer for the output signal frequency of the voltage controlled oscillator to become stable. .

The present invention solves these conventional problems,
It is an object of the present invention to provide a frequency synthesizer device that can reduce the frequency setting interval of the output signal of a voltage controlled oscillator without lowering the phase comparison frequency.

Means for Solving the Problems In order to solve the above problems, the present invention provides a system which is connected to a voltage controlled oscillator and divides the signal of the voltage controlled oscillator by selecting one of two frequency division ratios by a control circuit. A frequency divider that rotates,
A multiplier is inserted between two programmable counters.

Effect With the above configuration, by providing a multiplier, the phase comparison frequency can be increased by the multiplier, and therefore,
Even if the frequency setting interval of the output signal of the voltage controlled oscillator is small, it is possible to prevent noise from being superimposed on the output signal and from prolonging the time until the output signal frequency becomes stable.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of a frequency synthesizer device according to an embodiment of the present invention. In FIG. 1, 1 is a reference signal oscillator, the output of which is input to a fixed frequency divider 2. Reference numeral 3 denotes a frequency divider which can select one of two frequency division ratios, 1/(p+n) and 1/p, by a control signal, and the output of the voltage controlled oscillator 4 is input thereto. 5 and 6 are programmable counters that set the frequency division ratio by external signals, and their respective outputs are connected to the control circuit 7 and sent to the frequency divider 3 as a frequency division ratio switching control signal. 8
is a phase comparator, which controls the switch circuit 9 based on the phase difference between the output signals of the fixed frequency divider 2 and the programmable counter 5. The output of the switch circuit 9 is applied to the voltage controlled oscillator 4 through a filter circuit 10 as a control signal. 1
1 is a multiplier having a multiplier of m, and is interposed between the frequency divider 3 and the two programmable counters 5 and 6.

Next, the operation of the above embodiment will be explained. In FIG. 1, the control circuit 7 obtains the output of the programmable counter 6 and changes the division ratio of the frequency divider 3 from 1/(p ten n) to l/p.
The programmable counter 5 outputs the output of the programmable counter 5, returns the frequency division ratio to 1/(p+n), and presets the programmable counters 5 and 6. The oscillation frequency of the voltage controlled oscillator 4 is controlled so that the phases of the signals input to the phase comparator match. As a result, the first
What are the conditions for the phases of the input signals of the phase comparator 8 to match and become stable based on the frequency division ratios shown in the figure?

The oscillation frequency of the reference signal oscillator 1 is fR1, the set value of the fixed frequency divider 2 is r, and the oscillation frequency of the voltage controlled oscillator 4 is fV(
! If O, then pN+nA. Therefore, the oscillation frequency f of the voltage controlled oscillator 4
vco is. In this way, according to the above embodiment, the set value of the output signal frequency of the voltage controlled oscillator 4 is changed to the phase comparison frequency fi/
It has the advantage that the multiplication number of the multiplier 11 can be set more finely than r. Furthermore, according to the above embodiment, since it is not necessary to lower the phase comparison frequency fR/r, noise is not superimposed on the output signal of the voltage controlled oscillator 4, and the time required for the frequency to become stable can be avoided. It has the effect of being avoidable. In the above embodiment, the multiplication number of the multiplier 11 and the division ratio of the fixed frequency divider 2 are fixed, but they may be changed by external settings. In this case, the effect of being able to set the frequency more precisely can be obtained.

Effects of the Invention As described above, according to the present invention, the phase comparison frequency of the frequency synthesizer is made higher than the setting interval of the output signal frequency, and has the advantage that the frequency interval of the output signal can be set more finely. . Further, since the phase comparison frequency is high, it is possible to prevent noise from being superimposed on the output signal and to avoid a long time until the frequency becomes stable.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a frequency synthesizer according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a conventional frequency synthesizer device. 1... Reference signal generator, 2... Fixed frequency divider, 3...
- Frequency divider, 4... Voltage controlled oscillator, 5, 6... Programmable counter, 7... Control circuit, 8... Phase comparator, 9... Switch circuit, 10... Filter circuit , 11... Multiplier. Fig. 1/-, FJ Doyer No. 'Tilt device?・-Fixed divider 3-minute divider 4・voltage control 2 oscillator 5, 6-4o flamafum η counter 11, −blood meter

Claims (1)

[Claims] 1. A reference signal generator, a first frequency divider that divides the signal, a voltage controlled oscillator whose frequency is controlled by a control voltage applied to a control terminal, and a control circuit that selects one of the two frequency division ratios. a second frequency divider that selects one and divides the signal of the voltage controlled oscillator; two programmable counters whose frequency division ratios are determined by an external signal and whose inputs are connected in parallel; A phase comparison circuit that compares the phases of the output signals of one of the frequency dividers and one of the two programmable counters, a switch circuit that switches and outputs a positive potential and a negative potential based on the output signal of the phase comparison circuit, and the switch. A frequency synthesizer device comprising: a filter circuit for smoothing a circuit output signal to obtain a control voltage for a voltage controlled oscillator; and a multiplier interposed between the second frequency divider and two programmable counters. .