JPH01258471A - Manufacture of mos type semiconductor device - Google Patents
Manufacture of mos type semiconductor deviceInfo
- Publication number
- JPH01258471A JPH01258471A JP8689988A JP8689988A JPH01258471A JP H01258471 A JPH01258471 A JP H01258471A JP 8689988 A JP8689988 A JP 8689988A JP 8689988 A JP8689988 A JP 8689988A JP H01258471 A JPH01258471 A JP H01258471A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon
- gate electrode
- polysilicon film
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 claims abstract description 47
- 230000003647 oxidation Effects 0.000 claims abstract description 30
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 239000012212 insulator Substances 0.000 abstract description 5
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＭＯＳ型半導体装置の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a MOS type semiconductor device.
従来の技術
近年、低消費電力の要求からＭＯＳ型半導体装置が多く
利用されるようになってきた。一方、集積回路の集積度
が増加するにつれて半導体装置の寸法を小さくすること
が求められているが、ＭＯＳ型半導体装置のゲート長を
短かくしていくと、いわゆるショートチャンネル効果が
生じ、半導体装置のしきい１１電圧が著しく低下するこ
とが知られており、ゲート電極の寸法制蔀が＠要となっ
てきている。2. Description of the Related Art In recent years, MOS type semiconductor devices have come into widespread use due to the demand for low power consumption. On the other hand, as the degree of integration of integrated circuits increases, it is required to reduce the dimensions of semiconductor devices, but as the gate length of MOS type semiconductor devices is shortened, a so-called short channel effect occurs, and the size of semiconductor devices increases. It is known that the threshold voltage drops significantly, and it has become important to control the dimensions of the gate electrode.
以下に従来のＭＯＳ型半導体装置の製造方法について説
明する。第２図（ａ）、 （ｂ）は従来のＭＯＳ型半導
体装置の製造方法の一部分の工程断面図であり、１１は
シリコン基板、１２は素子分離領域、１３は拡散層、１
４はゲート酸化膜、１５はポリシリコン膜、１７はレジ
スト膜、１８は酸化されたポリシリコン膜である。A conventional method for manufacturing a MOS type semiconductor device will be described below. 2(a) and 2(b) are cross-sectional views of a part of a conventional method for manufacturing a MOS type semiconductor device, in which 11 is a silicon substrate, 12 is an element isolation region, 13 is a diffusion layer, 1
4 is a gate oxide film, 15 is a polysilicon film, 17 is a resist film, and 18 is an oxidized polysilicon film.
まず、シリコン基板１１に既知の技術にて厚い酸化膜の
素子分離領域１２を形成する。次にシリコン基板１１の
中にイオン注入を行い、しきい値電圧を設定する拡散層
１３を形成する。この後、ゲート酸化１［４を成長させ
、その上にゲート電極となるポリシリコン膜１５を成長
させる。ついで、ポリシリコン膜１５にリンを高濃度に
気相拡散し低抵抗膜とする。さらに、リンガラス化した
ポリシリコン膜を選択除去後、光露光技術、電子ビーム
露光技術、Ｘ線露光技術、あるいはイオンビーム露光技
術を用いてレジスト膜１７を所望のレジストパターンに
形成し、このレジストパターンをマスクとして、ポリシ
リコン膜１５をドライエッチにより選択除去しゲート電
極とする。このときの状態は第２図ｆａ）に示される。First, an element isolation region 12 made of a thick oxide film is formed on a silicon substrate 11 using a known technique. Next, ions are implanted into the silicon substrate 11 to form a diffusion layer 13 for setting a threshold voltage. After this, a gate oxide 1[4 is grown, and a polysilicon film 15 that will become a gate electrode is grown thereon. Next, phosphorus is vapor-phase diffused into the polysilicon film 15 at a high concentration to form a low resistance film. Furthermore, after selectively removing the phosphorized polysilicon film, a resist film 17 is formed into a desired resist pattern using light exposure technology, electron beam exposure technology, X-ray exposure technology, or ion beam exposure technology. Using the pattern as a mask, polysilicon film 15 is selectively removed by dry etching to form a gate electrode. The state at this time is shown in FIG. 2 fa).
次に、レジスト膜１７を除去し、第２図（ｂ）に示すよ
うに、素子分離領域１２のエツジ部の段差部などで除去
しきれなかったポリシリコン！２１５のエッチ残漬がポ
リシリコン同層間の電気的短絡の原因とならぬように、
熱酸化法を用いてポリシリコンＷ：！１５のエッチ残漬
を酸化し、絶縁物とする。このとき同時にポリシリコン
からなるゲート電極の側壁および表面も酸化される。さ
らに、このときに酸化がゲートｍｆｆ１部のゲート酸化
膜１４へ侵食し、ポリシリコン膜１５が持ち上げられて
、ゲート電極の両端１９でゲート酸化＃９厚が増加する
ゲートバーズビークと呼ばれる形状となり実効的なチャ
ンネル長の減少が発生することがある。Next, the resist film 17 is removed, and as shown in FIG. 2(b), the polysilicon film that could not be completely removed due to the steps at the edges of the element isolation region 12! To prevent the etch residue of 215 from causing an electrical short circuit between the same polysilicon layers,
Polysilicon W using thermal oxidation method:! The etched residue of No. 15 is oxidized to form an insulator. At the same time, the side walls and surface of the gate electrode made of polysilicon are also oxidized. Furthermore, at this time, the oxidation invades the gate oxide film 14 in the gate mff1 portion, and the polysilicon film 15 is lifted up, resulting in a shape called a gate bird's beak in which the thickness of the gate oxide #9 increases at both ends 19 of the gate electrode. A significant channel length reduction may occur.
発明が解決しようとする課題
しかしながら上記の従来の製造方法では、ポリシリコン
膜１５からなるゲート電極の表面が酸化され絶縁物とな
るため、導電性を有した実効的なゲート電極の寸法が細
くなり、さらには、ゲートバーズビーク形状となること
で、ＭＯＳ型半導体装置のチャンネル長が変化する。特
に、ポリシリコン膜１５が酸化により薄くなるためゲー
ト電極の電気抵抗値が増加する問題があった。ぞのため
、酸化を高い精度で制御する必要が生じるが、リンを高
濃度に拡散されたポリシリコン膜１５は、増速酸化現象
でシリコン基板１１に比べて酸化速度が著しく速いため
、工程が１１！雑になり、制御ｌｌ精度が損なわれたと
きには、ＭＯＳ型半導体装置の特性にばらつきが生じる
ことになる。Problems to be Solved by the Invention However, in the conventional manufacturing method described above, the surface of the gate electrode made of polysilicon film 15 is oxidized and becomes an insulator, so the effective dimensions of the conductive gate electrode become thin. Furthermore, the gate bird's beak shape changes the channel length of the MOS type semiconductor device. In particular, there was a problem in that the electrical resistance value of the gate electrode increased because the polysilicon film 15 became thinner due to oxidation. Therefore, it is necessary to control oxidation with high precision, but the polysilicon film 15 in which phosphorus is diffused at a high concentration has a significantly faster oxidation rate than the silicon substrate 11 due to the accelerated oxidation phenomenon, so the process is difficult. 11! If the control becomes rough and the control accuracy is impaired, variations will occur in the characteristics of the MOS type semiconductor device.
本発明は上記した従来の問題点を解決するものでＭＯＳ
型半導体＃７Ａｌのゲート電極の寸法を変えることなく
、ポリシリコンのエッチ残漬をＭｔすることのできるＭ
ＯＳ型半導体装置の製造方法を提供することを目的とす
るものである。The present invention solves the above-mentioned conventional problems.
M that can reduce the etching residue of polysilicon to Mt without changing the dimensions of the gate electrode of type semiconductor #7Al.
It is an object of the present invention to provide a method for manufacturing an OS type semiconductor device.
課題を解決するための手段
上記問題点を解決するため、本発明のＭＯＳ型半導体装
置の製造方法は、ポリシリコン膜の酸化工程前に、耐酸
化性被膜でポリシリコン膜からなるゲート電極の表面部
を覆う処理を施すものである。Means for Solving the Problems In order to solve the above problems, the method for manufacturing a MOS type semiconductor device of the present invention includes coating the surface of a gate electrode made of a polysilicon film with an oxidation-resistant film before the oxidation process of the polysilicon film. This is a process that covers the area.
さらに、本発明は、ゲート電極の表面部を耐酸化性被膜
で習う工程として、ポリシリコン膜上に耐酸化性被膜を
成長させる工程と、前記耐酸化性被膜およびポリシリコ
ン膜を所定のゲート電極パターンに形成する工程と、前
記耐酸化性被膜上にさらに耐′ｆａ（を性被膜を形成し
たのち上記耐酸化性被膜を所望形状にエツチングする工
程を罷えたものである。Furthermore, the present invention includes a step of growing an oxidation-resistant film on a polysilicon film, and a step of growing the oxidation-resistant film on a polysilicon film, and applying the oxidation-resistant film and polysilicon film to a predetermined gate electrode. This method consists of the steps of forming a pattern, and further forming a FA-resistant film on the oxidation-resistant film, and then etching the oxidation-resistant film into a desired shape.
作用
上記構成によれば、ポリシリコンからなるゲート電極の
表面部を耐酸化性被膜で覆うことで、ゲート電極の表面
部が酸化されず、ゲート寸法が酸化により減少すること
なく、ポリシリコン膜のエッチ残漬を酸化することがで
きる。Effect According to the above structure, by covering the surface portion of the gate electrode made of polysilicon with an oxidation-resistant film, the surface portion of the gate electrode is not oxidized, the gate dimensions are not reduced due to oxidation, and the polysilicon film is Etch residue can be oxidized.
実施例
以下本発明の一実施例について図面を参照しながら説明
する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（ｄ）は、本発明の一実施例におけるＭ
ＯＳ型半導体装置の製造方法の一部分の工程断面図を示
す、第１図において、１はシリコン基板、２は素子分離
領域、３は拡散層、４はゲート酸化膜、５はポリシリコ
ン膜、６は耐酸化性被膜、としての窒化シリコン膜７は
レジスト膜である。FIGS. 1(a) to 1(d) show M in an embodiment of the present invention.
In FIG. 1, which shows a cross-sectional view of a part of the method for manufacturing an OS type semiconductor device, 1 is a silicon substrate, 2 is an element isolation region, 3 is a diffusion layer, 4 is a gate oxide film, 5 is a polysilicon film, and 6 is a silicon substrate. is an oxidation-resistant film, and the silicon nitride film 7 is a resist film.
゛まず、シリコン基板１に既知の技術にて厚い酸化膜の
素子分離領域２を形成する。次に、シリコン基板１の中
にイオン注入を行い、しきい値電圧を設定する拡散層３
を形成する。この後、ゲート酸化膜４を成長させ、その
上にゲート電極となるポリシリコン膜５を成長させる。``First, an element isolation region 2 of a thick oxide film is formed on a silicon substrate 1 using a known technique. Next, ions are implanted into the silicon substrate 1 to form a diffusion layer 3 for setting the threshold voltage.
form. Thereafter, a gate oxide film 4 is grown, and a polysilicon film 5 that will become a gate electrode is grown thereon.
ついで、ポリシリコン膜５にリンを高ｉ１度に気相拡散
し低抵抗膜とする。ついで、リンガラス化したポリシリ
コン犠を選択除去した後、窒化シリコン躾６を周知のＣ
ＶＤ法にて厚さ０．１μｍに成長させる。さらに、光露
光技術、電子ビーム露光技術、Ｘ線露光技術、あるいは
イオンビーム露光技術を用いてレジスト膜７を所望のレ
ジストパターンに形成し、このレジストパターンをマス
クとして、窒化シリコン膜６とポリシリコンＷＡ５をそ
れぞれドライエッチにより選択除去しゲート電極パター
ンとする。このときの状態は第１図（ａ）に示される。Next, phosphorus is vapor-phase diffused into the polysilicon film 5 to a high degree of i1 to form a low resistance film. Next, after selectively removing the polysilicon sacrificial material that has been turned into phosphor glass, the silicon nitride layer 6 is heated using a well-known C.
It is grown to a thickness of 0.1 μm using the VD method. Furthermore, the resist film 7 is formed into a desired resist pattern using light exposure technology, electron beam exposure technology, X-ray exposure technology, or ion beam exposure technology, and using this resist pattern as a mask, the silicon nitride film 6 and polysilicon WA5 is selectively removed by dry etching to form a gate electrode pattern. The state at this time is shown in FIG. 1(a).
次に、レジスト膜７を除去し第１図（ｂ）に示すように
、ＣＶＤ法により窒化シリコン模６を厚さ０．１μｍに
成長させる。次に、第１図（Ｃ）に示すように、窒化シ
リコン躾６を異方性エツチングし、ポリシリコン膜５か
らなるゲート電極の上面部および側壁部に窒化シリコン
膜６を残す。さらに、第１図（ｄ）において、素子分離
領域２のエツジ部の段差部などで除去しきれなかったポ
リシリコン膜５のエッチ残漬がポリシリコン同居間の電
気的短絡の原因とならぬように、熱酸化法を用いてポリ
シリコン膜５のエッチ残渣を酸化し、絶縁物とする。以
降は公知の技術にて、ＭＯＳ型半導体装置を形成するこ
とができる。Next, the resist film 7 is removed and, as shown in FIG. 1(b), a silicon nitride pattern 6 is grown to a thickness of 0.1 μm by CVD. Next, as shown in FIG. 1C, the silicon nitride film 6 is anisotropically etched to leave the silicon nitride film 6 on the upper surface and sidewalls of the gate electrode made of the polysilicon film 5. Furthermore, in FIG. 1(d), the remaining polysilicon film 5 that could not be removed due to the steps at the edges of the element isolation region 2 is prevented from causing an electrical short circuit between the polysilicon layers. Next, the etch residue on the polysilicon film 5 is oxidized using a thermal oxidation method to form an insulator. Thereafter, a MOS type semiconductor device can be formed using a known technique.
なお、本実施例では、ポリシリコン膜からなるゲート電
極の表面部を覆う耐酸化性被膜として、窒化シリコンを
用いたが、炭化シリコン、酸化アルミ等の耐酸化性を有
する被膜であれば有効であることは言うまでもない。In this example, silicon nitride was used as the oxidation-resistant film covering the surface of the gate electrode made of polysilicon film, but any oxidation-resistant film such as silicon carbide or aluminum oxide would be effective. It goes without saying that there is.
このように本実施例によれば、ポリシリコンからなるゲ
ート電極の表面部および側壁部を耐酸イヒ性被膜で覆う
ことで、ゲート電極の表面部が酸化されず、ＭＯＳ型半
導体装置のゲート電極の電気抵抗値を変えることなく、
さらにゲートバーズビーク形状となることがないので、
ゲート長が減少するようなことはなく、エッチ残漬を酸
化して絶縁物とすることができる。As described above, according to this embodiment, by covering the surface and sidewalls of the gate electrode made of polysilicon with the acid-resistant film, the surface of the gate electrode is not oxidized and the gate electrode of the MOS type semiconductor device is protected from oxidation. without changing the electrical resistance value.
Furthermore, since the gate does not have a bird's beak shape,
The gate length does not decrease, and the etch residue can be oxidized to form an insulator.
発明の効果
以上本発明のＭＯＳ型半導体装置の￥Ｊ造方法によれば
、ポリシリコン膜からなるゲート電極の表面部を酸化す
ることなく、ポリシリコン膜のエッチ残漬を酸化するこ
とができ、ゲート電極の電気抵抗値が変わらない製造方
法を提供することができ、特に、高集積度回路の超微細
半導体装置の形成などにおいて優れている。Effects of the Invention According to the method for manufacturing a MOS type semiconductor device of the present invention, the etched residue of the polysilicon film can be oxidized without oxidizing the surface portion of the gate electrode made of the polysilicon film. It is possible to provide a manufacturing method in which the electrical resistance value of the gate electrode does not change, and is particularly excellent in the formation of ultrafine semiconductor devices of highly integrated circuits.
第１図（ａ）〜（ｄ）は本発明の一実施例におけるＭＯ
Ｓ型半導体装置の製造方法の工程を説明する断面図、第
２図（ａ）（ｂ）は従来のＭＯＳ型半導体装置の製造方
法の工程を説明する断面図である。
１・・・シリコン基板、２・・・素子分離領域、３・・
・拡散層、４・・・ゲート酸イヒ膜、５・・・ポリシリ
コン膜、６・・・窒化シリコン税（耐酸化性被膜）、７
・・・レジスト膜。
代理人 森 本 義 弘
第１図そのｌ
第１因その２
第２図
／９ ｔＱFIGS. 1(a) to 1(d) show MO in one embodiment of the present invention.
FIGS. 2(a) and 2(b) are cross-sectional views illustrating steps in a conventional method for manufacturing an S-type semiconductor device. FIGS. 1... Silicon substrate, 2... Element isolation region, 3...
・Diffusion layer, 4... Gate acid film, 5... Polysilicon film, 6... Silicon nitride layer (oxidation resistant film), 7
...Resist film. Agent Yoshihiro Morimoto Figure 1 Part 1 Cause 1 Part 2 Figure 2/9 tQ
Claims (1)
ト電極の表面部を耐酸化性被膜で覆った後、熱酸化を行
うＭＯＳ型半導体装置の製造方法。 ２、ゲート電極の表面部を耐酸化性被膜で覆う工程とし
て、ポリシリコン膜上に耐酸化性被膜を成長させる工程
と、前記耐酸化性被膜およびポリシリコン膜を所定のゲ
ート電極パターンに形成する工程と、前記耐酸化性被膜
上にさらに耐酸化性被膜を形成したのち上記耐酸化性被
膜を所望形状にエッチングする工程とを備えた請求項１
記載のＭＯＳ型半導体装置の製造方法。[Claims] 1. A method for manufacturing a MOS semiconductor device, in which the surface of a gate electrode made of a polysilicon film of the MOS semiconductor device is covered with an oxidation-resistant film, and then thermally oxidized. 2. The step of covering the surface of the gate electrode with an oxidation-resistant film is a step of growing the oxidation-resistant film on the polysilicon film, and forming the oxidation-resistant film and the polysilicon film into a predetermined gate electrode pattern. and a step of further forming an oxidation-resistant film on the oxidation-resistant film and then etching the oxidation-resistant film into a desired shape.
A method of manufacturing the described MOS type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8689988A JPH01258471A (en) | 1988-04-08 | 1988-04-08 | Manufacture of mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8689988A JPH01258471A (en) | 1988-04-08 | 1988-04-08 | Manufacture of mos type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01258471A true JPH01258471A (en) | 1989-10-16 |
Family
ID=13899682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8689988A Pending JPH01258471A (en) | 1988-04-08 | 1988-04-08 | Manufacture of mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01258471A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008514019A (en) * | 2004-09-21 | 2008-05-01 | フリースケール セミコンダクター インコーポレイテッド | Semiconductor device and method of forming the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6248071A (en) * | 1985-08-28 | 1987-03-02 | Nec Corp | Manufacture of mis field effect transistor |
| JPS62216268A (en) * | 1986-03-17 | 1987-09-22 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1988
- 1988-04-08 JP JP8689988A patent/JPH01258471A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6248071A (en) * | 1985-08-28 | 1987-03-02 | Nec Corp | Manufacture of mis field effect transistor |
| JPS62216268A (en) * | 1986-03-17 | 1987-09-22 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008514019A (en) * | 2004-09-21 | 2008-05-01 | フリースケール セミコンダクター インコーポレイテッド | Semiconductor device and method of forming the same |
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