JPH01258171A - Down loading circuit for distributed processing processor - Google Patents

Abstract

PURPOSE:To suppress the increase of the loading time accompanied with the increase of the number of distributed processing processors by outputting the contents of a memory onto a bus in accordance with the AND output of data requesting signals of respective distributed processing processors. CONSTITUTION:An AND gate 8 operates AND of data requesting signals sent from plural distributed processing processors 2, 3, and 4 which have the same function to execute processings, and programs and data are stored in a memory 1, and stored contents of the memory are outputted onto a bus 10 in accordance with the AND output of the AND gate 8, and responding signals to data requesting signals are outputted to plural distributed processing processors 2, 3, and 4 by one signal line 11. Thus, programs and data are simultaneously loaded to respective distributed processing processors 2, 3, and 4, and loading is scarcely affected by the number of distributed processing processors 2, 3, and 4, and the loading time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a distributed processing system, and particularly to downloading programs and data to distributed processing 7o processors having the same functions.

(Prior Art) Conventionally, in this type of distributed processing system, a ROM is provided on the distributed processing processor side to store a putro loader program.
Each distributed processing processor independently accesses the memory on the main processor side to load programs and data.

(Problems to be Solved by the Invention) In the above-mentioned conventional download circuit for distributed processing processors, each distributed processing processor receives programs and data independently.

Therefore, there is a drawback that the loading time of programs and data increases in proportion to the number of distributed processing processors.

An object of the present invention is to obtain an AND output tube of data request signals of each distributed processing processor, output the contents of the memory on a path by the AND output, and simultaneously send a response signal of the data request signal to a plurality of distributed processing processors. An object of the present invention is to provide a download circuit for a distributed processing processor configured to eliminate the above-mentioned drawbacks and to suppress an increase in load time due to an increase in the number of distributed processing 10 sensors. .

(Means for Solving the Problems) A download circuit for a distributed processing processor according to the present invention is a
It is configured to include an ND gate and a memory.

The AND gate is used to obtain the logical product of data request signals sent 6' from a plurality of distributed processing processors having the same function and executing processing.

The memory stores programs and data, outputs the stored contents to the output of the logical product onto the bus, and outputs the response signal of the data request signal to multiple distributed processing processors via a single signal line. It is for the purpose of

(Example) Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a download circuit for a distributed processing processor according to the present invention.

In FIG. 1, 1 is a memory, 2 to 4 are distributed processing processors, and 8 is an AND gate.

Memory l stores programs and data, and distributed processing processors 2 to 4 send data request signals to signal lines 5 to 4, respectively.
7 and has the same function. A
ND gate 8 obtains the AND of the data request signals on signal lines 5 to 7 and sends the result onto signal line 9 as a read request signal.

The bus 10 is the next one that connects the distributed processing processors 2 to 4 as components and the memory l, and when the read request signal on the signal line 9 is being sent, a bus use permission signal is sent on the signal line ll. YoV.

Distributed processing processors 2 to 4 are connected to memory 1.

The bus use permission signal on the signal line 11 is sent out onto the signal line 12 via a buffer, and is input to the distributed processing processor as a response signal to the data request signal. When the permission signal on signal line 13 is applied to distributed processing processor 2, an address is outputted from one distributed processing processor 2 onto bus 10.

FIG. 2 is a timing chart showing operation signal waveforms of each part in FIG. 1.

Hereinafter, one aspect of the present invention will be explained in detail.

When distributed processing processors 2 to 4 require programs and data, 1 signal line 5 is connected from distributed processing processors 2 to 4 to
A data request signal is sent onto .about.7. AND gate 8
Then, the data request signals are ANDed to generate a read request signal and output onto the signal line 9.

In response to the read request signal input via the signal line 9, the memory l waits for connection preparation with the bus 10 to be completed, outputs a bus use permission signal onto the signal line 11, and outputs the bus use permission signal onto the signal line 12. The distributed processing processors 2 to 4 are notified as a response signal.

Among the distributed processing processors 2 to 4, only the distributed processing processor 2 designated as the representative by the permission signal on the signal line 13 outputs an address signal for the memory l to the bus lO.

According to the address signal on the bus 10, the memory 1 outputs the data stored at the address on the bus 10.

Distributed processors 2-4 take over the data on bus 10 at the trailing end of the response signal on signal line 12, and turn off the data request signal on signal lines 5-7.

By repeating the above operations, the download is completed.

In this embodiment, the number of distributed processing processors is three, but it is clear that similar control is possible even when the number of distributed processing processors is increased.

(Effects of the Invention) As explained above, the present invention can shorten the loading time by loading programs and data to each distributed processing processor at the same time without being affected by the number of V1 distributed processing processors. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a download circuit for a distributed processing processor according to the present invention. FIG. 2 is a timing chart showing operation signal waveforms in each part of FIG. 1. 1...Memories 2-4...Distributed processing processor 8...AND gates 5-7, 9.11-13...Signal line l O...Nox patent applicant NEC Corporation

Claims (1)

[Claims] an AND gate for obtaining a logical product of data request signals sent from a plurality of distributed processing processors having the same function and for executing processing; and an AND gate for storing a program and data; The distributed processor is characterized in that it is configured to include a memory for outputting the contents of the data request signal onto a bus, and a memory for outputting a response signal of the data request signal to the plurality of distributed processing processors via one signal line. Download circuit for processing processor.