JP2740183B2 - Download circuit for distributed processing processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a distributed processing system, and more particularly to downloading programs and data to distributed processing processors having the same function.

(Prior art) Conventionally, this type of distributed processing system has a ROM on the distributed processing processor side and stores a put loader program,
Each distributed processor independently accesses the memory of the main processor to load programs and data.

(Problems to be Solved by the Invention) In the above-described download circuit of the conventional distributed processing processor, each distributed processing processor receives a program and data independently.

Therefore, there is a disadvantage that the load time of programs and data increases in proportion to the number of distributed processing processors.

An object of the present invention is to obtain a logical product output of a data request signal of each distributed processing processor, output the contents of the memory onto the bus by the logical product output, and simultaneously transmit a response signal of the data request signal to a plurality of distributed processing processors. It is an object of the present invention to provide a download circuit for a distributed processing processor configured to eliminate the above-mentioned drawback by notifying by one signal line, and to suppress an increase in load time due to an increase in the number of distributed processing processors.

(Means for Solving the Problems) A download circuit for a distributed processing processor according to the present invention obtains a logical product of data request signals sent from a plurality of distributed processing processors for executing processing with the same function. And a program and data, and a response signal to the data request signal is set to 1
A memory for outputting to the plurality of distributed processing processors with the signal lines, wherein the memory outputs the response signal according to the output of the logical product, and a distributed processing processor designated as a representative outputs an address signal to the memory. On the bus, the memory outputs the data stored in the address signal on the bus, and each distributed processing processor takes the data on the bus at the end of the response signal and turns off the data request signal. Thus, a program or data is simultaneously loaded into each distributed processing processor.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a download circuit for a distributed processing processor according to the present invention.

In FIG. 1, 1 is a memory, 2 to 4 are distributed processing processors, and 8 is an AND gate.

The memory 1 stores programs and data, and the distributed processing processors 2 to 4 transmit data request signals to signal lines 5 respectively.
7 and have the same function.
The AND gate 8 obtains the logical product of the data request signals on the signal lines 5 to 7 and sends it out as a read request signal on the signal line 9. The bus 10 is composed of distributed processing processors 2 to 4 as constituent elements.
And the distributed processing processors 2 to 4 are connected to the memory 1 by the bus use permission signal on the signal line 11 when the read request signal on the signal line 9 is transmitted. . The bus use permission signal on the signal line 11 is sent out on the signal line 12 via a buffer, and is input to the distributed processing processor as a response signal to the data request signal. Signal line 13
When the above permission signal is applied to the distributed processing processor 2, an address is output from the distributed processing processor 2 onto the bus 10.

FIG. 2 is a timing chart showing the operation signal waveform of each part in FIG.

 Hereinafter, the operation of the present invention will be described.

When the distributed processing processors 2 to 4 need a program and data, a data request signal is sent from the distributed processing processors 2 to 4 to signal lines 5 to 7. AND gate 8
Then, the logical AND of the data request signal is taken, a read request signal is generated and output on the signal line 9.

According to the read request signal input via the signal line 9,
The memory 1 waits for completion of preparation for connection to the bus 10 and outputs a bus use permission signal on the signal line 11 and notifies the distributed processing processors 2 to 4 of the bus use permission signal as a response signal on the signal line 12. Of the distributed processors 2 to 4, only the distributed processor 2 designated as a representative by the permission signal on the signal line 13 outputs an address signal for the memory 1 to the bus 10. In accordance with the address signal on the bus 10, the memory 1 outputs the data stored at the address on the bus 10.

The distributed processors 2 to 4 take the data on the bus 10 at the end of the response signal on the signal line 12 and turn off the data request signals on the signal lines 5 to 7.

The download is completed by repeating the above operation.

In this embodiment, the number of distributed processing processors is set to three. However, it is apparent that the same control can be performed when the number of distributed processing processors is increased.

(Effects of the Invention) As described above, according to the present invention, by loading a program and data to each distributed processing processor at the same time, the load time can be reduced without being largely affected by the number of distributed processing processors. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a download circuit for a distributed processing processor according to the present invention. FIG. 2 is a timing chart showing an operation signal waveform in each part of FIG. 1 Memory 2-4 Distributed processing processor 8 AND gate 5-7,9,11-13 Signal line 10 Bus

Claims (1)

(57) [Claims] An AND gate for obtaining a logical product of data request signals sent from a plurality of distributed processing processors for executing processing with the same function, and a program and data are stored therein. A memory for outputting a response signal to the data request signal to the plurality of distributed processing processors via one signal line, wherein the memory outputs the response signal by outputting the logical product, and A processing processor outputs an address signal for the memory on a bus, the memory outputs data stored in the address signal on a bus, and each distributed processing processor outputs data on the bus at a rear end of the response signal. By taking off the data request signal, a program or data is simultaneously loaded to each distributed processing processor. Distributed processing processor for downloading circuit to be.