JPH0628179A - Computer system - Google Patents

Abstract

PURPOSE:To speed up the processing by minimizing the number of signal lines. CONSTITUTION:A ROM device 12 has an address counter, and when a program readout control signal Pr that a central processor 11 sends out through a signal line 201, is received, the device reads a program out of a program storage area as an address counter indicates and sends it out to a central processor 11 through a program-only data bus 203 and counts up the address counter. Further, when a head address setting signal Pa sent out by the central processor 11 is received through a signal line 202, the value of the address counter is reset to a specific value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a computer system,
In particular, a read-only storage device (RO
M computer).

[0002]

2. Description of the Related Art An ordinary computer system includes a central processing unit for executing arithmetic processing and control processing for various devices, a read-only storage device for storing programs, a read / write storage device for storing data, It is composed of an input / output device that controls the input / output of data to the outside
Each device is connected via a control bus for control signals, an address bus for address signals, and a data bus for data signals.

However, in such a general computer system, data for reading a program and data for writing / reading and inputting / outputting data are required.
Since one data bus is shared, the computer system cannot be speeded up.

Therefore, in order to overcome such a drawback, a computer system as shown in FIG. 3 is used. That is, the central processing unit 21, the read / write storage device (hereinafter referred to as RAM device) 23, and the input / output device 24.
Are connected to each other by a general-purpose control bus, an address bus, and a data bus, as in a normal computer system, but a central processing unit 21 and a read-only storage device for storing programs (hereinafter referred to as a ROM device). Called)
A dedicated control bus 211, a dedicated address bus 212, and a dedicated data bus 213 are connected to each other via 22.

As described above, the dedicated bus for reading the program from the ROM device is provided and is separated from the bus system for other various signals, so that the speed of the computer system is increased.

[0006]

In the above-mentioned conventional computer system, in order to increase the speed, a dedicated bus for reading the program from the ROM device is provided and is separated from the bus system for other various signals. However, the number of signals increases as a computer system in order to provide a dedicated bus,
In the worst case, it will be about twice as large as a normal computer system. Therefore, there is a problem that it is difficult to downsize the system.

It is an object of the present invention to provide a computer system which can minimize the number of signal lines and speed up.

[0008]

A computer system according to the present invention stores at least a central processing unit for executing arithmetic processing and control processing of various devices and an RO for storing the program.
In a computer system including an M device, the ROM
The device has an address counter that counts up in response to a program read control signal sent from the central processing unit and also receives an initial address setting signal sent from the central processing unit and sets a count value to a specified value. Is configured. Further, the central processing unit and the RO
Between the M device, the signal line of the program read control signal, the signal line of the head address setting signal, and the RO
The M-unit is connected by a dedicated data bus for transmitting the program read by the M-unit to the central processing unit.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and like a normal computer system, a central processing unit 11 which executes arithmetic processing and control processing of various devices,
It comprises a ROM device 12 for storing programs, a RAM device 13 for storing data, and an input / output device 14 for controlling input / output of data to / from the outside.

Here, between the central processing unit 11, the RAM unit 13 and the input / output unit 14, a general-purpose control bus 101, an address bus 102, and a data bus 103 are provided, as in a normal computer system. The data writing / reading and the data input / output are performed via these buses.

Further, the central processing unit 11 and the ROM device 12
Between the signal Pr and the signal Pr for controlling the reading of the program.
A signal line 201 for reading, a signal line 202 for a signal Pa for setting the start address of the program to be read, and a dedicated data bus 203 for the program Pd read from the ROM device 12 are connected.

By the way, the ROM device 12 has an address counter, and the central processing unit 11 has the signal line 201.
When receiving a program read control signal Pr sent via, the program in the program storage area indicated by the address counter is read and the program dedicated data bus 2
The data is sent to the central processing unit 11 via 03 and the address counter is counted up. Further, when the central processing unit 11 receives the head address setting signal Pa transmitted via the signal line 202, the value of the address counter is reset to the designated value.

Next, the operation will be described.

Now, a case of executing the following program example stored in the ROM device 12 will be described.

Program example (1) 1000H: IN ACC, [30H]
[The contents of the I / O address 30H are read into the arithmetic logic circuit in the central processing unit 11. (2) 1001H: AND ACC, 0FH ... [Calculates the logical product of the contents of the arithmetic logic circuit and 0FH. ] (3) 1002H: MOV [5000H], ACC
... [Write contents of arithmetic logic circuit to address 5000H of data storage area. ] (4) 1003H: JMP 1100H ... [Jump to address 1100H of program storage area. Here, 1001H to 1003H represent program storage area addresses of the ROM device.

FIG. 2 is a timing chart of each signal when the above program example is executed. The address counter of the ROM device is set to 1000H in advance.

First, the central processing unit 11 uses the signal line 201.
The program read control signal Pr is transmitted via the. R
The OM device 12 receives the control signal Pr and receives the address 1000.
The program example (1) stored in H is read, the address counter is counted up to 1001H, and the read program Pd is stored in the dedicated data bus 203.
To the central processing unit 11 via.

The central processing unit 11 receives the program Pd, controls the input / output processing unit 14 via the general-purpose buses 101, 102, 103, reads the contents of the I / O address 30H, and outputs the arithmetic logic circuit in the central processing unit. Save to.

Next, the central processing unit 11 again sends out the program read control signal Pr. ROM device 12 stores program example (2) stored at address 1001H
Is read out, the address counter is counted up to 1002H, and is sent to the central processing unit 11 as program data Pd. The central processing unit 11 calculates the logical product of the contents of the arithmetic logic circuit and the direct data specified by the program, and stores the logical product in the arithmetic logic circuit.

Next, the central processing unit 11 again sends the program read control signal Pr. ROM device 12 stores program example (3) stored at address 1002H
Is read out, the address counter is counted up to 1003H, and the program data Pd is stored in the central processing unit 1.
Send to 1. The central processing unit 1 includes general-purpose buses 101, 1
The contents of the arithmetic logic circuit are written to the data storage area address 5000H in the RAM device 13 via 02 and 103.

Next, the central processing unit 11 sends the program read control signal Pr again. ROM device 12 stores program example (4) stored at address 1003H
Is read out, the address counter is counted up to 1004H, and the program data Pd is stored in the central processing unit 1.
Send to 1. The central processing unit 1 recognizes that the program to be executed is a branch instruction, sends out the program read control signal Pr and the head address setting signal Pa, and outputs the branch destination address 1100H to the address counter of the ROM device 12. Set. After that, the ROM device
Upon receiving the program read control signal Pr, the program is read from the program storage area address 1100H.

As described above, the central processing unit 11 and the ROM device 12 have the signal line 201 for the program read control signal and the signal line 202 for the head address setting signal Pa.
Then, the program is executed via the dedicated data bus 203 of the read program.

[0024]

As described above, according to the present invention, the address counter is provided in the ROM device for storing the program, and the program read control signal sent from the central processing unit is counted up in accordance with the address counter. By setting the count value to a specified value by the head address setting signal sent from the central processing unit, the central processing unit and the R
The only signal lines connected to the OM device are the program read control signal line, the head address setting signal line, and the dedicated data bus for the program read from the ROM device. Therefore, the conventional dedicated control bus and The number of dedicated address bus signal lines can be significantly reduced, and the system speed can be increased with the minimum number of signal lines.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an operation of this embodiment.

FIG. 3 is a block diagram showing an example of a conventional computer system.

[Explanation of symbols]

 11 central processing unit 12 read only memory device (ROM device) Pr program read control signal Pa start address setting signal Pd program data 201, 202 signal line 203 program dedicated data bus

Claims (2)

[Claims] 1. A computer system comprising at least a central processing unit that executes arithmetic processing and control processing of various devices and a ROM device that stores a program, wherein the ROM device controls the program read control sent by the central processing unit. A computer system having an address counter which receives a signal and counts up, and which receives an initial address setting signal sent from the central processing unit and sets a count value to a designated value. 2. The computer system according to claim 1, wherein a signal line for the program read control signal, a signal line for the head address setting signal, and the ROM device are provided between the central processing unit and the ROM device. A computer system which is connected by a dedicated data bus for transmitting the program read by the computer to the central processing unit.