JPH01255053A - Memory access device - Google Patents

Abstract

PURPOSE:To obtain a circuit to prevent the contention of asynchronous access from occurring by stopping the counting of a counter means transiently, and making access to a memory by selecting a memory access signal line corresponding to the value of the counter means. CONSTITUTION:A counter 5 repeats the counting of 00-11 periodically, and checks the coincidence of the count value of its own circuit with a signal value from a NAND45. When the counter 5 coincides with the signal values of flags F1-F4, a load is applied, and the count value of the counter 5 is outputted to a decoder 6. The decoder 6 decodes an inputted count value, and outputs RAM access signals S1-S4 via an AND7. The output of the decoder 6 is fed back to a selector 4, and is added on the counter 5 via ANDs 41-44 and the NAND45. And the counting of the counter 5 is stopped transiently while the load is applied on the counter 5, and the input of another flag is waited for a while. Also, the output of the decoder 6 is added on an FF8, and flag clear signals 1-4 are generated, and are fed back to the AND311 of a register 3, then, the access is released at every completion of the access.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a circuit that prevents contention of asynchronous accesses regarding a device that accesses memory asynchronously from multiple requesters. In a device that accesses memory via a selector, the device comprises: holding means holding a plurality of memory access request signal lines; selection means selecting one of the outputs of the holding means;
comprising a counting means for periodically counting the output of the selection means, a decoder for decoding the counted value of the counting means, and an AND for matching the output of the decoding with the holding means, and a value counted by the counting means. When the selection means selects the request signal line indicated by the value decoded by the decoder, the counting of the stitch number means is temporarily stopped and the memory access signal line is selected corresponding to the cough value to access the memory. Configure it to do so.

[Industrial application field]

The present invention relates to a device that asynchronously accesses memory from multiple request sources.

When transmitting subscriber information over a low-rate line, for example 16'Kb, a data converter is used to convert the subscriber information into low-speed data. This conversion device has a random access memory (hereinafter referred to as RAM) as a memory, and subscriber information is temporarily written in the RAM and then read out to transmit data.

These write and read accesses (hereinafter referred to as read/write) are performed randomly from both sides, from the data conversion device side and from the transmission line side, and the access speeds on both sides are different, resulting in various conflicts. I come to do it.

Therefore, such a data conversion device requires a circuit that prevents these various access conflicts.

[Prior Art] FIG. 4 is a diagram showing a RAM access method using a conventional sequence circuit. In the figure, 21 is a flag generating section;
2 is an address generation section, 23 is an address selector, 24 is a RAM, and 25 is a priority assignment section.

The flag generating unit 21 corresponds one-to-one to accesses 1 to n, which are a plurality of accesses, and generates and latches N flags of the request signal.

The address generation unit 22 receives these N flags and independently generates N types of addresses for accesses 1 to n.
24 RAMs are accessed via 23 address selectors.

Note that the flag from the flag generation section 21 is also sent to the priority assignment section 25. These 25 priority assignment units are assigned a priority in advance from access 1, and if different flags are received at the same time, the one with the higher priority will be given priority, and the one with the lower priority will be processed in the meantime. A selection signal for determining the order of operation of the address selectors is output to the address selector 23.

As a result, the address selector 23 generates addresses controlled in the order of the selection signals output from the priority assignment section 25 and accesses the RAM 24.

FIG. 5 is a diagram showing the timing of conventional RAM access.

As shown in FIG. 5, flag 1 is generated in response to access 1, flag 2 is generated in response to access 2, and flag n is generated in response to access n.
Assume that access is performed between Tsl, Ts2, and Tsn after a delay of 100 min. In this case, Tsl, Ts2, Tsn
is a time determined by the processing speed of the device, and is not necessarily constant. Therefore, in RAM access 2, time t2,
In RAM access n, time tn conflicts with RAM access 1, but since flag l has a high priority,
Flag 2 is masked for time L2, and flag N is masked for time tn. Therefore, even if flag 2 and flag N start accessing first, the access is interrupted by flag 1, and flag 1 starts accessing the RAM.

[Problem to be solved by the invention]

As described above, conventionally, there is a problem in that when access 1 conflicts with another access, access 1 masks the other access.

An object of the present invention is to provide a circuit that prevents this asynchronous access conflict.

(Means for solving problems) FIG. 1 is a diagram showing the basic configuration of the present invention.

As shown in the figure, in a device in which a plurality of request sources asynchronously access the memory 2 via a selector 1, 3 is a holding means that holds a plurality of memory access request signal lines, and 4 is a selector. means, and the holding means 3
5 is a counting means that periodically counts the output of the selection means 4; 6 is a decoder that decodes the count value of the counting means 5; be.

The decoded value of the counting means 5 is added to the AND of 7 to find a match between the decoded value 6 and the holding means 3, and the memory 2
It instructs access to.

[For production]

As shown in FIG. 1, in the present invention, a plurality of request signal lines are latched by the holding means 3, one of the outputs is selected by the selection means 4, and in addition to the counting means 5, a periodic After counting, the decoded value is output to the decoder 6, and the value is added to the memory 2 via AND of 7 for access. .

Note that the output of the decoder 6 is fed back to the selection means 1, and the counting of the counting means 5 is temporarily stopped while the request signal line is being input.

〔Example〕

FIG. 2 is a circuit diagram showing one embodiment of the present invention. In the figure, 3 is a register as a holding means, 31.32.33
．． It consists of 4 registers 1 to 4 with 34 identical configurations, and each register is 311 AND, 3
It consists of 12 NANDs and 313 FFs. 4 is a selector as a selection means, consisting of AND of 41, 42, 43, and 44 and NAND of 45; 5 is a counter as a counting means; 6 is a decoder; 7 is NAND; and 8 is FF.

Now, the request signal is flag 1 to flag 4 (hereinafter F1 to F4).
There are four types. For example, assume that Fl is generated and input to the first register. At this time, the signal level of Fl changes from 'LOW' to 'HIGH', and 312 ON.
The output converted from "high" to "°LOW" by AND is added to the FF of 313, and the signal value "00" corresponding to the flag expressed in binary is output and held by counting with the clock. , the corresponding signal value 00'' is set to 4 in selector 4.
Add to 45 NANDs via an AND of 1. Similarly, 3
The second to fourth registers of numbers 2 to 34 are set to “01” at the input of F2.
”, F3 outputs the corresponding signal value of “10”, F4 outputs the signal value of “11°, passes through AND of 42.43.44, and outputs the signal value of 45 NAN
The signals are synthesized at D and input to the terminal °L of the counter 5.

Counter 5 periodically reads 00°, “01”, “10”
, a counter that repeats counting "11" compares the count value of its own circuit with the signal value from the NAND of 45 to check for a match, and when the counter 5 matches the signal value of the flag, a load is added. Instead, the count value of counter 5 is output and added to the decoder 6, decoded by decode 6, and A of 7 is output.
It passes through ND and outputs RAM access signals 81 to S4. □For example, if flag 4 is input, then 5
Assume that the state of the counter of 5 is "OO゛".The state of the counter of 5 is "01", then '10', and when it reaches "11", the operation is temporarily stopped and the state of the counter 5 is "11°". is selected and outputted to the decoder 6.The decoder 6 decodes this binary number "11" and adds it to the AND of 7, matches the output of the fourth register 34 in the AND of 7, and when they match, A selection signal S4 is generated to allow RAM access.

Note that the output of decoder 6 is fed back to selector 4, and
．． 42, 43, and is added to counter 5 via NAND of 44 and 45. While the counter 5 is being loaded, the counting of the counter 5 is temporarily stopped and the input of another flag is waited for a while.

In addition, the output of the decoder 6 is counted in addition to 8OFF to generate flag clear signals 1 to 4,
11, and the access is canceled each time the access ends.

FIG. 3 is a diagram showing the timing of the sequence circuit of the present invention.

Now, assume that access is accessed in the order of access 4 and access 2, and the signal of flag 4 in (B) corresponding to access 4 and having a pulse width TF4 corresponding to the time width of one cycle of the clock is generated. Assume that it is input to the fourth register. This flag 4 signal outputs a signal (C) having a time width TL4 from the fourth register 34 at the falling time. Note that the output is always generated in one-to-one correspondence to the accesses.

At this time, the count value of counter 5 progresses periodically from "00" to "01" to "10" to "11" as shown in (D), and when it reaches 11, which is assigned to flag 4, By adding the loaded and current state signal to the decoder of 6, decoding it, and adding it to the AND of 7, (
The selection signal S4 of (F) is generated and the RAM access 4 of (G) is performed. At the same time, flag clear 4 of (E) is
), the signal generated from the FF 8 is fed back to the counter 4, and access 4 is terminated.

Note that even if the flag 2 shown in (11) of the next access comes during the counting time "TA" of the counter 5 in (D),
The selection signal S2 is not generated until the counter 5 advances to 01. Therefore, the RAM is not accessed, and after a certain waiting time TW2, access to the RAM2 is started.

〔effect〕

According to the circuit of the present invention, it is possible to prevent contention of asynchronous accesses, and it is possible to solve the problem that lower priority accesses are masked by higher priority accesses.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing the timing of the sequence circuit of the present invention, and Fig. 4 is a diagram showing the conventional sequence circuit. RAM access method using circuit FIG. 5 is a diagram showing the timing of conventional RAM access. In the figure, (2) is a selector, 2 is a memory, 3 is a holding means, 4 is a selection means, 5 is a counting means, 6 is a decoder, and 7 is an AND.

Claims (1)

[Claims] A device for asynchronously accessing a memory (2) from a plurality of request sources via a selector (1), comprising: a holding means (3) for holding a plurality of memory access request signal lines; selection means (4) for selecting one of the outputs of means (3);
), a counting means (5) for periodically counting the output of the selection means (4), a decoder (6) for decoding the counted value of the counting means (5), and an output of the decoding (6). AND (7) for matching the holding means (3), and a decoder (6) for the value counted by the counting means (5).
The selection means (
4), the memory access device is characterized in that, when the selection is made in accordance with 4), the counting of the counting means (5) is temporarily stopped, the memory access signal line is selected in response to the value, and the memory (2) is accessed. .