JPH01253990A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPH01253990A JPH01253990A JP8151088A JP8151088A JPH01253990A JP H01253990 A JPH01253990 A JP H01253990A JP 8151088 A JP8151088 A JP 8151088A JP 8151088 A JP8151088 A JP 8151088A JP H01253990 A JPH01253990 A JP H01253990A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- pattern
- wiring pattern
- improved
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 238000007772 electroless plating Methods 0.000 claims abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 12
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 6
- 239000011889 copper foil Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 238000007747 plating Methods 0.000 description 8
- 238000005476 soldering Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000013040 bath agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemically Coating (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は印刷配線板に関し、特にスルホールおよび配線
パターンに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to printed wiring boards, and particularly to through holes and wiring patterns.
従来の印刷配線板のスルホールおよび配線ノくターンの
導体層は第2図に示すように、例えば、無電%銅めっき
In14の上面に電解釦1めつき鳩5を有する構造にな
っていた。As shown in FIG. 2, the conductor layer of the through-holes and wiring nozzles of a conventional printed wiring board has a structure in which, for example, an electroless button 5 is plated on the upper surface of an In14 plated with % copper.
上述した従来の印刷配線板に、導体層の最上層が電解め
っき層となっているため、表面が平滑に仕上がっている
ので、以下の様な欠点がある。Since the above-mentioned conventional printed wiring board has a smooth surface because the uppermost layer of the conductor layer is an electroplated layer, it has the following drawbacks.
1、 エツチングレジストを形成する際に、エツチング
レジストと導電層の密着強度がとれないため微細な回路
パターンを形成することが困難であった。1. When forming an etching resist, it was difficult to form a fine circuit pattern because the adhesion strength between the etching resist and the conductive layer could not be maintained.
2 ソルダレジストと導体層の密着強度がとれないため
、ンルタレジストの耐熱性、耐粂品性および耐浴剤性が
乏しい。2. Because the adhesion strength between the solder resist and the conductor layer cannot be maintained, the heat resistance, kettle resistance, and bath agent resistance of the solder resist are poor.
3、部品実装時にはんだ付は性が悪い。3. Soldering is poor when mounting components.
不発明の目的は、微細な回路パターン形成可能で、耐熱
性、針条品性の良いソルダレジストヲ有し、はんだ付は
性の良い印刷配線板を提供することにある。The object of the invention is to provide a printed wiring board that can form a fine circuit pattern, has a solder resist with good heat resistance and needle quality, and has good soldering properties.
本発明の印刷配線板は、スルホール及び配線パターンの
導体層の最上層として無!解めっき層が設けられている
というものである。The printed wiring board of the present invention has no through-holes or the uppermost layer of the conductor layer of the wiring pattern. A deplating layer is provided.
次に1本発明について図面を参照して説明する。 Next, one embodiment of the present invention will be explained with reference to the drawings.
第1図は、本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
スルホール1および配線パターン2′(パッド9を含む
)の導体層は、絶縁基板8の両面に張られた銅箔3の上
面および絶縁基板8に穿設された孔の内壁面に、第1の
無電解銅めっき層4を2〜5μmの卑さで形成し、第1
の無電解銅めっき層4の上面に電解銅めっき層5を20
〜30μmの厚さで形成し、更に、電解銅めっき層5の
上面に第2の無電解銅めっき層6を、2〜5μmの厚さ
で形成し、その後所定の導電パターンにエツチングする
ことによシ形成されている。その後ソルダレジスト7を
形成することにより、印刷配線板を得る。The conductor layer of the through hole 1 and the wiring pattern 2' (including the pad 9) is formed by forming a first conductor layer on the upper surface of the copper foil 3 stretched on both sides of the insulating substrate 8 and on the inner wall surface of the hole drilled in the insulating substrate 8. An electroless copper plating layer 4 is formed with a thickness of 2 to 5 μm, and the first
Electrolytic copper plating layer 5 is placed on the top surface of electroless copper plating layer 4 for 20 minutes.
A second electroless copper plating layer 6 is formed on the upper surface of the electrolytic copper plating layer 5 to a thickness of 2 to 5 μm, and then etched into a predetermined conductive pattern. Well formed. Thereafter, a printed wiring board is obtained by forming a solder resist 7.
この実施例で仁、配線パターンの幅が150μmの配線
パターンを形成する場合、従来の印刷配線板では、細線
パターンの断線発生率が、5%であったものが、2%に
低減でき歩留りが向上した。In this example, when forming a wiring pattern with a width of 150 μm, the disconnection rate of the thin line pattern was reduced from 5% in the conventional printed wiring board to 2%, and the yield was increased. Improved.
また表1に示す様にはんだ付は性も向上することができ
た。Furthermore, as shown in Table 1, the soldering properties were also improved.
表1
リフロー条件 :150”090秒、235”020秒
はんだ付は条件: 238’03秒フロンルダサンプル
数 =15枚(スルホール数1563孔/枚パッド数
2162個/枚)
表1に示す様に本発明による印刷配線板は、リフロー等
の加熱処理後でもはんだ付は性が優れていることが判る
。Table 1 Reflow conditions: 150'090 seconds, 235'020 seconds Soldering conditions: 238'03 seconds Number of samples = 15 pieces (Number of through holes: 1563 holes/sheet Number of pads: 2162 pieces/sheet) As shown in Table 1. It can be seen that the printed wiring board according to the present invention has excellent soldering properties even after heat treatment such as reflow.
以上説明したように本発明は、スルホールおよび配線パ
ターンの導体層の最上層として無電解めっき層を有して
いるので、配線パターンをエツチングによシ形成する際
に導電層とエツチングレジストの密着性がよいため高密
度に形成できる。まり配線パターンとフルダレシストの
密着性が向上する。更に部品実装時のはんだ付は性も向
上する効果がある。As explained above, the present invention has an electroless plating layer as the uppermost layer of the conductor layer of the through-hole and wiring pattern, so when forming the wiring pattern by etching, the adhesion between the conductive layer and the etching resist is improved. Because of its good properties, it can be formed at high density. This improves the adhesion between the wiring pattern and the filler resist. Furthermore, soldering during component mounting has the effect of improving the soldering properties.
第1図は1本発明の一実施例の縦断面図、第2図は従来
例の縦断面図である。
1・・・スルホール、2.2’・・・配線パターン、3
・・・銅箔、4・・・無電解銅めっき層、5・・・電解
銅めっき層、6・・・無電解銅めっき層、7・・・ソル
ダレジスト、8・・・絶縁基板、9・・・パッド。
代理人 弁理士 内 原 晋
f;2 ”mFIG. 1 is a vertical cross-sectional view of one embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of a conventional example. 1...Through hole, 2.2'...Wiring pattern, 3
... Copper foil, 4 ... Electroless copper plating layer, 5 ... Electrolytic copper plating layer, 6 ... Electroless copper plating layer, 7 ... Solder resist, 8 ... Insulating substrate, 9 ···pad. Agent Patent Attorney Susumu Uchiharaf;2 ”m
Claims (1)
電解めっき層が設けられていることを特徴とする印刷配
線板。A printed wiring board characterized in that an electroless plating layer is provided as the top layer of a conductor layer of through holes and a wiring pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8151088A JPH01253990A (en) | 1988-04-01 | 1988-04-01 | Printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8151088A JPH01253990A (en) | 1988-04-01 | 1988-04-01 | Printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01253990A true JPH01253990A (en) | 1989-10-11 |
Family
ID=13748353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8151088A Pending JPH01253990A (en) | 1988-04-01 | 1988-04-01 | Printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01253990A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05327187A (en) * | 1992-05-18 | 1993-12-10 | Ishihara Chem Co Ltd | Printed circuit board and manufacture thereof |
-
1988
- 1988-04-01 JP JP8151088A patent/JPH01253990A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05327187A (en) * | 1992-05-18 | 1993-12-10 | Ishihara Chem Co Ltd | Printed circuit board and manufacture thereof |
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