JPH04287395A - Electrolytic plating method for multilayered printed board - Google Patents

Electrolytic plating method for multilayered printed board

Info

Publication number
JPH04287395A
JPH04287395A JP5233491A JP5233491A JPH04287395A JP H04287395 A JPH04287395 A JP H04287395A JP 5233491 A JP5233491 A JP 5233491A JP 5233491 A JP5233491 A JP 5233491A JP H04287395 A JPH04287395 A JP H04287395A
Authority
JP
Japan
Prior art keywords
inner layer
multilayer
substrate
layer conductor
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5233491A
Other languages
Japanese (ja)
Inventor
Shigeru Nishizawa
西沢 茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5233491A priority Critical patent/JPH04287395A/en
Publication of JPH04287395A publication Critical patent/JPH04287395A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To provide an electroplating method which can form an electrolytic plated layer having a uniform thickness in the through hole of a multilayered printed board having a high aspect ratio. CONSTITUTION:A multilayered substrate 2 which is formed by piling up printed board forming materials in a multilayered structure and provided with an inner layer conductor 1 formed by opening a through hole 3 is dipped in an electrolytic copper plating bath 7. In the bath 7, an electrode 8 and current supplying section 6 are respectively provided in the bath 7 and to the part of the conductor 1 extended toward the end section of the substrate 2 for performing electrolytic plating on the substrate 2 by supplying an electric current between the section 6 and electrode 8.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は多層プリント基板の電解
メッキ方法に係り、特に高アスペクト比の多層プリント
基板の電解メッキ方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrolytic plating method for multilayer printed circuit boards, and more particularly to an electrolytic plating method for multilayer printed circuit boards with a high aspect ratio.

【0002】電子部品を実装する多層プリント基板は、
益々高密度化が要求されるようになっており、これに伴
って内層導体を多数積層して形成し、かつスルーホール
も穴径の小さい製品が要求され、その結果、高いアスペ
クト比(プリント基板の厚さ/スルーホールの穴の直径
)の多層プリント基板が要求される傾向にある。
[0002] Multilayer printed circuit boards on which electronic components are mounted are
There is a growing demand for higher densities, and this requires products that are formed by laminating many inner layer conductors and have small through holes.As a result, products with high aspect ratios (printed circuit boards) are required. There is a trend toward demand for multilayer printed circuit boards with a thickness of 100 mm/diameter of through-holes).

【0003】0003

【従来の技術】このような多層プリント基板の製造方法
について述べると、図2(a) に示すように、所定の
銅箔パターンを有する基材をプリプレグを介して多数積
層して内層導体1を多数設けた多層基板2を形成し、こ
の多層基板にスルーホール3を穴開けする。
2. Description of the Related Art A method for manufacturing such a multilayer printed circuit board is as shown in FIG. A multilayer substrate 2 having a large number of them is formed, and through holes 3 are formed in this multilayer substrate.

【0004】次いでこの多層基板2を無電解銅メッキ液
に浸漬してスルーホール3内に無電解銅メッキ層4を形
成した後、表面銅箔5を多層基板2の周辺端部に延長し
て電解銅メッキ用の電流供給部6を設ける。次いで、図
2(b)に示すように、この多層基板2を電解銅メッキ
液7内に銅板よりなる電極8と対向させた状態で浸漬し
て設置する。
Next, this multilayer board 2 is immersed in an electroless copper plating solution to form an electroless copper plating layer 4 in the through hole 3, and then a surface copper foil 5 is extended to the peripheral edge of the multilayer board 2. A current supply section 6 for electrolytic copper plating is provided. Next, as shown in FIG. 2(b), this multilayer substrate 2 is immersed in an electrolytic copper plating solution 7 so as to face an electrode 8 made of a copper plate.

【0005】そして電極8が正、多層基板2が負となる
ように両者の間に直流電圧を印加して電解銅メッキをス
ルーホール3内に形成している。
[0005] Electrolytic copper plating is formed in the through holes 3 by applying a DC voltage between the electrodes 8 and the multilayer substrate 2 so that the electrodes 8 are positive and the multilayer substrate 2 is negative.

【0006】[0006]

【発明が解決しようとする課題】然し、図2(a)、図
2(b)に示すように、上記したスルーホール3内に設
ける無電解銅メッキ層4の厚さは1μm 程度と極めて
薄くしか析出されず、多層基板2のアスペクト比が高く
なるに連れて、表面銅箔5の部分に電流供給部6を設け
ると、スルーホール3の穴の深さ方向の中央部近傍では
、上記無電解銅メッキ層4の厚さが極めて薄いために、
電流供給部6からスルーホールの穴の深さ方向の中央部
近傍迄の間の抵抗が大きくなる。そのため、スルーホー
ルの穴の深さ方向の中央部近傍では電流の供給量が少な
くなり、電流密度が低下し、形成される電解銅メッキ層
9の厚さが、スルーホールが多層基板に表出する部分A
よりも薄くなる欠点がある。
[Problems to be Solved by the Invention] However, as shown in FIGS. 2(a) and 2(b), the thickness of the electroless copper plating layer 4 provided in the above-mentioned through hole 3 is extremely thin, about 1 μm. As the aspect ratio of the multilayer board 2 increases, when the current supply section 6 is provided in the surface copper foil 5, the above-mentioned Since the thickness of the electrolytic copper plating layer 4 is extremely thin,
The resistance from the current supply section 6 to the vicinity of the center of the through hole in the depth direction increases. Therefore, the amount of current supplied near the center of the through hole in the depth direction decreases, the current density decreases, and the thickness of the electrolytic copper plating layer 9 that is formed decreases so that the through hole is exposed on the multilayer board. Part A
It has the disadvantage that it is thinner than it is.

【0007】また高アスペクト比の多層基板では、プリ
ント板の厚さが3.2mm に対し、穴の直径が0.3
5mmと極めて小さいために、電解銅メッキが充分に供
給されないので余計に上記した傾向がある。
Furthermore, in a multilayer board with a high aspect ratio, the thickness of the printed board is 3.2 mm, and the diameter of the hole is 0.3 mm.
Due to the extremely small size of 5 mm, electrolytic copper plating is not sufficiently supplied, so there is the above-mentioned tendency.

【0008】また図2(b)に示すように、電極8と多
層基板2の間で電解銅メッキ液7中に生じる電界は図の
11に示すようになり、スルーホールが多層基板に表出
する部分Aの部分や、多層基板の表面の角の部分に集中
する。 そのため、スルーホール3の穴の深さ方向の中央部の電
解銅メッキ層9の厚さは、スルーホールの多層基板に表
出する部分Aより薄くなる傾向があり、スルーホール内
の導通が不完全となり、接続不良な多層プリント基板と
なる欠点がある。
Further, as shown in FIG. 2(b), the electric field generated in the electrolytic copper plating solution 7 between the electrode 8 and the multilayer substrate 2 becomes as shown in FIG. 11, and the through holes are exposed on the multilayer substrate. It concentrates on the part A where the irradiation occurs and the corner parts of the surface of the multilayer substrate. Therefore, the thickness of the electrolytic copper plating layer 9 at the center of the through hole 3 in the depth direction tends to be thinner than the portion A of the through hole exposed on the multilayer board, and the conduction inside the through hole is prevented. This has the disadvantage that it becomes incomplete, resulting in a multilayer printed circuit board with poor connections.

【0009】本発明は上記した欠点を除去し、スルーホ
ールの穴の内壁に均一な厚さの電解銅メッキ層が形成さ
れるようにした多層プリント基板の電解銅メッキ方法の
提供を目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for electrolytic copper plating of a multilayer printed circuit board, which eliminates the above-mentioned drawbacks and forms an electrolytic copper plating layer of uniform thickness on the inner wall of a through hole. .

【0010】0010

【課題を解決するための手段】本発明の多層プリント基
板の電解メッキ方法は、プリント板形成材料を多層構造
に積層し、スルーホールを穴開けして形成した内層導体
を有する多層基板を、電解液中に浸漬するとともに、該
電解液中に電極を設け、前記内層導体を含む領域を基板
の端部方向に選択的に導出して、該内層導体に接続する
電流供給部を設け、前記電極と内層導体より導出された
電流供給部間に通電して多層基板に電解メッキを行うこ
とを特徴とする。
[Means for Solving the Problems] The electrolytic plating method for a multilayer printed circuit board of the present invention is to electrolytically plate a multilayer board having an inner layer conductor formed by laminating printed board forming materials into a multilayer structure and drilling through holes. At the same time, an electrode is provided in the electrolytic solution, a region including the inner layer conductor is selectively led out toward an end of the substrate, and a current supply section is provided to connect to the inner layer conductor. The present invention is characterized in that electrolytic plating is performed on the multilayer substrate by passing current between the current supply portion and the current supply portion led out from the inner layer conductor.

【0011】[0011]

【作用】本発明の方法は内層導体を含む基板領域を、選
択的に基板の端部方向に導出して、該内層導体に接続す
る電流供給部より電解メッキ用の電流を供給する。この
ようにすると電流が最も供給され難いスルーホールの穴
の深さ方向の中央部で、抵抗が無い状態で電流が最も多
く供給されるようになり、均一な厚さで電解銅メッキ層
がスルーホール内の全領域に形成される。
According to the method of the present invention, the substrate region including the inner layer conductor is selectively led out toward the end of the substrate, and a current for electrolytic plating is supplied from a current supply section connected to the inner layer conductor. In this way, the largest amount of current is supplied in the center of the depth direction of the through-hole where it is most difficult to supply current, with no resistance, and the electrolytic copper plating layer is passed through with a uniform thickness. Formed in the entire area within the hole.

【0012】0012

【実施例】以下、図面を用いて本発明の実施例につき詳
細に説明する。図1(a)に示すように、多層基板2に
形成されている内層導体1が形成されている部分のみを
多層基板2の端部より突き出して設ける。このような構
造は、多層基板2を形成した後、該基板の表面と裏面と
を研磨、或いはエッチング等の方法で削って内層導体1
を形成した領域を露出させて、この露出した内層導体の
部分に電解銅メッキ用の電流を供給する電流供給部6を
設ける。
Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. As shown in FIG. 1(a), only the portion of the multilayer substrate 2 where the inner layer conductor 1 is formed is provided so as to protrude from the end of the multilayer substrate 2. As shown in FIG. In this structure, after forming the multilayer substrate 2, the inner layer conductor 1 is removed by polishing or etching the front and back surfaces of the substrate.
A current supply section 6 for supplying current for electrolytic copper plating is provided to the exposed area of the inner layer conductor.

【0013】次いで図1(b)に示すように、この電流
供給部6が負、電極8が正となるようにして電解銅メッ
キ液7に浸漬して電解銅メッキする。このようにすると
、電流が最も供給され難いスルーホール3の穴の深さ方
向の中央部に内層導体1を介して直接電解メッキ用の電
流が供給されるので、スルーホールの穴の深さ方向に沿
って均一な電流密度となるため、均一な厚さの電解銅メ
ッキ層9がスルーホール3内の全領域にわたって形成さ
れる。
Next, as shown in FIG. 1(b), electrolytic copper plating is performed by immersing it in an electrolytic copper plating solution 7 with the current supply section 6 being negative and the electrode 8 being positive. In this way, the current for electrolytic plating is directly supplied via the inner layer conductor 1 to the central part of the through hole 3 in the depth direction where it is most difficult to supply current, so Since the current density is uniform along the through hole 3, an electrolytic copper plating layer 9 having a uniform thickness is formed over the entire area within the through hole 3.

【0014】なお、本実施例では電解銅メッキに例を用
いて述べたが、電解半田メッキのようにプリント基板の
電解メッキの場合に於いて、総て適用できる。
Although this embodiment has been described using electrolytic copper plating as an example, the present invention can be applied to any electrolytic plating of printed circuit boards such as electrolytic solder plating.

【0015】[0015]

【発明の効果】以上述べたように、本発明の方法によれ
ば、電流が最も供給され難いスルーホールの穴の深さ方
向の中央部に、抵抗が無い状態で最も多くの電流が供給
され、スルーホールの穴の深さ方向に沿って電解メッキ
用の電流が均一に供給されるので、スルーホール内に形
成される電解銅メッキ層の厚さが均一となり、断線を生
じない高信頼度の高アスペクト比の多層プリント基板が
得られる効果がある。
[Effects of the Invention] As described above, according to the method of the present invention, the largest amount of current is supplied to the center of the through hole in the depth direction, where it is most difficult to supply current, with no resistance. Since the current for electrolytic plating is uniformly supplied along the depth direction of the through-hole, the thickness of the electrolytic copper plating layer formed inside the through-hole is uniform, resulting in high reliability with no disconnection. This has the effect of producing a multilayer printed circuit board with a high aspect ratio.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明の方法の実施例の説明図である。FIG. 1 is an explanatory diagram of an embodiment of the method of the present invention.

【図2】  従来の方法の説明図である。FIG. 2 is an explanatory diagram of a conventional method.

【符号の説明】[Explanation of symbols]

1  内層導体 2  多層基板 3  スルーホール 4  無電解銅メッキ層 5  表面銅箔 6  電流供給部 7  電解銅メッキ液 8  電極 9  電解銅メッキ層 1 Inner layer conductor 2 Multilayer board 3 Through hole 4 Electroless copper plating layer 5 Surface copper foil 6 Current supply section 7 Electrolytic copper plating solution 8 Electrode 9 Electrolytic copper plating layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  プリント板形成材料を多層構造に積層
し、スルーホール(3)を穴開けして形成した内層導体
(1) を有する多層基板(2) を、電解液(7) 
中に浸漬するとともに、該電解液(7) 中に電極(8
) を設け、前記内層導体(1) を含む領域を基板の
端部方向に選択的に導出した箇所に、該内層導体に接続
する電流供給部(6) を設け、前記電極(8) と内
層導体(1) より導出された電流供給部(6) 間に
通電して多層基板(2) に電解メッキを行うことを特
徴とする多層プリント基板の電解メッキ方法。
Claim 1: A multilayer board (2) having an inner layer conductor (1) formed by laminating printed board forming materials into a multilayer structure and forming through holes (3), and an electrolytic solution (7)
At the same time, the electrode (8) is immersed in the electrolyte (7).
) is provided, and a current supply section (6) connected to the inner layer conductor is provided at a location where the region including the inner layer conductor (1) is selectively drawn out toward the end of the substrate, and a current supply section (6) connected to the inner layer conductor is provided, and a current supply section (6) connected to the inner layer conductor is provided at a location where the region including the inner layer conductor (1) is selectively led out toward the end of the substrate. A method for electrolytic plating of a multilayer printed circuit board, characterized in that electrolytic plating is performed on a multilayer circuit board (2) by passing current between a current supply section (6) led out from a conductor (1).
JP5233491A 1991-03-18 1991-03-18 Electrolytic plating method for multilayered printed board Withdrawn JPH04287395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5233491A JPH04287395A (en) 1991-03-18 1991-03-18 Electrolytic plating method for multilayered printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5233491A JPH04287395A (en) 1991-03-18 1991-03-18 Electrolytic plating method for multilayered printed board

Publications (1)

Publication Number Publication Date
JPH04287395A true JPH04287395A (en) 1992-10-12

Family

ID=12911902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5233491A Withdrawn JPH04287395A (en) 1991-03-18 1991-03-18 Electrolytic plating method for multilayered printed board

Country Status (1)

Country Link
JP (1) JPH04287395A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002016332A (en) * 2000-06-28 2002-01-18 Ibiden Co Ltd Laminated board having through hole and its manufacturing method
CN107592755A (en) * 2017-09-07 2018-01-16 信丰文峰电子科技有限公司 A kind of heavy copper method of the pcb board of high aspect ratio

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002016332A (en) * 2000-06-28 2002-01-18 Ibiden Co Ltd Laminated board having through hole and its manufacturing method
CN107592755A (en) * 2017-09-07 2018-01-16 信丰文峰电子科技有限公司 A kind of heavy copper method of the pcb board of high aspect ratio

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Effective date: 19980514