JPH1143797A - Method for via-filling - Google Patents
Method for via-fillingInfo
- Publication number
- JPH1143797A JPH1143797A JP21387397A JP21387397A JPH1143797A JP H1143797 A JPH1143797 A JP H1143797A JP 21387397 A JP21387397 A JP 21387397A JP 21387397 A JP21387397 A JP 21387397A JP H1143797 A JPH1143797 A JP H1143797A
- Authority
- JP
- Japan
- Prior art keywords
- electrolysis
- via hole
- plating
- metal
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000011049 filling Methods 0.000 title claims abstract description 19
- 238000005868 electrolysis reaction Methods 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 238000009713 electroplating Methods 0.000 claims description 13
- 238000007747 plating Methods 0.000 abstract description 33
- 229910052802 copper Inorganic materials 0.000 abstract description 22
- 238000007772 electroless plating Methods 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- 229910052763 palladium Inorganic materials 0.000 abstract description 2
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 229910052718 tin Inorganic materials 0.000 abstract description 2
- 150000002739 metals Chemical class 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 21
- 239000010949 copper Substances 0.000 description 21
- 238000000151 deposition Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 229910021645 metal ion Inorganic materials 0.000 description 4
- 229910000365 copper sulfate Inorganic materials 0.000 description 3
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 238000013019 agitation Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000001376 precipitating effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Electroplating Methods And Accessories (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ビアフィリング方
法に関し、更に詳細には、ブラインドホール等の微小孔
中に金属を充填し、金属ピラーやポストを形成させるビ
アフィリング方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a via-filling method, and more particularly, to a via-filling method in which a metal is filled in a minute hole such as a blind hole to form a metal pillar or a post.
【０００２】[0002]
【従来の技術】最近、携帯電話、パソコン、ビデオ、ゲ
ーム機等の電子機器の回路実装法として、ビルドアップ
工法が適用されるようになってきた。このビルドアップ
工法では、積層板に微小孔（スルーホールやビアホー
ル）が設けられており、この微小孔中に析出させた金属
によって各回路層間の接続が行われる。 この微小孔の
うち、ブラインドの微小孔であるビアホール（以下、
「ビアホール」という）については、ビアホールめっき
やビアフィリングによって各層間の接続が施される。今
後、さまざまな高密度化および多層化のトレンドの中
で、各層間のビアホールの接続信頼性は重要となり、ま
た特に各層の平坦化の要求が高まるものと予測される。2. Description of the Related Art In recent years, a build-up method has been applied as a circuit mounting method for electronic devices such as mobile phones, personal computers, videos, and game machines. In this build-up method, micro holes (through holes and via holes) are provided in the laminated plate, and connection between circuit layers is performed by metal deposited in the micro holes. Via holes (hereinafter referred to as blind holes),
The connection between the layers is made by via-hole plating or via-filling. In the future, with various densification and multi-layer trends, it is expected that the connection reliability of via holes between the layers will become important, and in particular, the demand for flattening the layers will increase.
【０００３】ビアホールの内側面および底面に金属皮膜
を形成させるビアホールめっきでは、穴の上にさらに導
体層を積み上げることは難しく、また、層間接続にあた
って、通電を保証するためには金属皮膜の析出エリアを
増大させなければならない。一方、ビアフィリング法を
用いると穴が完全に埋まり、しかもビアフィリングを行
った後のビアホールの表面が平坦であれば穴の上に穴を
形成できるのでダウンサイジングには有利である。 し
たがって、ビアホールめっきでは絶縁体の平坦化には限
界があり、それゆえ、層間のホールを埋めるいわゆるビ
アフィリングの必要性が高まっている。[0003] In via-hole plating in which a metal film is formed on the inner side surface and the bottom surface of a via hole, it is difficult to further build up a conductor layer on the hole. Must be increased. On the other hand, if the via filling method is used, the hole is completely filled, and if the surface of the via hole after the via filling is flat, the hole can be formed on the hole, which is advantageous for downsizing. Therefore, there is a limit to the planarization of the insulator in via-hole plating, and therefore, the need for so-called via-filling for filling holes between layers has increased.
【０００４】従来のビアフィリングの形成は、絶縁層に
ホールを形成した底部の導体層を活性化し、電気めっき
によってピラー（柱）やポストを形成し、表面に露出し
た析出銅を研磨により平滑化する方法か、あるいは無電
解銅めっきを用いて穴の底部の導体層のみを活性化し、
無電解めっきで選択的に積み上げる方法がとられてい
た。これらの方法を採用すると、いずれにしても次の絶
縁層上にスパッタまたは無電解めっきで導体化処理をし
なければならず、きわめて煩雑な操作となる。[0004] Conventional via filling is performed by activating a conductive layer at the bottom where holes are formed in an insulating layer, forming pillars and posts by electroplating, and smoothing the deposited copper exposed on the surface by polishing. Or activate only the conductor layer at the bottom of the hole using electroless copper plating,
A method of selectively stacking by electroless plating has been adopted. If any of these methods is adopted, in any case, it is necessary to carry out a conductive treatment by sputtering or electroless plating on the next insulating layer, which is an extremely complicated operation.
【０００５】[0005]
【発明が解決しようとする課題】従って、簡単な操作
で、効率よくビアフィリングを形成する方法の開発が求
められていた。Accordingly, there has been a need for the development of a method for efficiently forming a via filling with a simple operation.
【０００６】[0006]
【課題を解決するための手段】本発明者は、ビアホール
を構成する底部の導体層、絶縁壁、表面の絶縁層の上に
まず無電解金属めっきで導体膜を形成した後、電気めっ
きで一定の膜厚を得る方法について検討した。Means for Solving the Problems The present inventor first forms a conductive film by electroless metal plating on the bottom conductive layer, insulating wall, and surface insulating layer constituting the via hole, and then performs constant plating by electroplating. A method of obtaining a film thickness of was examined.
【０００７】そしてその結果、単なる電気めっきでは、
ビアホール中に均一な金属皮膜を形成させることは困難
であるが、陰極と陽極を交換させるＰＲ電解の手法を利
用することによりビアホール中に適度な濃度の金属イオ
ンを存在せしめることができ、均一性の優れた金属皮膜
が形成されることを見出し、本発明を完成した。[0007] As a result, in simple electroplating,
It is difficult to form a uniform metal film in the via hole, but by using the PR electrolysis technique of exchanging the cathode and anode, it is possible to make metal ions of appropriate concentration exist in the via hole, The present inventors have found that a metal film excellent in the above is formed, and completed the present invention.
【０００８】すなわち本発明は、ビアホール中に無電解
金属皮膜を形成した後、ＰＲ電解により金属電気めっき
を行うことを特徴とするビアフィリング方法である。ま
た本発明は、ビアホール中に無電解金属皮膜を形成した
後、まず直流電解により金属電気めっきを行ない、次い
でＰＲ電解で金属電気めっきを行うことを特徴とするビ
アフィリング方法である。That is, the present invention is a via filling method characterized in that after forming an electroless metal film in a via hole, metal electroplating is performed by PR electrolysis. Further, the present invention is a via-filling method characterized in that after forming an electroless metal film in a via hole, metal electroplating is first performed by DC electrolysis, and then metal electroplating is performed by PR electrolysis.
【０００９】[0009]
【発明の実施の形態】本発明方法が適用されるビアホー
ルは、特にその径や深さが限定されるものではないが、
一般には径１０〜１０００μｍ、深さ１０〜１０００μ
ｍ程度のものである。このビアホールは、常法に従って
ビアホールの底部および側面を電導化処理し、次いで電
導化処理した底部および側面に無電解金属めっきを施し
た後、本発明に付される。 このビアホールは、一般に
金属箔と高分子の絶縁層が交互に積層された積層板にお
いて、金属箔間の通電を担うものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS The diameter and depth of a via hole to which the method of the present invention is applied are not particularly limited.
Generally 10 to 1000 μm in diameter and 10 to 1000 μ in depth
m. This via hole is subjected to an electroconductive treatment on the bottom and side surfaces of the via hole in accordance with a conventional method, and then subjected to electroless metal plating on the bottom and side surfaces subjected to the electroconductive treatment, and then applied to the present invention. In general, the via hole serves to conduct electricity between the metal foils in a laminate in which metal foils and polymer insulating layers are alternately stacked.
【００１０】電気めっき層を形成させるためのＰＲ電解
は、当然のことながらビアホール内に金属が析出するよ
うな条件でなければならない。 例えば、電圧が一定で
あれば物品が陰極である時間が長くなるようにしなけれ
ばならない。[0010] PR electrolysis for forming an electroplating layer must, of course, be carried out under such conditions that metal is deposited in the via hole. For example, if the voltage is constant, the time during which the article is a cathode must be increased.
【００１１】本発明方法において、好ましいＰＲの条件
は、析出させる金属の種類、そのための浴組成あるいは
ビアホールの形状（口径、深さ）等によって異なり、実
験的に定めるべきである。 しかし、一般的な条件とし
ては、陰極である時間と陽極である時間は、１：１〜１
０：１程度、好ましくは２：１〜５：１程度の時間割合
で、ＰＲ周期は、１秒〜６００秒程度、好ましくは１０
秒〜１００秒程度、全電解時間は０.１〜１０時間程度
である。 また、ＰＲ電解における電流密度は、特に制
限されるものでなく、各めっき浴における一般的なもの
が採用できる。In the method of the present invention, preferable PR conditions vary depending on the type of metal to be deposited, bath composition therefor or the shape (diameter, depth) of via holes, and should be determined experimentally. However, as a general condition, the time as a cathode and the time as an anode are 1: 1 to 1
At a time ratio of about 0: 1, preferably about 2: 1 to 5: 1, the PR period is about 1 second to 600 seconds, preferably 10 seconds.
The second electrolysis time is about 0.1 to 10 hours. Further, the current density in PR electrolysis is not particularly limited, and a general one in each plating bath can be adopted.
【００１２】本発明が適用可能な金属めっき浴として
は、銅、ニッケル、金、銀、パラジウム、スズやそれら
の合金、例えばはんだ等の電導性金属めっき皮膜が得ら
れるめっき浴が挙げられ、これらを析出することのでき
る種々の浴が特に制限なく利用される。The metal plating bath to which the present invention can be applied includes a plating bath capable of obtaining a conductive metal plating film of copper, nickel, gold, silver, palladium, tin and alloys thereof, such as solder. Various baths capable of precipitating are used without particular limitation.
【００１３】なお、本発明の実施に当たっては、実施当
初からＰＲ電解を行っても良いが、好ましくは一定時間
直流電解を行い、開口部周辺にある程度の金属を析出さ
せてからＰＲ電解を行った方が効率的である。In carrying out the present invention, PR electrolysis may be carried out from the beginning, but preferably, DC electrolysis is carried out for a certain time, and PR electrolysis is carried out after depositing a certain amount of metal around the opening. Is more efficient.
【００１４】[0014]
【作用】穴が小さく、かつ深いビアホール中では、金属
イオン濃度および電流分布が共に不均一であるため、均
一電着性の優れた電気めっき皮膜を形成するためには、
一般的に電流密度を低くするかまたは撹拌を強くしなけ
ればならない。特に金属イオンについては、ビアホール
の穴径が小さくなるほど、また深さが深くなるほど穴へ
めっき液が侵入することに対して外部の流れがあまり効
果を及ぼさなくなるため、ある程度強制的に金属イオン
を供給することが必要となってくる。In a small and deep via hole, both the metal ion concentration and the current distribution are non-uniform, so in order to form an electroplating film having excellent uniform electrodeposition,
Generally, the current density must be low or the agitation must be high. For metal ions in particular, as the hole diameter of the via hole becomes smaller and the depth becomes deeper, the external flow has less effect on the intrusion of the plating solution into the hole. It becomes necessary to do.
【００１５】本発明方法によれば、開口部分に優先的に
析出した金属を、ＰＲ電解で電極を逆転させることによ
り溶解させるものであるため、ビアホール内の析出部位
近傍の金属イオン濃度が常に過剰な状態で電気めっきが
でき、電流密度や撹拌を調整することなしに均一な成膜
が可能で、ビアフィリングが形成できるものである。According to the method of the present invention, the metal deposited preferentially in the opening is dissolved by inverting the electrode by PR electrolysis, so that the metal ion concentration near the deposition site in the via hole is always excessive. Electroplating can be performed in a suitable state, a uniform film can be formed without adjusting the current density and stirring, and a via filling can be formed.
【００１６】[0016]
【発明の効果】以上説明した本発明方法は、電気めっき
法という比較的簡単な手段により実施されるものである
ので、従来に比べ極めて簡単にビアフィリングを行なう
ことができ、種々の回路の製造に極めて有効なものであ
る。The method of the present invention described above is carried out by a relatively simple means of electroplating, so that via filling can be performed much more easily than in the past, and various circuits can be manufactured. It is extremely effective.
【００１７】[0017]
【実施例】次に実施例を挙げ、本発明を更に詳しく説明
するが、本発明はこれになんら制約されるものではな
い。Next, the present invention will be described in more detail with reference to Examples, but the present invention is not limited thereto.
【００１８】実 施 例 １ 硫酸銅めっきによるビアフィリング：下記組成の電気銅
めっき液２ｄｍ3をめっき実験装置のセルに注入し、温
度２５℃、１分間に１００ｍｌ・ｄｍ-3程度の空気撹拌
を行いながら、エキシマレーザーによってテーパー状の
ブラインドビア（開口部穴径６０μｍ、底部４０μｍ、
深さ６０μｍ）を形成した銅張積層板（１０００ｍｍ2
（２０×５０ｍｍ）、厚さ６０ミクロンのエポキシ樹脂
を絶縁層としてコーティング）に銅めっきを施した。EXAMPLE 1 Via Filling by Copper Sulfate Plating: An electrolytic copper plating solution (2 dm 3) having the following composition was injected into a cell of a plating experiment apparatus, and the air was stirred at a temperature of 25 ° C. and about 100 ml · dm -3 for 1 minute. While performing, a tapered blind via (opening hole diameter 60 μm, bottom 40 μm,
Copper-clad laminate (1000 mm 2 ) having a depth of 60 μm
(20 × 50 mm), coated with an epoxy resin having a thickness of 60 μm as an insulating layer).
【００１９】銅めっきは、下記条件で、直流、パルスお
よびＰＲ電解の３種類を行った。また、陽極には含りん
銅（チタンケース、アノ−ドパック使用）を使用し、陽
極と陰極間の距離は５０ｍｍに固定した。Three types of copper plating, DC, pulse and PR electrolysis, were performed under the following conditions. The anode was made of phosphorous copper (using a titanium case and an anode pack), and the distance between the anode and the cathode was fixed at 50 mm.
【００２０】ブラインドビアを形成した銅張積層板は、
慣用の手段により、過マンガン酸塩による樹脂エッチン
グ、キャタライジング、アクセラレーティングを行い、
無電解銅めっき（シプレイ社製、＃２５３）を約０.５
ミクロン施すことにより前処理を行った。電気銅めっき
皮膜の析出状態は、クロスカットした試料の走査型電子
顕微鏡観察の結果から評価した。The copper clad laminate having the blind vias formed therein
Perform resin etching with permanganate, catalyzing, and accelerating by conventional means,
Electroless copper plating (# 253, manufactured by Shipley) is about 0.5
Pretreatment was performed by applying a micron. The deposition state of the electrolytic copper plating film was evaluated from the results of scanning electron microscope observation of the cross-cut sample.
【００２１】 ［硫酸銅めっき液組成］ 硫 酸 銅 ０.２４ｍｏｌ／ｄｍ-3 硫 酸 １.８４ｍｏｌ／ｄｍ-3 塩化ナトリウム １００ｍｇ／ｄｍ-3 添 加 剤 ＨＬ（アトテック社製光沢剤） ２０ｍｌ／ｄｍ-3 ＧＳ（アトテック社製光沢剤） ０.２ｍｌ／ｄｍ-3 [Composition of Copper Sulfate Plating Solution] Copper sulfate 0.24 mol / dm -3 Sulfuric acid 1.84 mol / dm -3 Sodium chloride 100 mg / dm -3 Additive HL (Brightener manufactured by Atotech) 20 ml / dm -3 GS (brightener manufactured by Atotech) 0.2 ml / dm -3
【００２２】［めっき条件］ （１）直流電解 電流密度１.２Ａ・ｄｍ-2 電解時間６０分間 （２）パルス電解 電流密度３.６Ａ・ｄｍ-2 直流電解を１ミリ秒（ｍｓ）、休止を２ミリ秒 （３）ＰＲ電解 電流密度１.２Ａ・ｄｍ-2 カソード電解で約１０ミクロンの皮膜を形成させた後、
上記電流密度でカソード電解６０秒、アノード電解３０
秒のサイクルでＰＲ電解[Plating conditions] (1) DC electrolysis Current density: 1.2 A · dm −2 Electrolysis time: 60 minutes (2) Pulse electrolysis: Current density: 3.6 A · dm −2 DC electrolysis is suspended for 1 millisecond (ms) (3) PR electrolysis After forming a film of about 10 microns by cathodic electrolysis with a current density of 1.2 A · dm -2 ,
At the above current density, cathodic electrolysis 60 seconds, anodic electrolysis 30
PR electrolysis in a cycle of seconds
【００２３】［実験結果］めっき前のビアホール、直流
電解で電気銅めっきを行ったときのビアホール内への析
出状態およびパルス電解で電気銅めっきを行ったときの
ビアホール内への析出状態を図１のＡ、Ｂ、Ｃに、ＰＲ
電解で電気銅めっきを行ったときの析出状態を図２（Ａ
は２時間電解、Ｂは３時間電解）に示す。 この結果か
ら明らかなように、直流電解を行った場合はビアホール
開口部に析出銅が集中し、電気銅めっきが均一に成膜さ
れず、特に底部の銅回路と壁面の境界は、著しく膜厚が
薄く、隙間が形成されていた。[Experimental Results] FIG. 1 shows a via hole before plating, a deposition state in a via hole when electrolytic copper plating is performed by DC electrolysis, and a deposition state in a via hole when electrolytic copper plating is performed by pulse electrolysis. A, B, C, PR
FIG. 2 (A) shows the deposition state when electrolytic copper plating is performed by electrolysis.
Indicates electrolysis for 2 hours, and B indicates electrolysis for 3 hours. As is clear from this result, when DC electrolysis was performed, the deposited copper was concentrated at the opening of the via hole, and the electrolytic copper plating was not formed uniformly. Particularly, the boundary between the copper circuit at the bottom and the wall surface was extremely thick. Was thin and a gap was formed.
【００２４】またパルス電解の場合も、直流電解とはほ
とんど差異が無く、均一電着性が改善されなかった。
このことから、ビアホールでは穴径が小さくなるほど液
の循環および拡散が起こりにくくなり、一般的に設定さ
れるデューティーサイクルのパルス電解では、均一電着
性はほとんど改善できないことが確認された。Also in the case of pulse electrolysis, there was almost no difference from direct current electrolysis, and uniform electrodeposition was not improved.
From this, it was confirmed that as the hole diameter becomes smaller in the via hole, the circulation and diffusion of the liquid are less likely to occur, and that the pulse electrodeposition with a generally set duty cycle can hardly improve the throwing power.
【００２５】これに対しＰＲ電解で電気銅めっきを行っ
たときは析出銅が底部から徐々に積み上がり、３時間後
にはビアホールの開口部付近まで析出銅が埋まって、い
わゆるビアフィリングが形成できることが確認された。On the other hand, when electrolytic copper plating is performed by PR electrolysis, the deposited copper gradually builds up from the bottom, and after 3 hours, the deposited copper fills the vicinity of the opening of the via hole, so that a so-called via filling can be formed. confirmed.
【図１】めっき前のビアホール、直流電解で電気銅めっ
きを行ったときのビアホール内への析出状態およびパル
ス電解で電気銅めっきを行ったときのビアホール内への
析出状態を示す金属組織の写真。FIG. 1 is a photograph of a metal structure showing a via hole before plating, a deposition state in a via hole when electrolytic copper plating is performed by DC electrolysis, and a deposition state in a via hole when electrolytic copper plating is performed by pulse electrolysis. .
【図２】ＰＲ電解で電気銅めっきを行ったときのビアホ
ール内への析出状態を示す金属組織の写真。 以 上FIG. 2 is a photograph of a metal structure showing a precipitation state in a via hole when electrolytic copper plating is performed by PR electrolysis. that's all
フロントページの続き (72)発明者 藤波 知之 神奈川県藤沢市城南３−１−33−1110Continued on the front page (72) Inventor Tomoyuki Fujinami 3-1-3-3-1110, Jonan, Fujisawa-shi, Kanagawa
Claims (2)
後、ＰＲ電解により金属電気めっきを行うことを特徴と
するビアフィリング方法。1. A via-filling method, comprising: forming an electroless metal film in micropores; and performing metal electroplating by PR electrolysis.
後、まず直流電解により金属電気めっきを行ない、次い
でＰＲ電解で金属電気めっきを行うことを特徴とするビ
アフィリング方法。2. A via-filling method, comprising: after forming an electroless metal film in a micropore, first performing metal electroplating by DC electrolysis, and then performing metal electroplating by PR electrolysis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21387397A JPH1143797A (en) | 1997-07-25 | 1997-07-25 | Method for via-filling |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21387397A JPH1143797A (en) | 1997-07-25 | 1997-07-25 | Method for via-filling |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1143797A true JPH1143797A (en) | 1999-02-16 |
Family
ID=16646438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21387397A Pending JPH1143797A (en) | 1997-07-25 | 1997-07-25 | Method for via-filling |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1143797A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0786297A1 (en) * | 1996-01-16 | 1997-07-30 | Verein Deutscher Werkzeugmaschinenfabriken e.V. (VDW) | Drive for a forming machine |
| WO2003033775A1 (en) * | 2001-10-16 | 2003-04-24 | Shinko Electric Industries Co., Ltd. | Method of copper-plating small-diameter holes |
| JP2006214006A (en) * | 2005-02-04 | 2006-08-17 | Hoellmueller Maschinenbau Gmbh | Process and apparatus for electrochemical treatment of piece in passing equipment |
| KR100730326B1 (en) * | 2000-02-01 | 2007-06-19 | 신꼬오덴기 고교 가부시키가이샤 | Method of plating for filling via holes |
| JP2008031516A (en) * | 2006-07-28 | 2008-02-14 | Nippon Macdermid Kk | Electroplating method |
| JP2015097254A (en) * | 2013-10-09 | 2015-05-21 | 日立化成株式会社 | Multilayer wiring board manufacturing method |
| JP2015097252A (en) * | 2013-10-09 | 2015-05-21 | 日立化成株式会社 | Multilayer wiring board |
| JP2015097253A (en) * | 2013-10-09 | 2015-05-21 | 日立化成株式会社 | Method of manufacturing multilayer wiring board |
-
1997
- 1997-07-25 JP JP21387397A patent/JPH1143797A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0786297A1 (en) * | 1996-01-16 | 1997-07-30 | Verein Deutscher Werkzeugmaschinenfabriken e.V. (VDW) | Drive for a forming machine |
| KR100730326B1 (en) * | 2000-02-01 | 2007-06-19 | 신꼬오덴기 고교 가부시키가이샤 | Method of plating for filling via holes |
| WO2003033775A1 (en) * | 2001-10-16 | 2003-04-24 | Shinko Electric Industries Co., Ltd. | Method of copper-plating small-diameter holes |
| JP2006214006A (en) * | 2005-02-04 | 2006-08-17 | Hoellmueller Maschinenbau Gmbh | Process and apparatus for electrochemical treatment of piece in passing equipment |
| JP2008031516A (en) * | 2006-07-28 | 2008-02-14 | Nippon Macdermid Kk | Electroplating method |
| JP2015097254A (en) * | 2013-10-09 | 2015-05-21 | 日立化成株式会社 | Multilayer wiring board manufacturing method |
| JP2015097252A (en) * | 2013-10-09 | 2015-05-21 | 日立化成株式会社 | Multilayer wiring board |
| JP2015097253A (en) * | 2013-10-09 | 2015-05-21 | 日立化成株式会社 | Method of manufacturing multilayer wiring board |
| JP2015097251A (en) * | 2013-10-09 | 2015-05-21 | 日立化成株式会社 | Method of manufacturing multilayer wiring board |
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