JPH01253955A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make the gate dimensions of a P-type active region and an N-type active region equal to each other by specifying the difference in step level between the P-type active region and the N-type active region. CONSTITUTION:The difference Ha in step level between a P-type active region on an N-type well 6 and an N-type active region on a P-type well 7 is a multiple of lambda/2n multiplied by an integer wherein (lambda) denotes the wavelength of an exposure light source and (n) denotes the refractive index of a photoresist. If the difference in thickness between resist films is a multiple of lambda/2n multiplied by an integer, the same pattern dimensions can be obtained with the period of lambda/2n by the standing wave effect of the exposure light source so that the same pattern dimensions can be obtained even at the different parts where the resist film thickness are different. With this constitution, if the mask dimensions of the P-type region and the N-type region are the same, a semiconductor device in which the gate dimensions LPa and LNa of the P-type region and the N-type region are equal to each other can be obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

FIG. 9 is a diagram showing a cross-sectional structure of a conventional cPlos type semiconductor device, in which (11 is a silicon substrate, (2)
.

(2b) is a field oxide film, (3b) is a Pch gate electrode, (4b) is an Nch gate electrode, <5> is a gate oxide film, (6) is an N well, and <<η is a P well. Further, (Hb) indicates the level difference between the Pch active region and the Nch active region.

Next, the manufacturing process of this semiconductor device will be explained with reference to FIGS. 11 to 13. In FIG. 11, (3) is a polysilicon film for a gate electrode as an example, and a gate oxide film (5) is a polysilicon film for a gate electrode.
After formation, it is formed on the gate oxide film (5) using the CVD method. In addition, Q'J is a photoresist film used during photolithography for forming the gate electrode.
Using a photomask, expose and develop a resist pattern for gate electrodes, for Pch (13a) and for Nch (13a).
13b) is formed. Then, in FIG. 13, the polysilicon film is selectively removed by anisotropic etching using photoresist patterns (13a) and (13b) to form gate electrodes (3b) and (4b), and after the resist is removed, as shown in FIG. A semiconductor device having a cross-sectional structure as shown in FIG.

FIG. 10 is a graph showing the standing wave effect of the exposure light source during exposure to the photoresist film 01, and shows, as an example, the relationship between the resist film thickness during the gate process and the gate resist pattern dimensions. al is resist IJ, (13c)
indicates the resist pattern after exposure and development, (1) indicates the resist film thickness, and (L) indicates the pattern dimension. This shows that the film thickness and dimensions are not directly proportional. In Fig. 10 ta+, point A and point B are taken as an example.

Considering point C, point A (t = tl, L = Lx
) Point B (t = t,, L-L,) Point C (t-t6.L
-Ls), and points A and C are 1. >1. This is a general relationship when L3>Lo and the difference in resist film thickness is large (at point B, where the standing wave effect is strong, t.

>1. Nevertheless, L+<t,z, and the pattern dimension at point B where the resist film is thick becomes shorter.

[Problem to be solved by the invention]

Conventional semiconductor devices are manufactured using the process described above, and the resist film thickness is reduced by the island step (Hb).
If the relationship between points A and B in Figure 10 is established between the channel and Nch areas, the resist pattern and finished gate electrode length will be different even if the mask dimensions are Pch=Nch, or ≠L. There was an issue.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a semiconductor device in which the gate dimensions of Pch and Nch are always the same if the mask dimensions of Pch and Nch are the same.

(Means for Solving the Problems) The semiconductor device according to the present invention has the refractive index of the island step ombre resist. are made equal, and the gate dimensions of Pch and Nch are made equal.

[Effect]

The semiconductor device of this invention utilizes the advantage of the standing wave λ of the exposure light source that if the difference in resist film thickness is an integral multiple of -, the same pattern size can be obtained with a cycle of -. This makes it possible to obtain the same gate pattern dimensions even in locations where the resist film thickness is different. That is, although the resist film thickness is different at points A and D, the same resist pattern is λ due to scales and points, and the difference in the resist film thickness between points A and D is - n λ (1.-1= -).

n [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
In the figure, +11 is a silicon substrate, (21(2a)-
(5) is the gate oxide film, (6) is the N-well, (
7) shows the P well, and also the Pch active region and the Nch
The level difference Ha in the active λ active region is an integral multiple of -.

Next, the manufacturing process of the semiconductor device of the present invention will be explained with reference to FIGS. 2 to 8. In Fig. 2, (1) is formed by forming an underlying oxide film (8) on a silicon substrate by thermal oxidation, forming a nitride film on it by CVD method, and selectively removing it using a photoresist to form a nitride film pattern ( 9). Then, using the nitride film pattern (9) as a mask, ion implantation is performed over the entire surface of the wafer to form an implantation layer (7a) for the P well. In FIG. 3, an island oxide film α is formed by thermal oxidation using the nitride film pattern (9) as a mask.

At this time, the thickness of the island λ oxide film αl is set to n 2Ha, which is twice Ha (an integral multiple of -). At this time, the injection layer (7a
) are diffused by thermal diffusion to form a P-well (7). After removing the nitride film pattern (9), ions are implanted into the entire surface of the wafer using the island oxide film αφ as a mask, and thermal diffusion is performed to perform N well (6
Form 1. Then, by removing the underlying oxide film (8) and the island oxide film Ql, a cross-sectional structure as shown in FIG. 4 is obtained. At this time, the level difference between the N well (6) and the λP well (7) is Ha (an integral multiple of -1). In FIG. 5, after forming the underlying oxide film aIl, the CV
The nitride film is debossed by method D, and the nitride film is selectively removed using a photoresist to form a nitride film pattern am. Then, in FIG. 6, field oxide films (2a) (21) are formed by thermal oxidation using the nitride film pattern @ as a mask.Then, the nitride film pattern @ is removed and the underlying oxide film 0υ
After removing , a cross-sectional structure as shown in FIG. 7 is obtained. At this time, the Pch active region on the N well (6) and the N well on the P well (7)
In FIG. 8, the step difference in the channel active region is λ Ha (an integer multiple of -).
n After forming a gate oxide film (5) by thermal oxidation, a polysilicon film for a gate electrode is formed by a CVD method, and a photoresist film O1 for forming a gate electrode is applied.

At this time, the resist film thickness t on the Pch active region and Nc
The difference in resist film thickness 1H on the h active region is an integral multiple of λ −. Thereafter, the process becomes as shown in FIGS. 12 and 13 in exactly the same manner as in the conventional method, and the cross-sectional structure of the semiconductor device of the present invention as shown in FIG. 1 is completed. At this time, the finished gate dimensions are LPa''LNa.

Although the above embodiments have been described with reference to the case where polysilicon is used for the gate electrode, similar effects can be obtained in the case of a high melting point metal or its silicide, or in the case of a polycide structure with polysilicon.

In addition, although the gate electrode was explained in the above embodiment,
Similar effects can be obtained in the subsequent formation of contact holes and metal multilayer wiring patterns.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain a pattern with uniform dimensions even at locations on the wafer where the resist film thickness is different, it is possible to obtain a pattern as designed, and it is possible to obtain a pattern with higher precision. This has the effect of providing a semiconductor device with high performance.

[Brief explanation of the drawing]

1 to 8 are sectional views of a semiconductor device according to an embodiment of the present invention and sectional views of each manufacturing process thereof, and FIGS. 9 and 11 to 13 are sectional views and sectional views of a conventional semiconductor device. Cross-sectional views of each manufacturing process, FIG. , fl+ is the silicon substrate, +21 (2a) is the field oxide film, [31+41 is the gate electrode, (5)
is gate oxide film, (6th is N well, (7) is P well, (8) is underlying oxide film, (9) is nitride film pattern, al
(2) shows an island oxide film, Qll shows an underlying oxide film, (2) shows a nitride film pattern, and G1 shows a photoresist film. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (3)

[Claims] (1) Pch gate length and Nc of CMOS type semiconductor device
1. A semiconductor device characterized in that, in order to equalize the gate length of h, the step difference between the islands is made an integral multiple of λ/2n (λ: the wavelength of the exposure light source, n: the refractive index of the photoresist). (2) In order to equalize the diameters of the contact hole on the Pch active region of the CMOS type semiconductor device, the contact hole on the Pch gate wiring and the contact hole on the Nch active region, and the contact hole on the Nch gate wiring, an island step difference is made. A semiconductor device characterized in that λ/2n is an integral multiple of λ/2n. (3) In order to equalize the width of the metal multilayer interconnection passing over the Pch active region of the CMOS type semiconductor device and the width of the metal multilayer interconnection passing over the Nch active region, the step difference between the islands is set to λ/
A semiconductor device characterized in that the number is an integral multiple of 2n.