JPH01253242A - Bonding process for semiconductor chip - Google Patents

Bonding process for semiconductor chip

Info

Publication number
JPH01253242A
JPH01253242A JP63080415A JP8041588A JPH01253242A JP H01253242 A JPH01253242 A JP H01253242A JP 63080415 A JP63080415 A JP 63080415A JP 8041588 A JP8041588 A JP 8041588A JP H01253242 A JPH01253242 A JP H01253242A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonding
capillary
bonded
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63080415A
Other languages
Japanese (ja)
Inventor
Katsu Tomita
富田　克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP63080415A priority Critical patent/JPH01253242A/en
Publication of JPH01253242A publication Critical patent/JPH01253242A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To eliminate the arrangement of two bonding stages by a method wherein a semiconductor chip hung by using a capillary is shifted onto a leadframe arranged on a bonding stage to be die-bonded and then wire-bonded. CONSTITUTION:A semiconductor chip 1 is shifted to an alignment stage 2 to be aligned by correcting an alignment pawl 3. A capillary 4 is lowered sc that the lower end of a wire 5 inserted into the capillary 4 may be bonded onto an electrode pad 1a. Next, the semiconductor chip 1 hung by the capillary 4 is shifted onto a die pad 7a on a leadframe 7 arranged on a bonding stage 6 to be mounted on the die pad 7a. The semiconductor chip 1 is thrusted by the capillary 4 to be die-bonded through the intermediary of an inserted eutectic solder while it is being thrusted. Finally, the capillary 4 is shifted to bond the other end of the wire 5 onto a lead terminal 7b.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、半導体装置の組立工程における半導体チップ
のボンディング方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for bonding semiconductor chips in an assembly process of a semiconductor device.

〈従来の技術〉 従来から、ＬＥＤやトランジスタなどの半導体チップの
ポンディング、すなわち、半導体チップのリードフレー
ムへの組み込みに際しては、第２図（ａ）〜（ｃ）の工
程断面図に示すような手順が一般的に採用されている。<Prior art> Traditionally, when bonding semiconductor chips such as LEDs and transistors, that is, when assembling semiconductor chips into lead frames, processes as shown in the process cross-sectional views of FIGS. 2(a) to (c) have been carried out. procedures are commonly adopted.

まず、第２図（ａ）に示すように、半導体ウェハ（図示
していない）をグイシングすることによって分割された
半導体チップ２０をピックアップヘッド（図示していな
い）で位置決めステージ２１上に移送し、半導体チップ
２０の載置位置を位置決め爪２２で修正して位置決めす
る。つぎに、第２図（ｂ）に示すように、位置決めされ
た半導体チップ２０をボンディングヘッド２３によって
グイボンディングステージ２４上に配設されたリードフ
レーム２５上の所定位置、いわゆるグイパッド２５ａ上
に移送したうえ、この半導体チップ２０をボンディング
ヘッド２３で押圧することによって共晶半田（図示して
いない）などを介してダイパッド２５ａにダイボンドす
る。First, as shown in FIG. 2(a), a semiconductor chip 20 that has been divided by guising a semiconductor wafer (not shown) is transferred onto a positioning stage 21 using a pickup head (not shown). The mounting position of the semiconductor chip 20 is corrected and positioned using the positioning claw 22. Next, as shown in FIG. 2(b), the positioned semiconductor chip 20 was transferred by the bonding head 23 to a predetermined position on the lead frame 25 disposed on the Gui bonding stage 24, that is, onto the so-called Gui pad 25a. Further, by pressing the semiconductor chip 20 with the bonding head 23, it is die-bonded to the die pad 25a via eutectic solder (not shown) or the like.

さらに、第２図（ｃ）に示すように、半導体チップ２０
がダイボンドされたリードフレーム２５をグイボンディ
ングステージ２４に対して一直線状に配置されたワイヤ
ボンディングステージ２６上に移送したのち、半導体チ
ップ２０に形成された電極パッド２０ａとリードフレー
ム２５の所定部位としてのリード端子２５ｂとを、キャ
ピラリ２７に保持された金属細線、すなわち、ワイヤ２
８によって互いに接続する。Furthermore, as shown in FIG. 2(c), the semiconductor chip 20
After transferring the die-bonded lead frame 25 onto the wire bonding stage 26 which is arranged in a straight line with respect to the wire bonding stage 24, the electrode pads 20a formed on the semiconductor chip 20 and the lead frame 25 are bonded at predetermined positions. The lead terminal 25b is connected to a thin metal wire held in the capillary 27, that is, the wire 2
8 to each other.

〈発明が解決しようとする課題〉 ところで、前述したような従来のボンディング方法にお
いては、リードフレーム２５に対する半導体チップ２０
のグイボンディングとワイヤボンディングとが互いに異
なるボンディングステージ２４゜２６上で別々に行われ
るので、あらかじめ２つのボンディングステージ２４．
２６を互いに別体として用意しておかねばならず、半導
体チップ２０のボンディングに使用されるボンディング
装置の全体形状が大型化してしまう。<Problem to be Solved by the Invention> By the way, in the conventional bonding method as described above, the semiconductor chip 20 is attached to the lead frame 25.
Since wire bonding and wire bonding are performed separately on different bonding stages 24 and 26, two bonding stages 24 and 26 are performed in advance.
26 must be prepared separately from each other, which increases the overall size of the bonding device used for bonding the semiconductor chip 20.

また、半導体チップ２０がダイボンドされたリードフレ
ーム２５をワイヤボンディングステージ２６上に移送し
た際には、半導体チップ２０とリードフレーム２５との
ダイボンド誤差、すなわち、両者の位置ずれを検出して
補正しなければならないので、ＴＶカメラなどを備えて
なる高精度の位置認識装置を設けておく必要があった。Furthermore, when the lead frame 25 to which the semiconductor chip 20 is die-bonded is transferred onto the wire bonding stage 26, it is necessary to detect and correct the die-bonding error between the semiconductor chip 20 and the lead frame 25, that is, the positional deviation between the two. Therefore, it was necessary to provide a highly accurate position recognition device equipped with a TV camera or the like.

本発明はかかる現状に鑑みて創案されたものであって、
ボンディング装置の全体形状を小型化するとともに、高
価な位置認識装置の削減を図ることが可能な半導体チッ
プのボンディング方法を提供することを目的としている
。The present invention was created in view of the current situation, and
It is an object of the present invention to provide a semiconductor chip bonding method that can reduce the overall size of a bonding device and reduce the need for an expensive position recognition device.

〈課題を解決するための手段〉 本発明に係る半導体チップのボンディング方法は、上記
目的を達成するために、半導体チップをリードフレーム
にダイボンドしたのち、この半導体チップの電極パッド
とリードフレームとをワイヤボンドする半導体チップの
ボンディング方法において、キャピラリによって保持さ
れたワイヤの下端部を位置決めされた半導体チップの電
極パッドにボンドする工程と、この半導体チップをキャ
ピラリによって吊持してボンディングステージ上に配設
されたリードフレーム上の所定位置に移送する工程と、
移送された半導体チップをキャピラリで押圧してリード
フレームにダイボンドする工程と、ボンディングステー
ジ上でダイボンドした位置において半導体チップを固定
支持する工程と、半導体チップの電極パッドにボンドさ
れたワイヤの他端部をキャピラリによってリードフレー
ムの所定部位にボンドする工程とからなることに特徴を
有するものである。<Means for Solving the Problems> In order to achieve the above object, a semiconductor chip bonding method according to the present invention is provided by die-bonding a semiconductor chip to a lead frame, and then connecting the electrode pads of the semiconductor chip and the lead frame with wires. A bonding method for a semiconductor chip to be bonded includes a step of bonding the lower end of a wire held by a capillary to an electrode pad of a positioned semiconductor chip, and a step of suspending this semiconductor chip by a capillary and disposing it on a bonding stage. a step of transferring the lead frame to a predetermined position on the lead frame;
A process of die-bonding the transferred semiconductor chip to a lead frame by pressing it with a capillary, a process of fixing and supporting the semiconductor chip at the die-bonded position on the bonding stage, and a process of bonding the other end of the wire to the electrode pad of the semiconductor chip. This method is characterized by the step of bonding the lead frame to a predetermined portion of the lead frame using a capillary.

〈作用〉 上記方法によれば、キャピラリで吊持された半導体チッ
プをボンディングステージ上に配設されたリードフレー
ム上に移送してダイボンドするとともに、これと同一の
ボンディングステージ上でワイヤボンドしているので、
従来例のような２つのボンディングステージを別々に用
意しておくとともに、半導体チップがダイボンドされた
リードフレームをわざわざワイヤボンディングステージ
上に移送する必要がなくなる。このことにより、ボンデ
ィング装置の全体形状を小型化するとともに、ダイボン
ド誤差を検出して補正するための位置認識装置の削減が
図れる。<Operation> According to the above method, a semiconductor chip suspended by a capillary is transferred and die-bonded onto a lead frame placed on a bonding stage, and wire-bonded is also performed on the same bonding stage. So,
It is no longer necessary to separately prepare two bonding stages as in the conventional example and to take the trouble to transfer the lead frame to which the semiconductor chip is die-bonded onto the wire bonding stage. As a result, the overall shape of the bonding device can be reduced in size, and the number of position recognition devices for detecting and correcting die bonding errors can be reduced.

〈実施例〉 以下、本発明に係る半導体チップのボンディング方法を
、第１図（ａ）〜（ｃ）に示す工程断面図に基づいて説
明する。<Example> Hereinafter, a semiconductor chip bonding method according to the present invention will be described based on process cross-sectional views shown in FIGS. 1(a) to (c).

本発明方法においては、まず、第１図（ａ）に示すよう
に、半導体ウェハ（図示していない）のダイシングによ
って分割された半導体チップ１をピックアンプヘッド（
図示していない）で位置決めステージ２上に移送したう
え、この半導体チップ１の載置位置を位置決め爪３で修
正して位置決めする、そして、下降したキャピラリ４を
挿通して保持されたワイヤ５の下端部を位置決めステー
ジ２上で位置決めされた半導体チップ１の′Ｈ，ｓパッ
ド１ａにボンドする。つぎに、第１図（ｂ）に示すよう
に、この半導体チップ１をその電極パッド１ａとワイヤ
５とを介してキャピラリ４によって吊持し、ボンディン
グステージ６上に配設されたリードフレーム７上の所定
位置、いわゆるグイバッド７ａ上に移送して載置する。In the method of the present invention, first, as shown in FIG.
The semiconductor chip 1 is transferred onto the positioning stage 2 using the positioning claws 3 (not shown), and the positioning position of the semiconductor chip 1 is corrected and positioned using the positioning claws 3. The lower end portion is bonded to the 'H, s pads 1a of the semiconductor chip 1 positioned on the positioning stage 2. Next, as shown in FIG. 1(b), this semiconductor chip 1 is suspended by a capillary 4 via its electrode pads 1a and wires 5, and placed on a lead frame 7 disposed on a bonding stage 6. is transferred and placed on a predetermined position, the so-called Guibad 7a.

そして、リードフレーム７のグイバッド７ａ上に載置さ
れた半導体チップｌをキャピラリ４で押圧することによ
り、この半導体チップ１をこれとグイパッド７ａとの間
に介装された共晶半田（図示していない）などを介して
ダイボンドする。By pressing the semiconductor chip 1 placed on the lead pad 7a of the lead frame 7 with the capillary 4, the semiconductor chip 1 is bonded to the eutectic solder (not shown) interposed between the semiconductor chip 1 and the lead pad 7a. (not included) etc. for die bonding.

そののち、第１図（ｃ）に示すように、ボンディングス
テージ６上でリードフレーム７上にダイボンドした位置
において、半導体チップ１をボンディングステージ６に
配設された押さえ部材８によって固定支持した状態で、
キャピラリ４を半導体チップ１から引き離し、半導体チ
ップ１の電極パッドｌａにボンドされたワイヤ５の他端
部をキャピラリ４によってリードフレーム７の所定部位
、すなわち、リード端子７ｂにボンドする。そして、半
導体チップ１の有する他の電極パッド１ｂとリード端子
７Ｃとの間を、ワイヤ５によって互いに接続する。なお
、押さえ部材８による半導体チップｌの固定支持は、少
なくともキャピラリ４を半導体チップ１から離間させる
際に行われていればよい。Thereafter, as shown in FIG. 1(c), the semiconductor chip 1 is fixedly supported by the holding member 8 disposed on the bonding stage 6 at the position where it is die-bonded onto the lead frame 7 on the bonding stage 6. ,
The capillary 4 is separated from the semiconductor chip 1, and the other end of the wire 5 bonded to the electrode pad la of the semiconductor chip 1 is bonded by the capillary 4 to a predetermined portion of the lead frame 7, that is, the lead terminal 7b. Then, the other electrode pad 1b of the semiconductor chip 1 and the lead terminal 7C are connected to each other by the wire 5. Note that the fixed support of the semiconductor chip l by the holding member 8 only needs to be performed at least when the capillary 4 is separated from the semiconductor chip 1.

〈発明の効果〉 以上説明したように、本発明に係る半導体チップのボン
ディング方法においては、キャピラリによって保持され
たワイヤの下端部を半導体チップの電極パッドにボンド
したうえ、この半導体チップをキャピラリによってボン
ディングステージ上に配設されたリードフレーム上の所
定位置に移送してダイボンドしたのち、さらに、ダイボ
ンドされた半導体チップをボンディングステージの同じ
位置で固定支持した状態で半導体チップの１ｉｔｓパツ
ドにボンドされたワイヤの他端部をキャピラリによって
リードフレームの所定部位にボンドしている。<Effects of the Invention> As explained above, in the semiconductor chip bonding method according to the present invention, the lower end of the wire held by the capillary is bonded to the electrode pad of the semiconductor chip, and then the semiconductor chip is bonded by the capillary. After being transferred to a predetermined position on a lead frame arranged on a stage and die-bonded, the die-bonded semiconductor chip is fixed and supported at the same position on the bonding stage, and the wire is bonded to the 1its pad of the semiconductor chip. The other end is bonded to a predetermined portion of the lead frame by a capillary.

したがって、リードフレームに対する半導体チップのグ
イボンディングとワイヤボンディングとが、ともに同一
のボンディングステージ上で行われるから、従来例のよ
うに、２つのボンディングステージを別々に用意してお
くとともに、半導体チップがダイボンドされたリードフ
レームをわざわざワイヤボンディングステージ上に移送
してダイボンド誤差の検出や補正を行う必要がなくなる
。Therefore, since the die bonding and wire bonding of the semiconductor chip to the lead frame are both performed on the same bonding stage, two bonding stages are prepared separately as in the conventional example, and the semiconductor chip is die-bonded. There is no need to take the trouble of transporting the processed lead frame onto a wire bonding stage to detect and correct die bond errors.

そのため、ボンディング装置の全体形状を小型化すると
ともに、高価な位置認識装置の削減が図ることができる
という効果がある。Therefore, the overall shape of the bonding device can be reduced in size, and the need for expensive position recognition devices can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜（ｃ）は本発明に係る半導体チップのボ
ンディング方法の実施例をその手順に従って示す工程断
面図であり、第２図（ａ）〜（ｃ）は従来のボンディン
グ方法を示す工程断面図である。 図における符号１は半導体チップ、１ａは電極パッド、
４はキャピラリ、５はワイヤ、６はボンディングステー
ジ、７はリードフレーム、７ａはグイパッド、７ｂはリ
ード端子（所定部位）、８は押さえ部材である。FIGS. 1(a) to (c) are process cross-sectional views showing an embodiment of the semiconductor chip bonding method according to the present invention according to its steps, and FIGS. 2(a) to (c) are process cross-sectional views showing a conventional bonding method. FIG. In the figure, 1 is a semiconductor chip, 1a is an electrode pad,
4 is a capillary, 5 is a wire, 6 is a bonding stage, 7 is a lead frame, 7a is a guide pad, 7b is a lead terminal (predetermined portion), and 8 is a holding member.

Claims (1)

【特許請求の範囲】[Claims] （１）半導体チップをリードフレームにダイボンドした
のち、この半導体チップの電極パッドとリードフレーム
とをワイヤボンドする半導体チップのボンディング方法
において、 キャピラリによって保持されたワイヤの下端部を、位置
決めされた半導体チップの電極パッドにボンドする工程
と、 この半導体チップをキャピラリによって吊持してボンデ
ィングステージ上に配設されたリードフレーム上の所定
位置に移送する工程と、 移送された半導体チップをキャピラリで押圧してリード
フレームにダイボンドする工程と、ボンディングステー
ジ上でダイボンドした位置において、半導体チップを固
定支持する工程と、半導体チップの電極パッドにボンド
されたワイヤの他端部をキャピラリによってリードフレ
ームの所定部位にボンドする工程と からなることを特徴とする半導体チップのボンディング
方法。(1) In a semiconductor chip bonding method in which a semiconductor chip is die-bonded to a lead frame, and then the electrode pads of this semiconductor chip and the lead frame are wire-bonded, the lower end of a wire held by a capillary is attached to a positioned semiconductor chip. bonding to the electrode pads of the semiconductor chip, suspending the semiconductor chip with a capillary and transferring it to a predetermined position on the lead frame placed on the bonding stage, and pressing the transferred semiconductor chip with the capillary. A step of die-bonding to the lead frame, a step of fixing and supporting the semiconductor chip at the die-bonded position on the bonding stage, and a step of bonding the other end of the wire bonded to the electrode pad of the semiconductor chip to a predetermined part of the lead frame using a capillary. A semiconductor chip bonding method comprising the steps of:
JP63080415A 1988-03-31 1988-03-31 Bonding process for semiconductor chip Pending JPH01253242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63080415A JPH01253242A (en) 1988-03-31 1988-03-31 Bonding process for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63080415A JPH01253242A (en) 1988-03-31 1988-03-31 Bonding process for semiconductor chip

Publications (1)

Publication Number Publication Date
JPH01253242A true JPH01253242A (en) 1989-10-09

Family

ID=13717660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63080415A Pending JPH01253242A (en) 1988-03-31 1988-03-31 Bonding process for semiconductor chip

Country Status (1)

Country Link
JP (1) JPH01253242A (en)

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