JPH01251655A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit provided with a clamping circuit generating no malfunction even when a negative voltage is induced on the output terminal, by providing a transistor wherein the collector is connected to the output circuit and the emitter is grounded, and an MOS transistor which turns ON when a voltage inverse to the polarity of output voltage is applied to the output terminal. CONSTITUTION:From ground a current flows through the source and the drain of an MOS transistor 5, when a negative voltage is induced on an output terminals 2, the potential of the output terminal 2 decreases lower than the ground potential, and the potential difference between the output terminal 2 and ground becomes equal to the threshold voltage of an P-channel MOS transistor 5. Thus the output terminal 2 is clamped by the threshold voltage of the MOS transistor 5. Since the threshold voltage of the MOS transistor 5 is set smaller than the forward voltage of a P-N junction wherein a current begins to flow through a parasitic NPN transistor 4, the malfunction of an integrated circuit caused by the operation of the parasitic NPN transistor 4 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit equipped with a circuit for clamping an output terminal voltage.

Background of the Invention In recent years, semiconductor integrated circuits have come to be used to directly drive inductive loads such as motors, and in order to prevent semiconductor integrated circuits from malfunctioning due to negative induced voltage from the load, clamp circuits are used to clamp the output terminal voltage. It has become necessary to incorporate this into semiconductor integrated circuits.

A semiconductor integrated circuit equipped with a conventional clamp circuit will be described below with reference to FIG. FIG. 3 is a circuit diagram of an output section of a conventional semiconductor integrated circuit. In FIG. 3, 1 is a final stage output NPN transistor whose collector is connected to the output terminal 2 and whose emitter is grounded.
) - A diode 3 is provided, the cathode of which is connected to the collector of the transistor 1, and the anode of which is grounded.

The P-type semiconductor substrate of the integrated circuit on which these NPN transistors 1 and diodes 3 are provided is configured with the collector of the NPN transistor 1 as an emitter, the P-type semiconductor substrate as a base, and the epitaxial region of another integrated circuit as a collector. NPNh transistor 4 is parasitic.

The operation of the semiconductor integrated circuit configured as described above will be described below.

First, when a negative voltage is induced in the output terminal 2 by an inductive load, the potential of the output terminal 2 becomes lower than the ground potential, and the potential difference between the output terminal 2 and the ground becomes the forward voltage of the diode 3 (approximately 0.7V), the diode 3 becomes conductive and current flows from the ground through the diode 3 to the output terminal 2. The output terminal 2 is clamped to the voltage drop potential (approximately -0.7V) caused by the diode 3.

Problems to be Solved by the Invention However, in the conventional configuration as described above, the clamped voltage is the PN junction forward voltage of the diode 3, so in the clamped state, the parasitic NPN transistor 4
A forward bias is applied between the base and emitter of the parasitic N
A current flows from the collector to the emitter of the PN transistor 4. This has caused a problem in that the integrated circuit connected to the collector of the parasitic NPN transistor 4 malfunctions.

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor integrated circuit equipped with a clamp circuit that does not malfunction even when a negative voltage is induced at its output terminal.

Means for Solving the Problems To solve the above problems, the semiconductor integrated circuit of the present invention includes a transistor whose collector is connected to an output terminal and whose emitter is grounded, and whose gate and drain or source are connected to the output terminal. The device includes a MOS transistor which is connected to the output terminal, the other end of which is grounded, and which turns on when a voltage in the opposite direction to the polarity of the output voltage is applied to the output terminal.

Effect: With the above configuration, if a negative voltage is induced at the output terminal where the output voltage is a positive voltage, for example, by providing a P-channel MOS transistor with its source grounded and its gate and drain connected to the output terminal, the output terminal The voltage is clamped to the threshold voltage of the P-channel MOS transistor, and can be clamped below the voltage at which current begins to flow through the transistor parasitic to the collector of the transistor. Therefore, this parasitic transistor does not operate, and malfunction of the integrated circuit connected to the parasitic transistor is prevented.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a circuit diagram of an output section of a semiconductor integrated circuit according to an embodiment of the present invention, and the same components as in FIG. 3 of the conventional example are given the same reference numerals and explanations are omitted. In the circuit of Fig. 1, a P-channel MOS is used instead of the diode 3 of Fig. 3 in the conventional example.
It is equipped with a transistor 5. P channel MO
The gate and drain of the S transistor 5 are connected to the output terminal 2, and the source is grounded, and the threshold voltage of the P-channel transistor 5 is lower than the PN junction forward voltage at which current begins to flow through the parasitic NPN transistor 4. It is set.

2 is a sectional view of a semiconductor substrate showing the structure of the semiconductor integrated circuit of FIG. 1. FIG.

As shown in FIG. 2, island regions 7, 71 and 72 are formed by N-type epitaxial layers in a P-type semiconductor substrate 6, and a P-type base head constituting the NPN transistor 1 is formed in the island region 71. In the island region 72, a train region 10 and a source region 4!11 forming a P-channel MOS transistor 5 are formed.
A gate Etffi 13 is formed on the surface of the P-type semiconductor substrate 6 between the drain region 10 and the source region 11 with a gate insulating film 12 interposed therebetween. The emitter/vine region 9 of the NPN transistor 1 and the source V of the P channel MOS transistor 5! L! ! 11 is connected to a grounded P-type semiconductor substrate 6, and an island region 71 serving as a collector of an NPN transistor 1, a train region 10 and a gate pole 12 of a P-channel MOS transistor 5 are connected to an output terminal 2. According to this structure, N, P
The island region 71 serving as the collector of the N transistor 1 serves as the emitter. A parasitic NPN transistor 4 is formed with the P-type semiconductor substrate 6 as a base and the island region 7 as a collector.

The operation of the semiconductor integrated circuit configured as described above will be explained below.

First, when a negative voltage is induced to the output terminal 2 by an inductive load connected to the output terminal 2, the potential of the output terminal 2 decreases below the ground potential, and the potential difference between the output terminal 2 and the ground becomes the P channel. When the threshold voltage of the MOS transistor 5 is reached, a current flows from the ground through the source and drain of the P-channel MOS transistor 5 to the output terminal 2.

And output terminal 2 is P channel MO3) transistor 5
clamped at a threshold voltage of

At this time, the threshold voltage of the P-channel MOS transistor 5 is set lower than the PN junction forward voltage (approximately 0.7 V) at which current begins to flow through the parasitic NPN transistor 4, so the parasitic NPN transistor 4 does not operate. Malfunctions of the integrated circuit caused by the operation of the parasitic NPN transistor 4 can be reduced by 19jIF.

Note that in this embodiment, the output terminal 2 whose output voltage is a positive voltage
Although we explained the circuit in which a negative voltage is induced in the circuit, when a positive voltage is induced in the output terminal whose output voltage is a negative voltage, a similar effect can be obtained by using the MO5h run transistor to operate with a positive voltage at the output terminal. can be given.

Effects of the Invention As described above, according to the present invention, even if a negative voltage is induced at the output terminal where the output voltage is a positive voltage, the source of the P-channel MOS transistor is grounded and the gate and drain are connected to the output terminal. By connecting them, the output terminal voltage is clamped to the threshold voltage of the P-channel MOS transistor, and a parasitic transistor is generated at the collector of the transistor. does not operate, thereby preventing malfunction of the integrated circuit connected to the parasitic transistor.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an output section of a semiconductor integrated circuit showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor substrate showing the structure of the semiconductor integrated circuit of FIG. 1, and FIG. 3 is a conventional semiconductor integrated circuit. FIG. 3 is a circuit diagram of an output section of the integrated circuit. 1...NPN transistor, 2...output terminal, 3...
... PN junction diode, 4... Parasitic NPN) transistor, 5... P channel MOS transistor, 6...
...P-type semiconductor substrate, 7.71.72...Island region, 8
...Base region, 9...Emitter region, 10...
Drain region, 11... Source region, 12... Gate insulating film, 13... Gate electrode. Figure 3: Agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. A transistor whose collector is connected to the output terminal and whose emitter is grounded, and one of the gate and drain or source is connected to the output terminal and the other is grounded, and the voltage is in the opposite direction to the polarity of the output voltage. A semiconductor integrated circuit comprising a MOS transistor that turns on when is applied to the output terminal.