JPH01248642A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01248642A JPH01248642A JP7942288A JP7942288A JPH01248642A JP H01248642 A JPH01248642 A JP H01248642A JP 7942288 A JP7942288 A JP 7942288A JP 7942288 A JP7942288 A JP 7942288A JP H01248642 A JPH01248642 A JP H01248642A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode wiring
- electrode wirings
- etched
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000011229 interlayer Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 15
- 238000002161 passivation Methods 0.000 abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000004411 aluminium Substances 0.000 abstract 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特にコンタク
ト部における電極とパッシベーション膜の段差被覆性を
改善する製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for improving step coverage between an electrode and a passivation film in a contact portion.
従来、この種の半導体装置の製造方法は、第２図（ａ）
に示す様に眉間絶縁膜２にコンタクト孔４を形成後、ア
ルミニウム膜３を厚さ１ｌ１００ｎスパツタ法により成
長させ、次に、第２図（ｂ）に示すように、パターニン
グの為のホトレジストを厚さ２１００ｎｍ塗布し、パタ
ーニングしてホトレジストマスク７を形成した後に、ア
ルミニウム膜４をエツチングし電極配線６を形成する。Conventionally, the manufacturing method of this type of semiconductor device is as shown in FIG. 2(a).
After forming a contact hole 4 in the glabella insulating film 2 as shown in FIG. After coating and patterning to a thickness of 2100 nm to form a photoresist mask 7, the aluminum film 4 is etched to form an electrode wiring 6.
次に、第２図（ｃ）に示すようにホトレジストマスクを
剥離し、第２図（ｄ）に示すように、プラズマＣＶＤ法
によりパッシベーション膜１ｏを成長させていた。Next, as shown in FIG. 2(c), the photoresist mask was peeled off, and as shown in FIG. 2(d), a passivation film 1o was grown by plasma CVD.
上述した従来の半導体装置の製造方法は、コンタクト孔
とその周辺を覆って導電膜を被着したのちパターニング
を行うだけであるので第２図（ｅ）に示すように、コン
タクト部の電極配線の段差被覆性（ｂ ／ ａ ＞が良
くないという欠点がある。In the conventional semiconductor device manufacturing method described above, only the conductive film is deposited to cover the contact hole and its surroundings, and then patterned. It has a disadvantage that the step coverage (b/a>) is not good.
さらに、上層にパッシベーション膜を被覆する場合、コ
ンタクト段部でのパッシベーション膜形状も悪くなりバ
、ツトベーション膜にクラックが発生しゃすくな′る゛
という欠点もある。Furthermore, when the upper layer is coated with a passivation film, the shape of the passivation film at the contact step becomes poor, and cracks are less likely to occur in the passivation film.
本発明の目的は電極配線平面の平坦性を改善可能な半導
体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the flatness of an electrode wiring plane.
本発明の半導体装置の製造方法は、眉間絶縁膜のコンタ
クト孔とその周辺を覆って導電膜を選択的に設けて電極
配線を形成する工程と、前記電極配線の側面の厚さより
薄くレジスト膜を塗布し焼きしめを行なう工程と、前記
導電膜用のエラチャン１〜を用いてエツチングを行ない
前記電極配線の段差被覆性を改善する工程とを有すると
いうものである。The method for manufacturing a semiconductor device of the present invention includes a step of selectively providing a conductive film to cover the contact hole and the surrounding area of the glabella insulating film to form an electrode wiring, and forming a resist film thinner than the thickness of the side surface of the electrode wiring. The method includes a step of coating and baking, and a step of etching using the conductive film Erachan 1 to improve the step coverage of the electrode wiring.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｇ）は本発明の一実施例を説明するた
めの工程順に配置した半導体チップの断面図である。FIGS. 1(a) to 1(g) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of the present invention.
まず第１図（ａ）に示すように、眉間絶縁膜２にコンタ
ク、ト孔４を設けた後、スパッタ法により、アルミニウ
ム膜３を厚さ約１３００？１！１１成長した後、第１図
（ｂ）に示す様にホトレジストを厚さ約２１００ｎｍ塗
布し、現像してホトレジストマスク７を形成したのちア
ルミニウムのエツチングを行ない電極配線６を形成する
０次に、第１図（ｃ）に示すように、ホトレジストマス
ク７の剥離を行なう。First, as shown in FIG. 1(a), a contact hole 4 is provided in the glabella insulating film 2, and an aluminum film 3 is grown to a thickness of about 1300?1!11 by sputtering. As shown in FIG. 1(b), a photoresist is applied to a thickness of about 2100 nm and developed to form a photoresist mask 7, and then aluminum is etched to form an electrode wiring 6. Next, as shown in FIG. 1(c), Next, the photoresist mask 7 is removed.
次に、第１図（ｄ）に示すように、厚さ１ｌ１００ｎの
ホトレジスト膜８を塗布し、焼きしめを行なう。この際
ホトレジスト膜のバターニングは不要なので現像は行な
う必要はない。図示したように電極配線６の突起９が一
部露出するのが好ましいが、表面を薄くホトレジスト膜
が覆っていても差支えはない。次に、第１図（ｅ）に示
すように、反応性イオンエツチングを行ない突起９のエ
ツチングを行なう、このとき、ホトレジスト膜も少しエ
ツチングされるので、前述したように、電極配線の表面
がホトレジスト膜で薄く覆われていたとしても結局、突
起９がエツチングされる。Next, as shown in FIG. 1(d), a photoresist film 8 having a thickness of 1l100n is applied and baked. At this time, since patterning of the photoresist film is unnecessary, there is no need to perform development. Although it is preferable that a portion of the protrusion 9 of the electrode wiring 6 be exposed as shown in the figure, there is no problem even if the surface is covered with a thin photoresist film. Next, as shown in FIG. 1(e), reactive ion etching is performed to etch the protrusion 9. At this time, the photoresist film is also slightly etched, so as mentioned above, the surface of the electrode wiring is covered with the photoresist. Even if it is thinly covered with a film, the protrusion 9 will eventually be etched.
次に、第１図（ｆ）に示すように、ホトレジスト膜８を
剥離すると電極配線６′ができる。次に、第１図（ｇ）
に示すように、パッシベーション膜８を成長させる。Next, as shown in FIG. 1(f), the photoresist film 8 is peeled off to form an electrode wiring 6'. Next, Figure 1 (g)
A passivation film 8 is grown as shown in FIG.
このように、電極配線の突起がエツチングされるので、
コンタクト部での段差被覆性ｂ ／ ａが改善される。In this way, the protrusions of the electrode wiring are etched, so
The step coverage b/a at the contact portion is improved.
従って、その上に被覆されるパッシベーション膜のカバ
レッジ形状も改善される。Therefore, the coverage shape of the passivation film coated thereon is also improved.
なお、電極配線の材料はアルミニウムに限らず、タング
ステンシリサイド等、半導体装置に通常用いられる配線
材料を用いることができる。Note that the material of the electrode wiring is not limited to aluminum, and wiring materials commonly used in semiconductor devices, such as tungsten silicide, can be used.
以上説明した様に、本発明は、コンタクト部の電極配線
上にレジスト膜−を塗布し、焼きしめを行なったのち電
極配線を構成する導電膜のエッチャントでエツチングす
ることにより電極配線の段差被覆性が改善され、更にパ
ッシベーション膜形状も改善されるので、半導体装置の
歩留り、信頼性が向上するという効果がある。As explained above, the present invention provides step coverage of the electrode wiring by applying a resist film on the electrode wiring of the contact part, baking it, and etching it with an etchant for the conductive film constituting the electrode wiring. Since the passivation film shape is also improved, the yield and reliability of semiconductor devices are improved.
第１図（ａ）〜（ｇ）は本発明の一実施画の説明するた
めの工程順に配置した半導体チップの断面図、第２図（
ａ）〜（ｄ）は従来例を説明するための工程順に配置し
た半導体チップの断面図である。
１・・・半導体基板、２・・・層間絶縁膜、３・・・ア
ルミニウム膜、４・・・コンタクト孔、５・・・凹み、
６゜６′・・・電極配線、７・・・ホトレジストマスク
、８・・・ホトレジスト膜、９・・・突起、１０・・・
パッシベーション膜。1(a) to 1(g) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of the present invention, and FIG.
a) to (d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Interlayer insulating film, 3... Aluminum film, 4... Contact hole, 5... Recess,
6゜6'... Electrode wiring, 7... Photoresist mask, 8... Photoresist film, 9... Protrusion, 10...
passivation film.
Claims (1)
を選択的に設けて電極配線を形成する工程と、前記電極
配線の側面の厚さより薄くレジスト膜を塗布し焼きしめ
を行なう工程と、前記導電膜用のエッチャントを用いて
エッチングを行ない前記電極配線の段差被覆性を改善す
る工程とを有することを特徴とする半導体装置の製造方
法。a step of forming an electrode wiring by selectively providing a conductive film covering the contact hole of the interlayer insulating film and its surroundings; a step of applying a resist film thinner than the thickness of the side surface of the electrode wiring and baking it; A method for manufacturing a semiconductor device, comprising the step of performing etching using an etchant for a conductive film to improve step coverage of the electrode wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7942288A JPH01248642A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7942288A JPH01248642A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01248642A true JPH01248642A (en) | 1989-10-04 |
Family
ID=13689427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7942288A Pending JPH01248642A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01248642A (en) |
-
1988
- 1988-03-30 JP JP7942288A patent/JPH01248642A/en active Pending
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