JPH01243546A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01243546A
JPH01243546A JP7092288A JP7092288A JPH01243546A JP H01243546 A JPH01243546 A JP H01243546A JP 7092288 A JP7092288 A JP 7092288A JP 7092288 A JP7092288 A JP 7092288A JP H01243546 A JPH01243546 A JP H01243546A
Authority
JP
Japan
Prior art keywords
film
oxygen
photoresist
plasma
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7092288A
Other languages
Japanese (ja)
Other versions
JP2831646B2 (en
Inventor
Yasushi Nakasaki
靖 中崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63070922A priority Critical patent/JP2831646B2/en
Publication of JPH01243546A publication Critical patent/JPH01243546A/en
Application granted granted Critical
Publication of JP2831646B2 publication Critical patent/JP2831646B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To effectively remove a resist by a method wherein, when a pattern is to be formed by the photoresist by using a conductor film where a passive- state film is hard to form, the photoresist is removed in a plasma atmosphere whose partial pressure of oxygen is 10Pa or lower. CONSTITUTION:A Cu film 2 is formed on the surface of a semiconductor substrate 1; a pattern of a photoresist 3 is formed on its surface. The Cu film 2 is etched selectively by an ion etching method. The resist is ashed and removed by using a parallel-plate type plasma etching apparatus. Concrete conditions are as follows; the substrate is closely contacted to a specimen- holding sheet; the inside of the etching apparatus is evacuated to produce a vacuum of 0.1Pa or lower. After that, while oxygen gas with a pressure of 10Pa or lower flows at a flow rate of 20 SCCM, RF electric power is applied and an oxygen plasma is generated. A plasma treatment is executed in an oxygen plasma atmosphere for 10 minutes. By this setup, the resist 3 can be removed effectively.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は半導体装置の製造方法に係り、特に導体配線の
形成工程の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a process for forming conductor wiring.

(従来の技術) 近年、半導体集積回路の高集積化に伴・い、配線幅およ
び厚さの縮小や多層化がますま進められている。配線材
料としては、275Ω・ramという低い比抵抗を示し
、かつ不動態被膜が形成されて防食されるANQを主成
分とする合金膜が多く用いられている。しかしながら、
配線断面積の縮小と同じ比率で信号電流の低減はなされ
ず、このため、電流密度が増大してエレクトロ・マイグ
レーションによる断線が大きい問題となってきている。
(Prior Art) In recent years, as semiconductor integrated circuits have become more highly integrated, wiring widths and thicknesses have been reduced and the number of layers has been increased. As a wiring material, an alloy film mainly composed of ANQ is often used, which exhibits a low specific resistance of 275 Ω·ram and forms a passive film to prevent corrosion. however,
The signal current is not reduced at the same rate as the wiring cross-sectional area is reduced, and as a result, the current density increases and wire breakage due to electromigration has become a serious problem.

また配線の多層化により、配線は複雑な熱履歴を受ける
ことになり、熱ストレスによるストレス・マイグレーシ
ョンによる断線も問題になってきている。これらの問題
の主要因は、Afの融点がf360℃と低く、比較的低
温で原子の拡散が生じ、特に結晶粒界を経路とする拡散
が生じ易いこと、また引張り応力が生じた場合には上述
の原子拡散がより加速されること、等にある。そこで最
近は、Afと同等以上の低い比抵抗を有し、/lより高
融点であるCuまたはその合金を半導体装置の配線材料
に用いることが検討され始めている。
Furthermore, due to the multilayered wiring, the wiring is subjected to a complex thermal history, and disconnection due to stress migration due to thermal stress is also becoming a problem. The main reason for these problems is that the melting point of Af is as low as f360°C, and atomic diffusion occurs at relatively low temperatures, particularly through grain boundaries, and that when tensile stress occurs, The above-mentioned atomic diffusion is further accelerated. Therefore, recently, studies have begun to consider using Cu or its alloys, which have a resistivity as low as or higher than Af and a melting point higher than /l, as wiring materials for semiconductor devices.

一方、集積回路の導体配線のパターニングは、フォトレ
ジストを用いたフォトリソグラフィ技術・により行われ
ている。フォトレジストを用いて導体膜を選択エツチン
グした後、フォトレジストは酸素プラズマ照射により灰
化して除去される。通常この酸素プラズマの発生は、約
130Pa近傍の酸素分圧でのRF放電に行われる。こ
の圧力領域は比較的高圧であり、従ってプラズマ中の酸
素ラジカルの比率が高くなる。フォトレジスト灰化の機
構は、レジストポリマーが酸素によってCO2と820
に分解される反応である。この反応に寄与しているのは
、酸素ラジカルであり、レジスト除去速度は酸素ラジカ
ル濃度に比例する。
On the other hand, patterning of conductor wiring in integrated circuits is performed by photolithography technology using photoresist. After selectively etching the conductive film using a photoresist, the photoresist is ashed and removed by oxygen plasma irradiation. Typically, this oxygen plasma is generated by RF discharge at an oxygen partial pressure of around 130 Pa. This pressure region has a relatively high pressure and therefore a high proportion of oxygen radicals in the plasma. The mechanism of photoresist ashing is that the resist polymer is exposed to CO2 and 820
This is a reaction that decomposes into Oxygen radicals contribute to this reaction, and the resist removal rate is proportional to the oxygen radical concentration.

従って酸素プラズマ灰化によるレジスト除去法では、酸
素ラジカル濃度が高い方がよく、一般に上述のような酸
素分圧が選ばれる。
Therefore, in the resist removal method using oxygen plasma ashing, it is better to have a high oxygen radical concentration, and the above-mentioned oxygen partial pressure is generally selected.

ところで配線としてA1またはAJL合金膜を用いた場
合には、その表面は不動態被膜であるち密な酸化アルミ
ニウムにより覆われる。従って、配線形成後のフォトレ
ジスト除去工程で上述のような酸素プラズマ雰囲気に晒
されても、AL膜の内部に酸化が進行することはない。
By the way, when an A1 or AJL alloy film is used as the wiring, its surface is covered with a dense aluminum oxide film which is a passive film. Therefore, even if the AL film is exposed to the oxygen plasma atmosphere as described above in the photoresist removal process after wiring formation, oxidation will not progress inside the AL film.

ところが・Cuの場合には、上述のような酸素プラズマ
条件では多孔質の脆い酸化膜が形成されるため、フォト
レジスト除去の工程でCu配線が内部まで酸化されてし
まう、という不都合がある。例えば、通常のフォトレジ
スト除去条件では、0.8μ乳の厚みのCu1lは全て
酸化銅に変化してしまう。この酸化により、比抵抗は5
桁以上も上昇し、また配線形状も当然悪くなる。
However, in the case of Cu, a porous and brittle oxide film is formed under the above-mentioned oxygen plasma conditions, so there is a disadvantage that the Cu wiring is oxidized to the inside during the process of removing the photoresist. For example, under normal photoresist removal conditions, Cu11 with a thickness of 0.8 μm all changes to copper oxide. Due to this oxidation, the specific resistance becomes 5
This increases by more than an order of magnitude, and the wiring shape also naturally deteriorates.

(発明が解決しようとする課題) 以上のように、不動態被膜が形成され難い導体膜を配線
材料として用いた場合、フォトレジスト除去を従来と同
様の条件のプラズマ雰囲気で行なうと、所望の配線が得
られない、という問題があった。
(Problems to be Solved by the Invention) As described above, when a conductive film in which a passive film is difficult to form is used as a wiring material, if photoresist is removed in a plasma atmosphere under the same conditions as before, the desired wiring The problem was that it was not possible to obtain

本発明は、この様な問題を解決した半導体装置の製造方
法を提供することを目的とする。
An object of the present invention is to provide a method for manufacturing a semiconductor device that solves these problems.

[発明の構成] (課題を解決するための手段) 本発明は、不動態被膜が形成されにくい導体膜を用いて
フォトレジストによりパターン形成した場合に、フォト
レジストの除去を酸素分圧10pa以下のプラズマ雰囲
気で行なうことを特徴とする。
[Structure of the Invention] (Means for Solving the Problems) The present invention provides a method for removing the photoresist at an oxygen partial pressure of 10 pa or less when a pattern is formed using a photoresist using a conductor film in which a passive film is difficult to form. It is characterized by being carried out in a plasma atmosphere.

(作用) 酸素分圧10Pa以下のプラズマ雰囲気でCUまたはC
u合金膜上のフォトレジスト除去を行なうと、レジスト
除去速度は通常の酸素分圧100Pa程度の場合とそれ
程度らず、CuまたはCU金合金酸化速度を一桁程度以
上低くすることができる。ちなみに酸素ラジカル濃度は
、RF比出力酸素流量にも依存するが、酸素分圧130
Pa近傍の場合およそ10%程度になる。典型的には7
0Pa−Jl/sea程度の酸素ラジカル流量となる。
(Function) CU or C in a plasma atmosphere with an oxygen partial pressure of 10 Pa or less
When the photoresist on the u-alloy film is removed, the resist removal rate is not as fast as the normal oxygen partial pressure of about 100 Pa, and the oxidation rate of Cu or CU-gold alloy can be lowered by about an order of magnitude or more. By the way, the oxygen radical concentration depends on the RF specific output oxygen flow rate, but the oxygen partial pressure is 130
In the vicinity of Pa, it is approximately 10%. Typically 7
The oxygen radical flow rate is about 0 Pa-Jl/sea.

ところが酸素分圧10Pa以下では、酸素ラジカル濃度
は約1/1oに減少する。この結果、酸化速度が抑制さ
れるのみならず、形成される酸化膜も130Pa程度の
場合と比べてち密なものとなり、これが効果的に酸化の
進行を抑制することになる。
However, when the oxygen partial pressure is less than 10 Pa, the oxygen radical concentration decreases to about 1/10. As a result, not only the oxidation rate is suppressed, but also the formed oxide film becomes denser than in the case of about 130 Pa, which effectively suppresses the progress of oxidation.

(実施例) 以下、本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)〜(C)は、本発明の一実施例による配線
形成工程を示す。第1図(a)において、1は所望の素
子が形成され、表面が絶縁膜で覆われた半導体基板であ
り、その表面に配線材料膜としてCa1l!2を形成し
、その表面に通常のフォトリソグラフィによりフォトレ
ジスト3をパターン形成する。CLI膜2は例えば40
00人とし、フォトレジスト3は1.2μmとする。次
にイオンエツチング法により、第1図(b)に示す−よ
うにCul!2を選択エツチングする。次いで平行平板
型プラズマエツチング装置により、フォトレジスト3を
灰化処理して除去し、第1図(C)に示す配線を形成す
る。
FIGS. 1A to 1C show a wiring forming process according to an embodiment of the present invention. In FIG. 1(a), 1 is a semiconductor substrate on which a desired element is formed and whose surface is covered with an insulating film, and a wiring material film is formed on the surface of the semiconductor substrate. 2 is formed, and a photoresist 3 is patterned on the surface thereof by ordinary photolithography. For example, the CLI film 2 has a thickness of 40
00 people, and the photoresist 3 has a thickness of 1.2 μm. Next, using the ion etching method, the Cul! Select and etch 2. Next, the photoresist 3 is removed by ashing using a parallel plate type plasma etching apparatus, and the wiring shown in FIG. 1(C) is formed.

具体的なプラズマエツチングの条件は次の通りである。The specific plasma etching conditions are as follows.

先ず、プラズマエツチング装置内の裏面が水冷されてい
る試料保持板上に基板を密着させて配置し、エツチング
装置内を0.1Pa以下に真空排気する。その後、圧力
1Pa以下の酸素ガスを流ffi208ccMで流しな
がら、周波数13.56MHz 、出力150WのRF
電力を印加し、酸素プラズマを発生させる。この酸素プ
ラズマ雰囲気中で10分間プラズマ処理を行う。
First, a substrate is placed in close contact with a sample holding plate whose back surface is water-cooled in a plasma etching apparatus, and the inside of the etching apparatus is evacuated to 0.1 Pa or less. Then, while flowing oxygen gas with a pressure of 1 Pa or less at a flow ffi of 208 ccM, RF with a frequency of 13.56 MHz and an output of 150 W was applied.
Apply electric power to generate oxygen plasma. Plasma treatment is performed for 10 minutes in this oxygen plasma atmosphere.

この実施例によれば、Cu膜配線を殆ど酸化させること
なく、フォトレジスト除去が行われる。
According to this embodiment, the photoresist is removed without substantially oxidizing the Cu film wiring.

酸素プラズマ処理を100間延長しても、Cu膜配線の
酸化は殆ど進行せず、配線抵抗変化や形状変化も認めら
れなかった。
Even if the oxygen plasma treatment was extended for 100 hours, oxidation of the Cu film wiring hardly progressed, and no change in wiring resistance or shape was observed.

第2図は、Cu配線の酸化速度およびレジスト除去速度
の酸素ガス圧力依存性を示すデータである。酸素プラズ
マによる処理時間は、レジスト除去に要する時間の2倍
としている。従来例(ム。
FIG. 2 shows data showing the dependence of the oxidation rate of Cu wiring and the rate of resist removal on oxygen gas pressure. The processing time using oxygen plasma is twice the time required to remove the resist. Conventional example (mu.

・)は円筒型の場合のデータであり、実施例(△。・) is data for cylindrical type, and Example (△).

○)は平行平板型の場合のデータであるが、これら装置
の相違は本質的ではない。従来のレジスト灰化処理で用
いられている酸素ガス圧力130Paでは4000人の
Cu配線が全て酸化される。酸素ガス圧力の低下と共に
酸化量は減少し、酸素ガス圧力1PaではCLJ配線の
表面近傍数10人程度に酸化が抑制されている。図のデ
ータから明らかなように、レジスト除去速度は、酸素ガ
ス圧力の低下によってもそれ程低下しない。従ってこの
実施例により、酸化され易いCu膜配線のパターニング
に際しても、プラズマ処理により効果的にレジスト除去
が行われる。
○) is data for the parallel plate type, but the difference between these devices is not essential. At the oxygen gas pressure of 130 Pa used in the conventional resist ashing process, all 4000 Cu wiring lines were oxidized. The amount of oxidation decreases as the oxygen gas pressure decreases, and at an oxygen gas pressure of 1 Pa, oxidation is suppressed to about 10 layers near the surface of the CLJ wiring. As is clear from the data in the figure, the resist removal rate does not decrease significantly even with a decrease in oxygen gas pressure. Therefore, according to this embodiment, even when patterning a Cu film interconnection that is easily oxidized, the resist can be effectively removed by plasma treatment.

実施例では、Cu膜の場合を説明したが、Cu合金躾の
場合にも本発明は有効である。その他、容易には不動態
膜が形成され難い他の導体膜を用いた場合にも、本発明
は有効である。配線構造は単層配線に限らず、多層配線
にも当然本発明を適用できる。
In the embodiment, the case of a Cu film was explained, but the present invention is also effective in the case of a Cu alloy film. The present invention is also effective when using other conductor films in which it is difficult to form a passive film. The wiring structure is not limited to single-layer wiring, but the present invention can of course be applied to multi-layer wiring.

[発明の効果] 以上述べたように本発明によれば、不動態膜が形成され
にくい導体膜をフォトリソグラフィにより形成する場合
に、酸素プラズマ処理で配線の劣化をもたらすことなく
、効果的にレジスト除去を行なうことができる。これに
より、エレクトロマイグレーションなどに強い配線をも
った半導体装置を得ることができる。
[Effects of the Invention] As described above, according to the present invention, when forming a conductive film in which a passive film is difficult to form by photolithography, the resist can be effectively removed without deteriorating the wiring due to oxygen plasma treatment. Removal can be performed. This makes it possible to obtain a semiconductor device with wiring that is resistant to electromigration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(C)は、本発明の一実施例のCu1i
!線形成工程を示す図、第2図は、プラズマエツチング
によるCLJの酸化速度と酸素分圧の関係を示す図であ
る。 1・・・半導体基板、2・・・Cu膜、3・・・フォト
レジスト。 出願人代理人 弁理士 鈴 江 武 彦:51図
FIGS. 1(a) to (C) show Cu1i of an embodiment of the present invention.
! FIG. 2, which is a diagram showing the line forming process, is a diagram showing the relationship between the oxidation rate of the CLJ by plasma etching and the oxygen partial pressure. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Cu film, 3... Photoresist. Applicant's agent Patent attorney Takehiko Suzue: Figure 51

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板に不動態被膜を形成しにくい導体膜を
被着し、この導体膜上にフォトレジストをパターン形成
して導体膜を選択エッチングした後、前記フォトレジス
トを酸素分圧10Pa以下のプラズマ雰囲気で灰化して
除去することを特徴とする半導体装置の製造方法。
(1) A conductor film that is difficult to form a passive film is deposited on a semiconductor substrate, a photoresist is patterned on the conductor film, and the conductor film is selectively etched. A method for manufacturing a semiconductor device, characterized in that it is removed by ashing in a plasma atmosphere.
(2)前記導体膜はCuまたはCu合金膜である請求項
1記載の半導体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the conductor film is a Cu or Cu alloy film.
JP63070922A 1988-03-25 1988-03-25 Method for manufacturing semiconductor device Expired - Fee Related JP2831646B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63070922A JP2831646B2 (en) 1988-03-25 1988-03-25 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63070922A JP2831646B2 (en) 1988-03-25 1988-03-25 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01243546A true JPH01243546A (en) 1989-09-28
JP2831646B2 JP2831646B2 (en) 1998-12-02

Family

ID=13445481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63070922A Expired - Fee Related JP2831646B2 (en) 1988-03-25 1988-03-25 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2831646B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003518768A (en) * 1999-12-27 2003-06-10 ラム リサーチ コーポレーション In-situ post-etching process to remove residual photoresist and residual sidewall passivation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5589474A (en) * 1978-12-26 1980-07-07 Ibm Chromium etching method
JPS6080111A (en) * 1983-10-11 1985-05-08 Tdk Corp Method and device for manufacturing thin film magnetic head
JPS6265331A (en) * 1985-09-17 1987-03-24 Hitachi Ltd Etching process for copper or copper alloy

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5589474A (en) * 1978-12-26 1980-07-07 Ibm Chromium etching method
JPS6080111A (en) * 1983-10-11 1985-05-08 Tdk Corp Method and device for manufacturing thin film magnetic head
JPS6265331A (en) * 1985-09-17 1987-03-24 Hitachi Ltd Etching process for copper or copper alloy

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003518768A (en) * 1999-12-27 2003-06-10 ラム リサーチ コーポレーション In-situ post-etching process to remove residual photoresist and residual sidewall passivation
JP2012023385A (en) * 1999-12-27 2012-02-02 Lam Res Corp In-situ post etch process to remove remaining photoresist and residual sidewall passivation

Also Published As

Publication number Publication date
JP2831646B2 (en) 1998-12-02

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