JPH01204449A - Copper wiring method for vlsi - Google Patents
Copper wiring method for vlsiInfo
- Publication number
- JPH01204449A JPH01204449A JP2754388A JP2754388A JPH01204449A JP H01204449 A JPH01204449 A JP H01204449A JP 2754388 A JP2754388 A JP 2754388A JP 2754388 A JP2754388 A JP 2754388A JP H01204449 A JPH01204449 A JP H01204449A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- copper
- film
- transition metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010949 copper Substances 0.000 title claims abstract description 62
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract 12
- 238000000034 method Methods 0.000 title claims description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 13
- 150000003624 transition metals Chemical class 0.000 claims abstract description 13
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- 239000006104 solid solution Substances 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- 230000008569 process Effects 0.000 claims description 5
- 230000003064 anti-oxidating effect Effects 0.000 claims description 3
- 229910000765 intermetallic Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 238000001312 dry etching Methods 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 14
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 13
- 229910002091 carbon monoxide Inorganic materials 0.000 description 13
- 239000000758 substrate Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000012159 carrier gas Substances 0.000 description 10
- 238000004458 analytical method Methods 0.000 description 9
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000000992 sputter etching Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 239000005751 Copper oxide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000431 copper oxide Inorganic materials 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 150000003623 transition metal compounds Chemical class 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＶＬＳ Ｉ用配線の形成法に係り、特に、微細
な配線パターンに大きな電流を通じる素子をもつＶＬＳ
Ｉ用Ｃｕ配線の形成法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming wiring for VLS I, and particularly for VLS I having an element that conducts a large current through a fine wiring pattern.
This invention relates to a method of forming Cu wiring for I.
従来の半導体プロセスにおいて、異方性トライエツチン
グ等により段差側壁部にのみ選択的に堆積物を残す技術
はＬＳ！ハンドブックＰ、４００（１９８４，電子通信
学会）に記載のＬ Ｄ Ｄ （ｌｉｇｈｔｌｙｄｏｐｅ
ｄ ｄｒａｉｎ）構造形成の際の５ｉＯｚスペーサ形成
等に見られる。しかし、これはデバイス形成のための絶
縁物のパターニング技術であり、この技術を導体に用い
た例はない。In conventional semiconductor processes, the technology that selectively leaves deposits only on the step sidewalls using anisotropic tri-etching, etc. is LS! LDD (lightlydope) described in Handbook P, 400 (1984, Institute of Electronics and Communication Engineers)
This can be seen in the formation of 5iOz spacers during the formation of the d drain) structure. However, this is a technique for patterning insulators to form devices, and there is no example of this technique being used for conductors.
Ｗ（ＣＯ）ｅを用いＷ膜をＣＶＤ法により形成する技術
は、ジャーナル オブ エレクトロケミカル ソサイエ
テイ Ｖｏｌ、１１７ＰＰ、６９３−７００ （１９７
０）、（ｊ、Ｅｌｅｃｔｒｏｃｈｅｍ Ｓｏｃ、 １１
７ 。The technique of forming a W film using W(CO)e by CVD method is described in Journal of Electrochemical Society Vol. 117PP, 693-700 (197
0), (j, Electrochem Soc, 11
7.
６９３−７００ （１９７０））、及び、ジャーナル
オブ バキューム サイエンステクノロジーＶｏｌ。693-700 (1970)) and Journal
Of Vacuum Science Technology Vol.
２０ 、 ｐ ｐ 、 １３３６−１３４０（１９８２
） （Ｊ、Ｖａｃ、Ｓｃｉ、Ｔｅ−ｃｈｎｏｌ、 ２０
、１３３６−１３４０（１９８２））において論じら
れている。20, pp, 1336-1340 (1982
) (J, Vac, Sci, Te-channel, 20
, 1336-1340 (1982)).
しかし、これらの技術を配線形成に用いた例はなく、微
細配線の側壁部について従来特別な考慮はされていない
。特に、従来ＣＯの還元効果に注目した佳ＩＵ士ない。However, there have been no examples of using these techniques for wiring formation, and no special consideration has been given to the sidewall portions of fine wiring. In particular, some researchers have focused on the reduction effect of CO.
〔発明が解決しようとする課題〕
配線幅が１μｍ以上ある従来のＶＬＳＩ配線では十分な
幅があるので側壁の保護には特に考慮がされていなかっ
た。特に、配線材料が従来のＡＱの場合には表面酸化皮
膜が強く、側面保護の必要性は小さかった。しかし、Ｖ
ＬＳ Ｉの配線抵抗の低減のためにＡＱより比抵抗の小
さなＣｕ、あるいは、Ｃｕ合金を配線に用いる微細パタ
ーンでは、Ｃｕがち密な酸化皮膜を形成できないため側
面の保護が新たに必要となる。特に、配線幅が０．５μ
ｍ以下と微細化が進むと配線側壁からの腐食による配線
のほそり、あるいは、断線と酸化皮膜を通じたＣｕ配線
の酸化の進行が大きな問題となる。[Problems to be Solved by the Invention] Conventional VLSI wiring having a wiring width of 1 μm or more has a sufficient width, so no particular consideration has been given to sidewall protection. In particular, when the wiring material is conventional AQ, the surface oxide film is strong and the need for side protection is small. However, V
In order to reduce the wiring resistance of LSI, in fine patterns that use Cu or Cu alloy, which has a specific resistance lower than that of AQ, for wiring, a dense oxide film of Cu cannot be formed, so side protection is newly required. In particular, the wiring width is 0.5μ
As miniaturization progresses to less than m, major problems arise such as thinning of the wiring due to corrosion from the sidewalls of the wiring, or progression of oxidation of the Cu wiring through disconnection and oxide film.
また、微細配線でも配線抵抗を下げるために、配線の厚
さはできるだけ大きくする必要があり、配線のアスペク
ト比は１を超えるまでになる。アスペクト比が１以上と
いうことは配線の側壁の面積が上、下部の面積をうわま
わることを意味しており、この点からもＣｕ配線の保護
のためには上下部の保護だけでは不足であり側壁の保護
が不可欠である。Furthermore, in order to reduce the wiring resistance even with fine wiring, the thickness of the wiring needs to be as large as possible, and the aspect ratio of the wiring exceeds 1. An aspect ratio of 1 or more means that the area of the sidewall of the wiring exceeds the area of the top and bottom, and from this point of view, it is insufficient to protect the top and bottom of the Cu wiring. Side wall protection is essential.
本発明の目的は、０．５μｍ以下の微細なＣｕ配線にお
いて、新たに問題となる配線側壁の保護の必要性に対し
、配線の上・下部の保護と同時に、側壁も保護する配線
構造、および、その形成法を提供することにある。The purpose of the present invention is to provide a wiring structure that protects the upper and lower parts of the wiring as well as the sidewalls, in response to the new problem of the need to protect the wiring sidewalls in fine Cu wiring of 0.5 μm or less. , and to provide a method for its formation.
上記目的はＣｕ配線の周囲が全て導電性の膜でおおわれ
た構造とすることにより達成される。この構造の実現は
バリヤメタル層、Ｃｕ配線層、上部配化防止メタル層を
形成後、ホトレジストに配線パターンを形成し、ドライ
エツチング、もしくは、イオンミリングにより配線を形
成し、ＣＶＤ法により全面に遷移金属、もしくは、その
化合物層を形成し、その後、異方性ドライエツチング、
もしくは、イオンミリングにより配線側壁にのみ選択的
にこの層を残し、その後、ホトレジストを除去し、配線
を形成することにより達成される。The above object is achieved by forming a structure in which the entire periphery of the Cu wiring is covered with a conductive film. To realize this structure, after forming a barrier metal layer, a Cu wiring layer, and an upper metal layer, a wiring pattern is formed on photoresist, wiring is formed by dry etching or ion milling, and transition metal is etched over the entire surface by CVD. , or form the compound layer and then anisotropic dry etching,
Alternatively, this can be accomplished by selectively leaving this layer only on the wiring sidewalls by ion milling, then removing the photoresist and forming the wiring.
この際、遷移金属もしくはその化合物層のＣＶＤ中に一
酸化炭素（ＣＯ）、あるいは、水素（Ｈ２）が存在する
と、Ｃｕ表面の酸化銅が還元され、この酸化銅が原因と
なる配線の腐食や、遷移金属層のはがれを防止すること
ができる。At this time, if carbon monoxide (CO) or hydrogen (H2) is present during CVD of the transition metal or its compound layer, the copper oxide on the Cu surface will be reduced, and this copper oxide will cause corrosion of the wiring. , peeling of the transition metal layer can be prevented.
また、この遷移金属にＣｕと固溶せず、また、金属間化
合物も形成しない金属を用いると、配線表面にはＣｕ原
子が拡散してくることがなく、Ｃｕを完全に側壁保護層
でおおいかくずごとができ、その耐酸化性を一層向上さ
せることができる。In addition, if a metal that does not form a solid solution with Cu or forms an intermetallic compound is used as the transition metal, Cu atoms will not diffuse to the wiring surface and the Cu will be completely covered with a sidewall protective layer. This allows the oxidation resistance to be further improved.
Ｃｕ配線の側壁に形成序れた遷移金属、あるいは、その
化合物の保護層と上部保護層によりＣｕは直接周囲の雰
囲気と触れることがない。そのため、Ｃｕの腐食および
酸化は完全に防ぐことができる。特に、側壁保護層を形
成した場合にはレジスト除去工程以前に側壁保護層がで
きるので、レジスト除去に０２プラズマアツシヤ等のＣ
ｕを酸化する可能性のある工程を用いることができる。Due to the protective layer and upper protective layer of a transition metal or its compound formed on the side wall of the Cu wiring, the Cu does not come into direct contact with the surrounding atmosphere. Therefore, corrosion and oxidation of Cu can be completely prevented. In particular, when a sidewall protective layer is formed, the sidewall protective layer can be formed before the resist removal process, so the resist can be removed using C
Any process that may oxidize u can be used.
また、Ｃｕ配線の周囲の遷移金属層もＣｕに比べ耐酸化
性の高い金属、あるいは、化合物が選択されるので、配
線自体の耐酸化性は従来のＣｕ配線に比べて非常に高い
。Further, since the transition metal layer surrounding the Cu wiring is also selected from a metal or compound that has higher oxidation resistance than Cu, the oxidation resistance of the wiring itself is much higher than that of conventional Cu wiring.
以下、本発明の一実施例を第１図により説明する。３は
Ｃｕ配線であり、コンタク１−孔を通じてＳｉ素子２と
接触している。このＣｕ配線３は、ＴｉＮより成るバリ
ヤメタル層１０と上部酸化防止層４、および、Ｗより成
る側壁保護層５により囲まれ、Ｓｉ素子、および、周囲
の雰囲気と直接触れることはない。図中１はＳｉ基板、
６はＳｉＯ２゜第２図は、本発明の一実施例を、プロセ
スを追い説明したものである。はじめに、Ｓｉ素子の形
成されたＳｉウェハ上に、ＴｉターゲットとＮ２の反応
性スパッタ法で形成されたＴｉＮ膜４，１０にはさまれ
たＣｕ膜７をスパッタ法により形成する。７，４．１０
の膜厚はそれぞれ８０００人。An embodiment of the present invention will be described below with reference to FIG. 3 is a Cu wiring, which is in contact with the Si element 2 through the contact 1 hole. This Cu wiring 3 is surrounded by a barrier metal layer 10 made of TiN, an upper antioxidation layer 4, and a sidewall protection layer 5 made of W, and does not come into direct contact with the Si element or the surrounding atmosphere. 1 in the figure is a Si substrate,
6 is SiO2. FIG. 2 is a process-by-step explanation of an embodiment of the present invention. First, a Cu film 7 sandwiched between a Ti target and TiN films 4 and 10 formed by reactive sputtering using N2 is formed by sputtering on a Si wafer on which Si elements are formed. 7,4.10
The film thickness of each is 8,000 people.
２００人、２００人である。次に、ホトリソグラフィ技
術により、レジスト８に配線パターンを形成し、ＴｉＮ
１ｌＩをＣＦ４によるドライエツチングで、Ｃｕ膜をＡ
ｒによるイオンミリングで加工し、配線パターンを形成
する。次に、基板全面に、Ｗ（Ｃｏ）ｃを原料とするプ
ラズマＣＶＤ法でＷより成る膜９を３００人形成する。200 people, 200 people. Next, a wiring pattern is formed on the resist 8 using photolithography technology, and a TiN
The Cu film was etched by dry etching with CF4.
A wiring pattern is formed by ion milling using r. Next, 300 people form a film 9 made of W on the entire surface of the substrate by plasma CVD using W(Co)c as a raw material.
第３図にプラス７ＣＶＤ装置を示す。Ｗ （Ｇ Ｏ）ｅ
１１は５０℃に加熱しＡｒをキャリヤガスとしてＣＶ
Ｄチャンバ１４内へ導入する。Ｗ （ＣＯ）ｅ導入管１
３およびＣＶＤチャンバ１４は、５０℃以上に保つ。基
板１５は下部のヒータ１６により１００℃〜２００℃に
加熱されている。ＣＶＤチャンバ１４内に導入されたＷ
（Ｃｏ）ｅは、高周波コイル１７により形成される高周
波プラズマ中で分解され、生成したＷが、基板上に腹を
形成する。この際、基板が１００℃以下ではＣｕ膜とＷ
膜との密若性が悪く。Figure 3 shows a plus 7 CVD apparatus. W (G O)e
11 was heated to 50℃ and CV was performed using Ar as a carrier gas.
Introduce it into the D chamber 14. W (CO)e introduction pipe 1
3 and the CVD chamber 14 are maintained at 50° C. or higher. The substrate 15 is heated to 100° C. to 200° C. by a heater 16 at the bottom. W introduced into the CVD chamber 14
(Co)e is decomposed in the high frequency plasma formed by the high frequency coil 17, and the generated W forms an antinode on the substrate. At this time, if the substrate is below 100°C, the Cu film and W
Poor adhesion to the membrane.
また、ち密なＷ膜を形成できない。反応の結果発生する
ＣＯはＣｕ表面の酸化膜を還元する。図中１２はるつぼ
状ヒータ、１８はキャリヤガス導入管、１９は排気管。Furthermore, a dense W film cannot be formed. CO generated as a result of the reaction reduces the oxide film on the Cu surface. In the figure, 12 is a crucible-shaped heater, 18 is a carrier gas introduction pipe, and 19 is an exhaust pipe.
第４図に５ｉＯｚ基板上のＣｕ膜上に本実施例にあるプ
ラズマＣＶＤによりＷ膜を形成したものについてのＳＩ
ＭＳ分析結果を示す。ＷとＣｕの界面には少量の酸素し
か検出されない。それに対し、Ｗ膜形成前のＣｕ膜表面
の分析結果（第５図）では表面にかなりの酸素が検出さ
れ、Ｗ膜の膜形成中に酸素が除かれていることがわかる
。さらに、ｗＢ形成時にキャリヤガス導入管１８よりキ
ャリヤガスと同時にＣＯをモル比１０％以下導入した場
合にはＣｕ表面の還元効果はより顕著であり、その際の
分析結果を第６図に示す。プラズマＣＶＤによるＷ囚の
形成後５基板全面をＡｒ＋イオン２ｏによりイオンミリ
ングする。イオンミリングの結果、水平面上に形成され
たＷ膜は除かれ、Ｃｕ配線の側壁部にのみＷ膜が残り、
側壁保護ＷＪ５となる。その後にレジスト８を除去し、
Ｃｕ配線パターンを完成する。Figure 4 shows the SI of a W film formed on a Cu film on a 5iOz substrate by plasma CVD in this example.
The MS analysis results are shown. Only a small amount of oxygen is detected at the interface between W and Cu. On the other hand, the results of analysis of the surface of the Cu film before the formation of the W film (FIG. 5) show that a considerable amount of oxygen was detected on the surface, indicating that oxygen was removed during the formation of the W film. Further, when CO is introduced at a molar ratio of 10% or less through the carrier gas introduction pipe 18 simultaneously with the formation of wB, the reduction effect on the Cu surface becomes more remarkable, and the analysis results in this case are shown in FIG. After forming W particles by plasma CVD, the entire surface of the five substrates is ion-milled using Ar+ ions 2o. As a result of ion milling, the W film formed on the horizontal plane was removed, and the W film remained only on the side walls of the Cu wiring.
It becomes side wall protection WJ5. After that, remove the resist 8,
Complete the Cu wiring pattern.
ＶＬＳ Ｉ製造プロセスでは配線の形成後にはプラズマ
ＣＶＤによる５ｉＯｚ膜形成等の工程があり、さらに、
加熱が加わるので、配線の熱安定性も重要な要素である
。Ｓｉ○２基板上のＣｕ膜上に本実施例によるプラズマ
ＣＶＤによりＷ膜を形成し、５００℃、六時間の熱処理
を実施後、ＳＩＭＳ分析を行なった結果を第４図に示す
。Ｃｕと固溶せず、また、金属間化合物も形成しないＷ
の場合にはＣｕとＷとの相互拡散はよく抑制されており
、Ｗ膜の表面にＣｕが現れることはない。それに対し、
Ｚｒ、Ｖ等に代表されるＣｕと固溶する金属でＣｕ表面
をおおう場合には、膜形成後にアニール工程があると表
面にＣｕが現れ、Ｃｕの酸化物が形成される。In the VLSI manufacturing process, after the wiring is formed, there are steps such as forming a 5iOz film by plasma CVD.
Thermal stability of the wiring is also an important factor since heating is applied. A W film was formed on the Cu film on the Si○2 substrate by plasma CVD according to this example, and after heat treatment at 500° C. for 6 hours, SIMS analysis was performed. The results are shown in FIG. W does not form a solid solution with Cu and does not form intermetallic compounds
In this case, mutual diffusion between Cu and W is well suppressed, and Cu does not appear on the surface of the W film. For it,
When the Cu surface is covered with a metal that dissolves in solid solution with Cu, such as Zr and V, when an annealing step is performed after film formation, Cu appears on the surface and a Cu oxide is formed.
Ｃｕ配線の側壁保護層としてＣｕと固溶しない金属であ
る。Ｗ、Ｍｏ、Ｒｅを用いることができる。また、Ｃｒ
＋ＪＣｕとの固溶量が非常に少なく、用いることができ
る。ＣＯを含む化合物でＣＶＤの原料として、Ｍｏ（Ｃ
Ｏ）ｅ、Ｗ （Ｃｏ）６゜Ｃｒ（ＣＯ）ａｔ Ｒｅｚ
（Ｃｏ）ｔｏを用いることができる。また、［（π−Ｃ
５Ｈ５） Ｗ （ＣＯ）３］２゜［（π−Ｃ３Ｈ６）Ｍ
ｏ（ＣＯ）３］！、 ［（π−Ｃ３Ｈ６）Ｃｒ（Ｃｏ）
３］ｚ（π−Ｃ５Ｈ６）Ｒｅ（Ｃｏ）３を用いる場合に
は、キャリヤガス中にＨ２を添加することがπＣ５Ｈａ
の還元のために必要である。遷移金属化合物ＷＮ、ＭＯ
２Ｎ、ＣｒｚＮを形成する際は、キャリヤガスにＮ Ｈ
ａを添加すれば良い。また、金属ソースの種類にかかわ
らず、キャリヤガスにＨ２を添加することにより、形成
される金属膜中のＯの量を一層減少させることができる
。この効果はｃｏよりも弱いが、キャリヤガスにＣＯを
添加した場合には、第６図に示すように、膜中のＣの濃
度が高くなるのに対し、Ｈ２添加の場合には、第７図に
示すように、Ｃの濃度を低く保ってＯの濃度を下げるこ
とができる。It is a metal that does not form a solid solution with Cu as a sidewall protective layer for Cu wiring. W, Mo, and Re can be used. Also, Cr
The amount of solid solution with +JCu is very small and it can be used. Mo(C) is a compound containing CO and is used as a raw material for CVD.
O) e, W (Co)6゜Cr(CO) at Rez
(Co)to can be used. Also, [(π-C
5H5) W (CO)3]2゜[(π-C3H6)M
o(CO)3]! , [(π-C3H6)Cr(Co)
3] When using z(π-C5H6)Re(Co)3, adding H2 to the carrier gas
It is necessary for the reduction of Transition metal compounds WN, MO
When forming 2N and CrzN, N H is added to the carrier gas.
Just add a. Furthermore, regardless of the type of metal source, by adding H2 to the carrier gas, the amount of O in the formed metal film can be further reduced. Although this effect is weaker than that of CO, when CO is added to the carrier gas, the concentration of C in the film increases as shown in Figure 6, whereas when H2 is added, the concentration of C in the film increases. As shown in the figure, the O concentration can be lowered while keeping the C concentration low.
本発明によれば、Ｃｕ表面の酸化物の除去と配線側壁へ
の遷移金属、あるいは、その化合物層の形成を同時に行
なうことができる。According to the present invention, it is possible to simultaneously remove the oxide on the Cu surface and form the transition metal or its compound layer on the wiring sidewall.
第１図は本発明の一実施例のＣｕ配線の断面図。
第２図は本発明の実施手順を示した図、第３図は本発明
の実施の際、Ｗ膜の形成に用いるプラズマＣＶ Ｄ装置
の構造を示す図、第４図はＳｉ○２鵡板」二のＣｕ膜上
にＷ（Ｇｏ）ｓをソースとしてＷ膜を形成し、５００℃
６時間の熱処理後ＳＩＭＳ分析を行なった結果を示す図
、第５図が同じ試料のＷ膜形成前の分析結果を示す図、
第６図はＷ膜形成の際、キャリヤガスにｃｏを添加した
場合の分析結果を示す図、第７図はキャリヤガスにＨ２
を添加した場合の分析結果を示す図である。
１・・・Ｓｉ基板、２・・・Ｓｉ素子、３・・・Ｃｕ配
線、４・・・上部酸化防止層、５・・・側壁保護層、６
・・・５ｊ−Ｏｚ、７・・・Ｃｕ膜、８・・・レジスト
、９・・・ＣＶＤＷ膜。
】０・・・バリヤ層、１１・・・Ｗ（Ｃｏ）ｅ、１２・
・・るっぼ状ヒータ、１３・・・Ｗ（Ｃｏ）６導入管、
１４・・・ＣＶＤチャンバ、１５・・・基板、１６・・
・基板ヒータ、１７・・高周波コイル、１８・・・キャ
リヤガス導入管、第１図
第２図
第３図
第４図
第５図
第６図FIG. 1 is a sectional view of Cu wiring according to an embodiment of the present invention. Fig. 2 is a diagram showing the implementation procedure of the present invention, Fig. 3 is a diagram showing the structure of a plasma CVD apparatus used for forming a W film when implementing the present invention, and Fig. 4 is a diagram showing the structure of a plasma CVD apparatus used for forming a W film in the implementation of the present invention. A W film was formed on the second Cu film using W(Go)s as a source, and heated at 500°C.
Figure 5 shows the results of SIMS analysis after 6 hours of heat treatment, Figure 5 shows the analysis results of the same sample before formation of the W film,
Figure 6 shows the analysis results when Co was added to the carrier gas during W film formation, and Figure 7 shows the analysis results when Co was added to the carrier gas.
It is a figure showing the analysis result when adding. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Si element, 3... Cu wiring, 4... Upper antioxidation layer, 5... Sidewall protective layer, 6
... 5j-Oz, 7... Cu film, 8... Resist, 9... CVDW film. ]0... Barrier layer, 11... W(Co)e, 12...
...Rubbo-shaped heater, 13...W(Co)6 introduction pipe,
14...CVD chamber, 15...substrate, 16...
・Substrate heater, 17...High frequency coil, 18...Carrier gas introduction pipe, Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6
Claims (1)
アスペクト比が１以上の、銅あるいは銅を主成分とする
ＶＬＳＩ用微細配線において、前記配線の周囲を全て導
電性の膜でおおうことを特徴とするＶＬＳＩ用銅配線方
法。 ２、半導体素子上に、バリヤメタル層、銅配線層、上部
酸化防止メタル層より成る配線層を形成し、ホトレジス
トで配線パターンを形成し、前記配線層をエッチングし
て配線を形成し、レジストを除去する工程からなるＶＬ
ＳＩ用銅配線において、 前記配線層のエッチング工程の後にＣＶＤ法により遷移
金属、もしくは、その化合物層を全面に形成し、その後
に異方性エッチングにより配線パターンの段差側壁部に
のみ選択的に前記遷移金属もしくはその化合物層を残し
、その後、前記レジストを除去することを特徴とするＶ
ＬＳＩ用銅配線方法。 ３、特許請求の範囲第２項において、 前記遷移金属が銅と固溶せず、かつ、銅と金属間化合物
を形成しない金属であることを特徴とするＶＬＳＩ用銅
配線方法。[Claims] 1. Wiring width 0.5 μm or less formed on a semiconductor element,
1. A copper wiring method for VLSI, which comprises covering the entire periphery of the wiring with a conductive film in fine wiring for VLSI which has an aspect ratio of 1 or more and is copper or whose main component is copper. 2. Form a wiring layer consisting of a barrier metal layer, a copper wiring layer, and an upper anti-oxidation metal layer on the semiconductor element, form a wiring pattern with photoresist, etch the wiring layer to form a wiring, and remove the resist. VL consists of the process of
In copper wiring for SI, after the etching process of the wiring layer, a transition metal or its compound layer is formed on the entire surface by CVD, and then anisotropic etching is performed to selectively remove the transition metal or its compound layer only on the stepped sidewalls of the wiring pattern. V characterized in that the transition metal or its compound layer is left and then the resist is removed.
Copper wiring method for LSI. 3. The copper wiring method for VLSI according to claim 2, wherein the transition metal is a metal that does not form a solid solution with copper and does not form an intermetallic compound with copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2754388A JPH01204449A (en) | 1988-02-10 | 1988-02-10 | Copper wiring method for vlsi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2754388A JPH01204449A (en) | 1988-02-10 | 1988-02-10 | Copper wiring method for vlsi |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01204449A true JPH01204449A (en) | 1989-08-17 |
Family
ID=12224000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2754388A Pending JPH01204449A (en) | 1988-02-10 | 1988-02-10 | Copper wiring method for vlsi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01204449A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5164332A (en) * | 1991-03-15 | 1992-11-17 | Microelectronics And Computer Technology Corporation | Diffusion barrier for copper features |
| US5506449A (en) * | 1993-03-24 | 1996-04-09 | Kawasaki Steel Corporation | Interconnection structure for semiconductor integrated circuit and manufacture of the same |
| WO2000005773A1 (en) * | 1998-07-23 | 2000-02-03 | Applied Materials, Inc. | Integrated circuit interconnect lines having sidewall layers |
-
1988
- 1988-02-10 JP JP2754388A patent/JPH01204449A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5164332A (en) * | 1991-03-15 | 1992-11-17 | Microelectronics And Computer Technology Corporation | Diffusion barrier for copper features |
| US5506449A (en) * | 1993-03-24 | 1996-04-09 | Kawasaki Steel Corporation | Interconnection structure for semiconductor integrated circuit and manufacture of the same |
| WO2000005773A1 (en) * | 1998-07-23 | 2000-02-03 | Applied Materials, Inc. | Integrated circuit interconnect lines having sidewall layers |
| JP2002521826A (en) * | 1998-07-23 | 2002-07-16 | アプライド マテリアルズ インコーポレイテッド | Interconnect wiring for integrated circuits with sidewall layers |
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