JPH01239932A - Dry-etching of polysilicide structure gate laminate film - Google Patents

Abstract

PURPOSE:To form gate wiring which is rectangle-shaped in cross section and tapered at a upper end thereof by etching a gate laminate film composed of an upper layer silicide film and a lower layer polysilicon film using a predetermined etching gas. CONSTITUTION:A polysilicide structure gate laminate film composed of an upper silicide film 5 and a lower polysilicon film 11 both formed on a gate oxide film 6 on a substrate 1 is rendered to reactive ion etching by etching gas involving chlorine gas including a chlorine atom in a molecule and nitrogen gas using a resist pattern 7 as a mask. Hereby, an adherend 9 is formed during the etching on the side wall of the resist pattern 7 and on the side wall of the upper layer silicide film 12. When the adherend 9 and the resist pattern 7 are exfoliated, the upper layer silicide film 12 is etched into a trapezoid shape directed upward and into a rectangle shape in cross section with a tapered gate the upper end of which is pointed upward. Hereby, any current leakage between metal wiring and gate wiring is prevented from being produced together with elimination of variations of a gate length.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a dry etching method for a polysilicide structure gate stacked film, and in particular, it relates to a method for dry etching a gate stacked film having a polysilicide structure. The present invention relates to a method for forming gate wiring on a substrate.

[Prior art] and [Issues to be solved by the invention]
In the VLSI manufacturing process, dry etching technology is widely used to form fine patterns with high precision. In particular, the etching of the gate of a MOS transistor determines the characteristics of the transistor, and the most accurate etching method is applied.

However, when a high-precision processing method such as reactive ion etching is applied to gate processing, the cross-sectional shape after processing becomes a rectangular shape with right angle corners, which causes problems in subsequent processes. It's here. This problem will be explained using FIG. 2.

FIG. 2 is a cross-sectional view of a substrate in which an interlayer insulating film and metal wiring are further formed on a substrate on which a gate wiring having a rectangular cross-sectional shape is formed. In the figure, 1 is a silicon substrate. A gate wiring 2 is formed on a silicon substrate 1, and an interlayer insulating film 3 is formed thereon. A contact hole 4 is formed in the interlayer insulating film 3 . Then, metal wiring 5 is formed thereon. For example, aluminum wiring is used for the metal wiring 5.

Referring to FIG. 2, gate wiring 2 has a rectangular cross-sectional shape, and both upper end portions 2a thereof are formed at right angles.

Therefore, since the thickness of the interlayer insulating film 3 is insufficient in the contact hole 4 portion, current leakage easily occurs between the metal wiring 5 and the gate wiring 2. The occurrence of this current leakage is the biggest problem when using a gate wiring having a rectangular cross-sectional shape.

In order to solve this problem, as shown in FIG. 3, it is necessary to make the cross-sectional shape of the gate wiring 2 rectangular and to make the upper end 2a a tapered shape. With such a tapered shape, the interlayer insulating film 3 is formed in the contact hole 4 portion.
The film thickness of metal wiring 5 and gate wiring 2 is no longer insufficient.
Current leakage will no longer occur between the two.

Next, a conventional method attempted to prevent current leakage between metal wiring and gate wiring will be described.

FIGS. 4A and 4B show the first example, which is shown in cross-section.

In the figure, 1 is a silicon substrate, 6 is a gate oxide film formed on the silicon substrate 1, 8 is a gate formed on the gate oxide film 6, and 7 is a resist pattern (hereinafter simply referred to as resist).

In summary, the first method takes advantage of resist wear during etching to adjust the taper angle of resist 7 to gate 8.
This is a method of transferring images to When the resistor is removed, the fourth
A trapezoidal gate 8 facing upward is obtained as shown in Figure B. Note that the cross-sectional shape of this gate 8 differs from the shape of the gate shown in FIG. 3 in that the side walls of the gate 8 are not perpendicular to the substrate 1. This method has poor reproducibility in forming a taper in the resist 7, and since the sidewalls of the gate 8 are not perpendicular to the substrate 1, it is difficult to control the gate length, and is therefore impractical.

FIGS. 5A and 5B show the second example, which is shown in cross-section. In the figure, 1 is a silicon substrate, 6 is a gate oxide film formed on the silicon substrate 1, 8 is a gate formed on the gate oxide film 6,
7 is a resist, 9 is a deposit attached to the side wall of the gate 8 and the side wall of the resist 7, and 10 is a pattern consisting of the gate 8 and the resist 7. The second example, in summary, involves plasma polymerization during etching and deposits 9 on the sidewalls.
In this method, the pattern 10 is processed while being formed and thickened. When the deposits 9 on the resist and side walls are peeled off, an upwardly facing trapezoidal gate 8 is obtained as shown in FIG. 5B. Note that the cross-sectional shape of the gate 8 is such that the side wall of the gate 8 is not perpendicular to the substrate 1.
The shape of the gate is different from that shown in FIG. This method is
By optimizing the etching conditions, a taper can be formed with good reproducibility, but since the pattern 10 is tailed, the controllability of the gate length is poor, as in the first example.

FIGS. 6A and 6B show the third example, which is shown in cross-section.

In the figure, 1 is a silicon substrate, 6 is a gate oxide film formed on the silicon substrate 1, 8 is a gate formed on the gate oxide film 6, 7 is a resist, and 9 is a side wall of the gate 8 and the resist 7. It is a deposit that has adhered to the surface. This third example is a method in which the second method described above is applied in the first step, and then etched in the vertical direction in the second step.

When the deposits 9 on the resist and side walls are peeled off, the 6th B
A gate 8 shown in the figure is obtained which has a rectangular cross-sectional shape and a tapered upper end. The shape of the gate 8 obtained by this method is the same as the shape of the gate shown in FIG. Large variations occur during the transition to the second stage, resulting in variations in gate length.

As described above, although all of the conventional methods can obtain a gate having a shape that does not cause current leakage, there is a problem in that the gate length varies because it is difficult to control the gate length.

This invention was made in order to solve the above-mentioned problems, and provides a dry etching method for a polysilicide structure gate laminated film that provides a gate shape that does not cause current leakage and does not cause variations in gate length. The purpose is to provide.

[Means for Solving the Problems] The present invention is a method for forming, on a substrate, a gate wiring having a rectangular cross-sectional shape and a tapered upper end that tapers upward. Contains processes.

(1) A step of preparing a substrate on which a gate stacked film having a polysilicide structure consisting of an upper silicide film and a lower polysilicon film is formed.

(2) A step of forming a resist pattern on the gate laminated film.

(3) A step of performing reactive ion etching on the gate laminated film using an etching gas using the resist pattern as a mask.

The etching gas contains at least a chlorine-based gas containing chlorine atoms in its molecules and nitrogen gas.

[Operation] When a gate stacked film with a polysilicide structure consisting of an upper silicide film and a lower polysilicon film is subjected to reactive ion etching using an etching gas containing chlorine gas containing chlorine atoms in the molecule and nitrogen gas, Although the mechanism is not clear, a phenomenon occurs during etching in which deposits are formed only on the sidewalls of the resist pattern and the sidewalls of the upper silicide film, but not on the sidewalls of the lower polysilicon film.

When deposits are formed on the side walls of the resist pattern and the side walls of the upper silicide film, the upper silicide film is tapered by following the same route as shown in FIG. 5A. On the other hand, since no deposits are formed on the side walls of the lower polysilicon film, the lower polysilicon film is etched vertically. This vertical etching process has good precision, so
As a result, no variation in gate length occurs.

[Example] An embodiment of this invention will be described below.

FIG. 1A and FIG. 1B are sectional views showing the state after implementing the present invention.

In the figure, 1 is a silicon substrate, and 6 is a gate oxide film formed on this silicon substrate 1. A gate laminate film having a polysilicide structure is formed on the gate oxide film 6, and includes an upper silicon layer, a side film 12, and a lower polysilicon film 11. This gate laminate film is coated with butter using the resist pattern 7 as a mask. has been updated. In the embodiment, tungsten silicide was used as the upper silicide film 12 and polysilicon was used as the lower polysilicon film 11, but the present invention is not limited thereto. Sidewalls of resist 7 and upper silicide film 12
A deposit 9 is formed on the side wall of. FIG. 1B shows the state when the resist 7 and the deposits 9 on the side walls are peeled off.

Referring to FIG. 1B, upper silicide film 12 is etched into an upward trapezoidal shape, and lower seven-layer polysilicon film 11 is etched into a rectangular shape. That is, a gate (a gate consisting of the upper silicide film 12 and the lower polysilicon film 11) is realized which has a rectangular cross-sectional shape and whose upper end is tapered upward.

Since the upper end of the gate is tapered, when an LSI as shown in FIG. 3 is formed, the thickness of the interlayer insulating film 3 is maintained at a sufficient thickness in the contact hole 4 portion.
No current leakage occurs between the metal wiring 5 and the gate wiring 2.

Next, the etching method will be explained. Tungsten silicide was used for the upper silicide film 12, and polysilicon was used for the lower polysilicon film 11. A mixed gas consisting of chlorine gas and nitrogen gas was used as the etching gas. The reaction conditions were chlorine gas 30cc/min, nitrogen gas 30cc/min, pressure 40mTorr, and RF power 4.
This was done at 00W.

During etching under these conditions, resist pattern 7
and the side wall of the tungsten silicide 12,
Deposits 9 were attached. However, polysilicon 11
No deposits were observed on the side walls.

Although the principle of this etching is not yet clear, it is thought that chlorine gas forms chlorides of tungsten and silicon, which contribute to etching the tungsten silicide 12 and the polysilicon film 11. Further, the nitrogen gas as an additive is considered to contribute to the polymerization of the reaction product by forming nitrides.

Also, during etching, deposits 9 are formed on the side walls of the resist pattern 7 and the side walls of the tungsten silicide film 12.
However, the reason for this phenomenon has not yet been elucidated. However, for this phenomenon to occur,
The upper silicide film 12 is etched into an upward trapezoidal shape, and the lower polysilicon film 11 is etched vertically. Since this vertical etching process has good precision, as a result, no variation in gate length occurs. Then, a gate wiring having the shape shown in FIG. 1B is obtained. Although the case where chlorine is used as the chlorine-based gas has been described here, any gas containing chlorine atoms and generating chlorine radicals may be used.

In a preferred embodiment, a second additional etching step (hereinafter referred to as the first step) is performed. This is because even after the polysilicon film is completely removed by etching, a residual film remains in the parts of the substrate 1 where the etching speed is slow, and a residual film also occurs in the stepped parts, and it is necessary to remove these residual films. This is because there is. In this additional etching (hereinafter referred to as overetching) for removing the remaining film, since there is almost no deposit on the sidewalls of the polysilicon film 11, the sidewalls of the polysilicon film 11 are attacked by chlorine radicals and etched laterally. There is a possibility that Therefore, it is necessary to perform overetching under conditions different from those of the first step. The conditions for this overetching are chlorine gas 30cc/min, nitrogen gas 30cc/min, 5i
C1l! ,.

20cc/min, pressure 40mTorr, RF power 4
It was found that 00w is optimal. It was confirmed that when overetching was performed under these conditions, the remaining film was removed without any effect on the end face shape of the gate. Note that this overetching step is a preferred embodiment and is not essential to the present invention.

Table 1 summarizes the results obtained by the above etching process. Note that in Table 1, the Taber angle formed in tungsten silicide can be easily changed by changing the nitrogen concentration in the gas.

Table I Although the present invention has been described with reference to specific examples, the present invention may be embodied in various other forms without departing from its spirit or essential characteristics. Therefore, the above-described embodiments are merely illustrative in all respects and should not be construed as limiting. The scope of the present invention is indicated by the claims, and is not restricted in any way by the main text of the specification. Furthermore, all modifications and changes that come within the scope of equivalents of the claims are intended to be within the scope of the present invention.

[Effects of the Invention] As described above, according to the present invention, a gate wiring having a rectangular cross-sectional shape and a tapered upper end can be obtained. Therefore, current leakage will not occur and variations in gate length will not occur.

[Brief explanation of the drawing]

FIG. 1A and FIG. 1B are diagrams showing an embodiment of the present invention. FIG. 2 is a cross-sectional view of an LSI equipped with gate wiring having a rectangular cross-sectional shape. Figure 3 shows an LSI with a gate wiring whose cross section is rectangular and whose upper end is tapered.
FIG. FIGS. 4A and 4B are cross-sectional views showing a first conventional example of gate taper processing. FIGS. 5A and 5B are cross-sectional views showing a second conventional example of gate taper processing. FIGS. 6A and 6B are cross-sectional views showing a third conventional example of gate taper processing. In the figure, 1 is a silicon substrate, 2 is a gate wiring, 7 is a resist pattern, 9 is a deposit, 11 is a lower polysilicon film, and 12 is an upper silicide film. In each figure, the same reference numerals indicate the same or corresponding parts. Yes, Figure +A, Figure 4, Figure 4B, Figure B, Figure 6β.

Claims (1)

[Claims] A method for forming a gate wiring on a substrate, the gate wiring having a rectangular cross-sectional shape and a tapered upper end tapering upward, the gate wiring comprising an upper silicide film and a lower polysilicon film. a step of preparing a substrate on which a gate laminated film having a polysilicide structure is formed; a step of forming a resist pattern on the gate laminated film; and a step of forming a resist pattern on the gate laminated film using an etching gas using the resist pattern as a mask. and performing reactive ion etching on the gate stacked film using a polysilicide structure gate stacked film, wherein the etching gas contains at least a chlorine-based gas containing chlorine atoms in its molecules and nitrogen gas. dry etching method.