JP2008135534A - Manufacturing method of semiconductor substrate comprising bottomed slot - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for forming a slot whose upper part is rounded by dry etching with a semiconductor material, utilizing the gas containing no carbon. <P>SOLUTION: A semiconductor substrate comprising a bottomed slot 30 is manufactured. Firstly, a semiconductor material 10 is prepared which comprises a masked region 10b which is covered with a mask 20 containing semiconductor material carbon and a non-masked region 10c which is not covered with the mask. By supplying the gas that contains no carbon toward both the mask 20 and the non-masked region 10c, the bottomed slot 30 that extends from the non-masked region 10c toward the inside of the semiconductor material 10 is formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor substrate having a bottomed groove.

For example, a semiconductor device having a trench gate electrode is widely known. When manufacturing such a semiconductor device, first, a bottomed groove is formed in a semiconductor material. Next, a trench gate electrode is formed in the trench. As a method for forming a bottomed groove in a semiconductor material, the following Patent Documents 1 and 2 are known.
The method of Patent Document 1 will be described with reference to FIG. A semiconductor material 110 having a mask 120 in contact with the surface is prepared. This mask 120 is a silicon oxide film. The mask 120 has an opening 118. Before the trench 130 is formed, the upper surface of the semiconductor material 110 is flat. That is, the semiconductor material 110 exists up to the position indicated by the broken line in FIG. A gas not containing carbon is supplied toward the upper surface of the mask 120. As a result, the semiconductor material 110 existing in the portion corresponding to the opening 118 of the mask 120 is etched, and the groove 130 is formed. In the case of dry etching, an oxide film 132 is formed on the side and bottom surfaces of the groove 130 of the semiconductor material 110. Etching of the semiconductor material 110 on which the oxide film 132 is formed is less likely to proceed. However, the bottom surface of the groove 130 is etched due to the effect of sputtering by ions. On the other hand, since the high pressure gas is not supplied to the side surface of the groove 130 as much as the bottom surface, the side surface of the groove 130 in which the oxide film 132 is formed is not easily etched. As a result, a groove 130 having a width that substantially matches the width of the opening 118 of the mask 120 is formed. Next, a trench gate electrode (not shown) is formed in the trench 130. Through such a process, a semiconductor device having a trench gate electrode is manufactured.

Next, the method of Patent Document 2 will be described with reference to FIG. In the method of Patent Document 2, the groove 230 is formed in the semiconductor material 210 by performing dry etching using a gas containing carbon. The mask 220 in contact with the surface of the semiconductor material 210 is composed of a silicon oxide film and a silicon nitride film. A gas containing carbon (a mixed gas of C ₄ F ₈ and Ar) is supplied toward the upper surface of the mask 220. As a result, the semiconductor material 210 is etched and a groove 230 is formed. When dry etching is performed using a gas containing carbon, oxygen in the oxide film formed on the side and bottom surfaces of the groove 230 reacts with carbon in the gas to become hydrocarbons (for example, carbon monoxide). Almost no oxide film is formed in 230. For this reason, the etching also proceeds on the side surface of the groove 230. As a result, a groove 230 having a width wider than the width of the opening 218 of the mask 220 is formed.

JP 2006-196523 A JP 2006-237182 A

  As described above, when dry etching is performed using a gas not containing carbon (in the case of Patent Document 1), there is almost no dimensional difference between the width of the opening 118 of the mask 120 and the width of the groove 130, and the intended width is obtained. A groove 130 can be formed. However, in the example of FIG. 10, the upper part 130a of the groove 130 is angular. It is known that when the upper portion 130a of the groove 130 is angular, the electric field tends to concentrate on the upper portion 130a of the groove 130 when the completed semiconductor device is energized. This is described in paragraph “0003” of Patent Document 2, for example. If there is a portion where the electric field tends to concentrate, the semiconductor device is likely to be damaged.

On the other hand, Patent Document 2 discloses that when dry etching is performed using a high-order fluorocarbon gas (for example, C ₄ F ₈ ), roundness is formed in the upper part of the groove. However, when dry etching is performed using a gas containing carbon, as shown in FIG. 11, the entire side surface of the groove 230 is over-etched. Since the dimensional difference between the width of the opening 218 of the mask 220 and the width of the groove 230 becomes large, the groove 230 having the intended width cannot be formed.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to form a groove having a rounded upper portion by dry etching a semiconductor material using a gas not containing carbon.

In the present invention, a semiconductor substrate having a bottomed groove is manufactured. This manufacturing method includes a preparation step of preparing a semiconductor material having a mask covering region covered with a mask containing carbon and a mask non-covering region not covered with the mask. Furthermore, a groove forming step is provided for forming a bottomed groove extending from the non-mask covering region into the semiconductor material by supplying a gas not containing carbon toward both the mask and the non-mask covering region.
The above-mentioned “supplying a gas not containing carbon toward both the mask and the non-mask covering region” means supplying a gas at least near the opening of the mask. The gas may be supplied toward the entire surface of the mask, or the gas may be supplied only in the vicinity of the opening of the mask.
In this method, the mask contains carbon. The gas supplied toward the mask erodes the mask. As a result, carbon is supplied from the mask. The carbon supplied from the mask enters the groove together with the gas. A large amount of carbon is supplied to the upper part of the groove near the mask. For this reason, it is difficult to form an oxide film on the side surface of the upper portion of the groove. Etching is easy to proceed on the side surface of the upper part of the groove, and roundness is formed on the upper part of the groove.
On the other hand, the lower part of the groove is supplied with a large amount of gas that is supplied toward the non-mask covering region and does not contain carbon. Some of the carbon from the mask may also be supplied to the bottom of the trench. However, the amount of carbon supplied to the lower part of the groove far from the mask is smaller than the amount of carbon supplied to the upper part of the groove near the mask. For this reason, compared with the upper part of the groove, an oxide film is easily formed in the lower part of the groove, and the side surface of the lower part of the groove is less likely to be etched. It is possible to prevent the side surface at the bottom of the groove from being over-etched.
According to this method, a groove having a roundness at the top can be formed by dry etching. Moreover, since dry etching is performed using a gas not containing carbon, it is possible to prevent the entire side surface of the groove from being over-etched. According to this method, a semiconductor substrate in which a groove having an intended width is formed can be manufactured.

The semiconductor substrate manufactured by the above method can be suitably used for a semiconductor device having a trench gate electrode. In this case, an insulating layer may be formed on the side and bottom surfaces of the groove, and then the trench gate electrode may be formed in the groove.
If the upper portion of the groove is angular, the insulating layer formed in that portion becomes thin. In this case, when the trench gate electrode is energized, the electric field is concentrated on the upper portion of the groove (thin portion of the insulating layer). On the other hand, since the semiconductor substrate manufactured by this method has roundness formed in the upper part of the groove, the thickness of the insulating layer formed in that portion can be increased. For this reason, when the trench gate electrode is energized, the electric field is less likely to concentrate on the upper portion of the trench. A semiconductor device that exhibits stable electrical characteristics can be realized.
In addition, the semiconductor substrate manufactured by this method may be used for a semiconductor device in which electronic components other than electrodes are arranged in the groove. For example, it may be used for a semiconductor device in which a conductor other than an electrode is disposed in the groove.

  The semiconductor material may be made of silicon. On the other hand, the semiconductor material may be composed of other materials such as gallium nitride, silicon carbide, gallium arsenide.

The mask may be a single layer mask or a multilayer mask. In the former case, the single layer mask contains carbon. In the latter case, it is preferable that at least the uppermost layer contains carbon. Note that all layers of the multilayer mask may contain carbon, or only the uppermost layer of the multilayer mask may contain carbon.
In the method of the present invention, either a single layer mask or a multilayer mask may be used, but it is preferable to use a multilayer mask. The reason for this will be described below. When a single layer mask is used, a gas supplied toward the single layer mask erodes the single layer mask. Single layer masks are susceptible to erosion in the vicinity of the opening. For this reason, the width of the opening of the single-layer mask is increased in the process of forming the groove. When the width of the opening of the single layer mask is increased, the width of the groove formed in accordance with the shape of the opening is also increased. For this reason, when a single layer mask is used, it is difficult to form a groove having an intended width. On the other hand, when the multilayer mask is used, even if the uppermost layer is eroded and the width of the opening is widened, the shape of the opening of the lower layer is maintained. For this reason, a groove having an intended width can be formed.

When using a multilayer mask, the mask may be configured as follows. That is, the mask may have a first mask and a second mask. The first mask is in contact with the surface of the semiconductor material and may have a predetermined mask pattern. The second mask is in contact with the surface of the first mask, has the above-described predetermined mask pattern, and may contain carbon.
In this configuration, a two-layer mask is used. The second mask which is the upper layer contains carbon. For this reason, the second mask is eroded by the gas, and carbon is supplied from the second mask. Note that the first mask, which is the lower layer, may contain carbon or may not contain carbon.
According to this configuration, even when the second mask is eroded by the gas, the shape of the opening of the first mask is maintained. For this reason, a groove having an intended width can be formed.

  The first mask may be made of an insulator. When a mask is formed using an insulator, a desired mask pattern can be formed with high accuracy. For this reason, a groove having an intended shape can be formed.

When the first mask is an insulator, the above preparation process may include the following processes. That is, a step of preparing a semiconductor material having an insulator region in contact with the surface may be provided. And forming a second mask covering region covered with the second mask having the predetermined mask pattern and a second mask non-covering region not covered with the second mask on the surface of the insulator region. You may have. And forming a first mask having the predetermined mask pattern by forming a hole extending from the second mask uncovered region of the insulator region to the surface of the semiconductor material in the insulator region. Also good.
In this way, two layers made of different materials can be formed in the same mask pattern.

Embodiments of the present invention will be described with reference to the drawings. In this embodiment, a semiconductor substrate in which a trench gate electrode is formed in a trench is manufactured. This manufacturing process will be described in order. In the following description, for each component, the upper surface shown in each drawing is the front surface, and the lower surface is the back surface.
First, the semiconductor material 10 shown in FIG. 1 is prepared. FIG. 1 shows a cross-sectional view of a semiconductor material 10. The semiconductor material 10 is made of silicon.
The insulator region 12 is in contact with the surface 10 a of the semiconductor material 10. The insulator region 12 of the present embodiment is formed by performing CVD (Chemical Vapor Deposition) on the surface 10a of the semiconductor material 10 having the thickness D2. The insulator region 12 does not contain carbon.
The insulator region 12 may be formed by oxidizing (for example, thermal oxidation) the semiconductor material 10 having the thickness D1.

Next, as shown in FIG. 2, a resist mask 14 is formed on the surface 12 a of the insulator region 12. In this embodiment, the resist mask 14 is formed using photolithography. The resist material used for photolithography contains carbon. For example, the resist material of this embodiment is a novolac resin. Since the resist material contains carbon, the resist mask 14 also contains carbon.
The resist mask 14 has an opening 16. For this reason, a region 12 b covered with the resist mask 14 and a region 12 c not covered with the resist mask 14 are formed on the surface 12 a of the insulator region 12. Hereinafter, the former region 12b is referred to as a resist coating region, and the latter region 12c is referred to as a resist non-covering region.

Subsequently, dry etching is performed on the surface 12 a of the insulator region 12. In this embodiment, reactive ion etching (RIE) is performed. Moreover, the etching gas of this embodiment contains carbon. For example, a mixed gas having a ratio of CF ₄ , CHF ₃ and Ar of 9: 1: 100 is used. The RF frequency is in the range of 380 KHz to 13.56 MHz. The gas pressure is 30 to 200 mTorr.
As shown in FIG. 3, the resist-coated region 12b is not etched, but the resist-uncoated region 12c is etched. As a result, a hole 18 extending from the resist uncoated region 12 c to the surface 10 a of the semiconductor material 10 is formed in the insulator region 12. A hole 18 having the same width as the opening 16 of the resist mask 14 is formed in the insulator region 12. That is, the insulator mask 12 having the same mask pattern as the resist mask 14 is formed. In the present embodiment, trench etching, which will be described later, is performed using the two mask layers of the insulator mask 12 and the resist mask 14. That is, in this embodiment, a multilayer mask is used. Hereinafter, the insulator mask 12 and the resist mask 14 may be simply referred to as a mask 20.
When the insulator mask 12 is formed, a part 10c of the surface 10a of the semiconductor material 10 is exposed. That is, on the surface 10 a of the semiconductor material 10, a region 10 b covered with the mask 20 and a region 10 c not covered with the mask 20 are formed. Hereinafter, the former region 10b is referred to as a mask covering region, and the latter region 10c is referred to as a mask non-covering region.

Next, dry etching is performed on the surface 10 a of the semiconductor material 10. In this embodiment, reactive ion etching is performed. This etching gas does not contain carbon. As the etching gas, for example, SF ₆ , HBr, NF ₃ , SiF ₄ or the like can be used. Etching conditions include an SF ₆ / O ₂ ratio of 0.5 to 1.5, an RF power of 500 to 1500 W, and a pressure of 10 to 100 mT.
As shown in FIG. 4, the etching gas is supplied to both the surface 14 a of the resist mask 14 and the unmasked region 10 c of the semiconductor material 10. The mask covering region 10b is not etched, but the mask non-covering region 10c is etched. As a result, a groove 30 extending from the non-mask covering region 10 c toward the semiconductor material 10 is formed. The gas supplied toward the resist mask 14 erodes the resist mask 14. That is, the resist mask 14 is gradually removed. As a result, carbon is supplied from the resist mask 14. The carbon supplied from the resist mask 14 enters the groove 30 together with the gas. A large amount of carbon is supplied to the side surface 30 a of the upper portion of the groove near the resist mask 14. This carbon reacts with oxygen in the oxide film formed on the side surface 30a at the upper part of the groove to become carbon monoxide. For this reason, it is difficult to form an oxide film on the side surface 30a of the upper portion of the groove. Since the oxide film is not easily formed on the side surface 30a of the upper portion of the groove, the etching is likely to proceed. The side surface 30a at the top of the groove is slightly over-etched. As a result, a roundness (taper) is formed on the side surface 30a of the upper portion of the groove. The side surface 30 a at the upper part of the groove is located outside the hole (opening) 18 of the insulator mask 12.

  As the dry etching progresses, the groove 30 becomes deeper. FIG. 5 shows a groove 30 formed to a desired depth. As described above, since a large amount of carbon is supplied to the upper portion of the groove, the side surface 30a of the upper portion of the groove is rounded. On the other hand, the lower part of the groove is supplied with a large amount of gas that is supplied toward the non-mask covering region 10c and does not contain carbon. Some of the carbon from the resist mask 14 may also be supplied to the bottom of the trench. However, the amount of carbon supplied to the lower part of the groove far from the resist mask 14 is smaller than the amount of carbon supplied to the upper part of the groove near from the resist mask 14. For this reason, compared with the upper part of the groove, the oxide film 32 is easily formed in the lower part of the groove, and the side surface 30b of the lower part of the groove is less likely to be etched. It is possible to prevent the side surface 30b below the groove from being over-etched. The groove 30 is less likely to be etched as the side surface is deeper. For this reason, the entire side surface of the groove 30 has a tapered shape.

  In addition, another reason can be guessed as a reason why the roundness is formed on the side surface 30a of the upper part of the groove. As shown in FIG. 5, the resist mask 14 is scraped as dry etching progresses. In particular, the vicinity of the opening 16 of the resist mask 14 is scraped off. When the vicinity of the opening 16 of the resist mask 14 is cut, it is considered that the amount of carbon supplied from the resist mask 14 into the groove 30 is reduced. That is, it is considered that the amount of carbon supplied from the resist mask 14 into the groove 30 is large in the initial stage of dry etching, and the amount of carbon supplied from the resist mask 14 to the groove 30 is reduced as dry etching proceeds. In this case, in the initial stage of dry etching, since the amount of carbon supplied into the trench 30 is large, the oxide film 32 is hardly formed on the side surface 30a of the trench upper portion. As a result, the etching of the side surface 30a at the upper part of the groove proceeds, and the side surface 30a at the upper part of the groove is rounded. On the other hand, in the final stage of dry etching, the amount of carbon supplied into the groove 30 is small, so that the oxide film 32 is easily formed in the groove 30. As a result, the etching of the side surface 30b at the bottom of the groove is difficult to proceed, and the side surface 30b at the bottom of the groove is prevented from being over-etched.

  As the vicinity of the opening 16 of the resist mask 14 is shaved, the width of the opening 16 of the resist mask 14 changes. However, in this embodiment, since the multilayer mask is used, the width of the opening 18 of the insulator mask 12 is maintained even if the width of the opening 16 of the resist mask 14 is changed. Etching proceeds while the width of the opening 18 of the insulator mask 12 is maintained. Even if the resist mask 14 is shaved, the groove 30 having a shape according to the opening 18 of the insulator mask 12 can be formed. A groove 30 having an intended shape can be formed.

  When dry etching is performed using a gas not containing carbon, an oxide (so-called residue) 36 extending upward from the bottom surface 30c of the groove 30 may be formed. In this embodiment, dry etching is performed using a gas not containing carbon, but carbon is supplied from the resist mask 14 into the groove 30. As this carbon reacts with the oxide 36, the oxide 36 is removed. In the present embodiment, the oxide 36 is hardly formed on the bottom surface 30 c of the groove 30, and it is not necessary to perform a step of removing the oxide 36 after forming the groove 30.

  Subsequently, the resist mask 14 and the insulator mask 12 are removed. FIG. 6 shows the semiconductor material 10 after this removal step has been performed. This removal step can be performed using various known methods. For example, the resist mask 14 can be removed by ashing.

Next, the surface 10 a of the semiconductor material 10 and the inside of the groove 30 are oxidized. FIG. 7 shows the semiconductor material 10 after this oxidation step has been performed. By performing this oxidation step, an oxide film 34 is formed. The oxide film 34 is thicker than the oxide film 32 (see FIG. 6 and the like) formed by the above-described dry etching.
If the side surface 30a at the upper part of the groove is not rounded, the oxide film formed in that part becomes thin. In this case, when the finally completed semiconductor device is energized, the electric field tends to concentrate on the thin oxide film. On the other hand, in the present embodiment, since the side surface 30a at the upper part of the groove is rounded, the oxide film 34 formed in that portion can be made sufficiently thick. In a finally manufactured semiconductor device, the electric field is unlikely to concentrate on the upper part of the groove.

  Subsequently, as shown in FIG. 8, polysilicon 38 is deposited in the trench 30 in an impurity atmosphere. As a result, the conductor polysilicon 38 is formed in the groove 30. This polysilicon 38 functions as a trench gate electrode.

Next, as shown in FIG. 9, the oxide film 34 formed on the surface 10 a of the semiconductor material 10 and the polysilicon 38 deposited outside the trench 30 are removed. A so-called etch back process is performed. Thereby, the semiconductor substrate 50 in which the trench gate electrode 38 is formed in the groove 30 is completed.
The semiconductor substrate 50 is used for, for example, an IGBT or a MOS transistor. When the semiconductor substrate 50 is used for IGBT or the like, an insulating film is formed on the upper surface of the trench gate electrode 38, and then a main electrode (emitter electrode) is formed on the surface 10 a of the semiconductor material 10.

According to the above embodiment, it is possible to form roundness on the side surface 30a of the upper portion of the groove by dry etching. After the groove 30 is formed, there is no need to perform a step of forming a roundness on the side surface 30a of the upper part of the groove.
Further, in the above embodiment, since the gas not containing carbon is used, the side surface 30b at the lower part of the groove is not easily over-etched. For this reason, it can suppress that the whole side surface of the groove | channel 30 is over-etched. A groove 30 having an intended width can be formed.
Since the side surface 30a at the upper part of the groove is rounded, the oxide film 34 formed in that part is sufficiently thick. For this reason, it is possible to prevent the electric field from concentrating on a part of the oxide film 34 when the trench gate electrode 38 of the completed semiconductor device (for example, IGBT) is energized. According to this embodiment, a semiconductor device having stable electrical characteristics can be manufactured.

Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, in the above embodiment, silicon is used as the semiconductor material, but other semiconductor materials may be used. For example, gallium nitride, silicon carbide, gallium arsenide, or the like may be used for the semiconductor material.
Further, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of purposes at the same time, and has technical utility by achieving one of the purposes.

The manufacturing process of the semiconductor substrate in which the bottomed groove | channel is formed is shown. The manufacturing process of a semiconductor substrate is shown (continuation of FIG. 1). The manufacturing process of a semiconductor substrate is shown (continuation of FIG. 2). The manufacturing process of a semiconductor substrate is shown (continuation of FIG. 3). The manufacturing process of a semiconductor substrate is shown (continuation of FIG. 4). The manufacturing process of a semiconductor substrate is shown (continuation of FIG. 5). The manufacturing process of a semiconductor substrate is shown (continuation of FIG. 6). The manufacturing process of a semiconductor substrate is shown (continuation of FIG. 7). The manufacturing process of a semiconductor substrate is shown (continuation of FIG. 8). The figure for demonstrating the conventional manufacturing process is shown. The figure for demonstrating the conventional manufacturing process is shown.

Explanation of symbols

10: Semiconductor material 10a: Surface 10b of semiconductor material: Mask covering region 10c: Mask non-covering region 12: Insulator mask 14: Resist mask 20: Mask 30: Groove 30a: Side surface 30b of groove upper portion: Side surface 30c of lower portion of groove: Groove bottom surface 32: oxide film

Claims (6)

A method of manufacturing a semiconductor substrate having a bottomed groove,
A preparation step of preparing a semiconductor material having a mask covering region covered by a mask containing carbon and a mask non-covering region not covered by the mask;
A groove forming step of forming a bottomed groove extending from the non-mask covering region into the semiconductor material by supplying a gas not containing carbon toward both the mask and the non-mask covering region.   The manufacturing method according to claim 1, further comprising a step of forming a trench gate electrode in the groove.   3. The manufacturing method according to claim 1, wherein the semiconductor material is made of silicon. The mask is
A first mask in contact with the surface of the semiconductor material and having a predetermined mask pattern;
The manufacturing method according to claim 1, further comprising: a second mask that is in contact with a surface of the first mask, has the predetermined mask pattern, and contains carbon.   The manufacturing method according to claim 4, wherein the first mask is made of an insulator. The preparation step includes
Preparing a semiconductor material having an insulator region in contact with the surface;
Forming a second mask covering region covered by the second mask having the predetermined mask pattern and a second mask non-covering region not covered by the second mask on the surface of the insulator region; ,
Forming the first mask having the predetermined mask pattern by forming, in the insulator region, a hole extending from the second mask uncovered region of the insulator region to the surface of the semiconductor material. The manufacturing method of Claim 5 characterized by the above-mentioned.

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