JPH0123938B2 - - Google Patents

Info

Publication number
JPH0123938B2
JPH0123938B2 JP55024831A JP2483180A JPH0123938B2 JP H0123938 B2 JPH0123938 B2 JP H0123938B2 JP 55024831 A JP55024831 A JP 55024831A JP 2483180 A JP2483180 A JP 2483180A JP H0123938 B2 JPH0123938 B2 JP H0123938B2
Authority
JP
Japan
Prior art keywords
etching
silicon
oxide film
silicon substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55024831A
Other languages
Japanese (ja)
Other versions
JPS56122129A (en
Inventor
Yukinori Kuroki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP2483180A priority Critical patent/JPS56122129A/en
Publication of JPS56122129A publication Critical patent/JPS56122129A/en
Publication of JPH0123938B2 publication Critical patent/JPH0123938B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法、特に写真刻食
技術の一つであるドライエツチング技術を施すこ
とによつて露呈することとなる基板表面の処理方
法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for treating the surface of a substrate exposed by dry etching, which is one of photoetching techniques.

従来、集積回路等々の半導体装置を製造する工
程に於いて、シリコン酸化膜をエツチングするに
は弗化水素酸を主成分とする水溶液を、またシリ
コン窒化膜をエツチングするには150℃程度の熱
リン酸を使用する、等々のいわゆる湿式エツチン
グの手法がとられて来た。近年これらの方法にか
わつて、CF4とH2の混合ガス又はC3F8、CHF3
のフレオンガス等々のガスを使つて形成したプラ
ズマ中にてシリコン酸化膜やシリコン窒化膜をエ
ツチングする、いわゆるドライエツチング技術が
使用されるようになつた。この新しいドライエツ
チング技術は、レジストをマスクにして基板面に
垂直な方向にのみエツチングが進行し、横方向に
エツチングが進行しない、いわゆる異方性エツチ
ングの性質を示し、シリコン基板上にマスクとな
るレジスト寸法通りのシリコン酸化膜及びシリコ
ン窒化膜のパターンを高精度に形成できる利点を
有する。しかるに、この方法によりエツチングさ
れ、露出したシリコン基板表面を酸化して形成し
たシリコン酸化膜及び基板とシリコン界面の性質
は、金属(etal)−酸化膜(Silicon−xide)−
シリコン(ilicon)が積層されたいわゆるMOS
素子として使用する上では、絶縁破壊電圧が低
い、表面準位が多い等々の問題があり、実用に供
するには問題が多い。このため、シリコン酸化膜
のエツチングの場合、シリコン基板が露出するま
ではドライエツチングせず、ごく薄いシリコン酸
化膜を残してエツチングを終り、残りの薄いシリ
コン酸化膜を弗化水素を含む水溶液でエツチング
除去するという便法が用いられている。
Conventionally, in the process of manufacturing semiconductor devices such as integrated circuits, an aqueous solution containing hydrofluoric acid as the main component was used to etch a silicon oxide film, and heat of about 150°C was used to etch a silicon nitride film. So-called wet etching techniques, such as using phosphoric acid, have been used. In recent years, instead of these methods, so-called etching methods have been developed in which silicon oxide films and silicon nitride films are etched in plasma formed using a gas such as a mixed gas of CF 4 and H 2 or a Freon gas such as C 3 F 8 or CHF 3 . Dry etching techniques began to be used. This new dry etching technology exhibits so-called anisotropic etching properties, in which etching progresses only in the direction perpendicular to the substrate surface using the resist as a mask, and etching does not progress in the lateral direction. This method has the advantage that patterns of silicon oxide films and silicon nitride films can be formed with high accuracy according to resist dimensions. However, the properties of the silicon oxide film formed by oxidizing the surface of the silicon substrate etched and exposed by this method and the interface between the substrate and the silicon are metal ( M etal) - oxide film (Silicon - Oxide ) -
So-called MOS in which silicon is laminated
When used as an element, there are problems such as a low dielectric breakdown voltage and a large number of surface states, and there are many problems in putting it into practical use. For this reason, when etching a silicon oxide film, dry etching is not performed until the silicon substrate is exposed, the etching is finished leaving a very thin silicon oxide film, and the remaining thin silicon oxide film is etched with an aqueous solution containing hydrogen fluoride. The expedient method of removing is used.

本発明者等の研究によれば、これら弗化炭素系
のドライエツチング後のシリコン表面に、多量の
炭素及び弗素がオージエ電子分光法により観測さ
れた。またスパツタリング効果を取り入れ、弗化
炭素ガスによる反応性スパツタエツチングを行つ
たシリコン面の場合、いわゆるシリコン表面にと
どまらず、約30Åの深さにわたるシリコン基板中
にまで炭素及び弗素が分布していることが確かめ
られた。
According to research conducted by the present inventors, large amounts of carbon and fluorine were observed by Auger electron spectroscopy on the silicon surface after dry etching of these fluorocarbons. Furthermore, in the case of a silicon surface that has been subjected to reactive sputter etching using carbon fluoride gas by incorporating the sputtering effect, carbon and fluorine are distributed not only on the so-called silicon surface but also within the silicon substrate to a depth of about 30 Å. This was confirmed.

本発明者は、このため、エツチング後のシリコ
ン表面の損傷を受けた層を通常のシリコン基板な
ら、約100Åエツチング除去できる条件で、
HNO3−HF−CH3−COOHからなるエツチング
液で除去し、そのシリコン表面を酸化し、MOS
の電気的特性を評価した。そのゲート絶縁膜の絶
縁耐圧は、3〜6MV/cmであり、表面を上記エ
ツチング液でエツチングせず、そのまま酸化した
ものの絶縁耐圧6〜8MV/cmよりもむしろ悪く、
もちろん清浄なシリコン表面を酸化してできたシ
リコン酸化膜の絶縁破壊電圧9.5〜10.2MV/cmよ
りも極めて悪い結果を得、エツチング後のシリコ
ン基板表面層をどんな方法でも良いから単に除去
してしまえば良いというものではないことを確認
した。
For this reason, the inventor of the present invention has developed an etching method under which the damaged layer on the silicon surface after etching can be removed by etching approximately 100 Å on a normal silicon substrate.
It is removed with an etching solution consisting of HNO 3 −HF−CH 3 −COOH, and the silicon surface is oxidized to form a MOS
The electrical characteristics of the were evaluated. The dielectric strength voltage of the gate insulating film is 3 to 6 MV/cm, which is actually worse than the dielectric strength voltage of 6 to 8 MV/cm when the surface is oxidized without being etched with the above etching solution.
Of course, the result was much worse than the dielectric breakdown voltage of 9.5 to 10.2 MV/cm for a silicon oxide film formed by oxidizing a clean silicon surface, and the surface layer of the silicon substrate after etching was simply removed by any method. We confirmed that it is not just a matter of just doing it.

本発明の目的は、上述のドライエツチング後の
シリコン基板表面の損傷層を、エツチング後に適
当な表面処理を加えることにより取り除き、以後
の半導体集積回路製造工程と両立性のあるものと
し、また製作された素子の電気的性質を改善する
ことにある。
It is an object of the present invention to remove the damaged layer on the surface of the silicon substrate after dry etching by applying an appropriate surface treatment after etching, thereby making it compatible with the subsequent semiconductor integrated circuit manufacturing process, and making it easier to manufacture. The objective is to improve the electrical properties of the device.

本発明によれば、シリコン基板上のシリコン酸
化膜又はシリコン窒化膜をCF4+H2、CHF3
C2F6、C3F8、C4F8、CClF3+H2CCl4などの弗化
塩化炭素系ガスを用いた、平行平板型のプラズマ
エツチング、反応性スパツタエツチング、反応性
イオンシヤワーエツチング等のドライエツチング
技術により、シリコン基板が露呈するまでエツチ
ングし、その後少なくともCF4を最大10モル%含
んだ酸素プラズマガス中で表面処理を行うことを
特徴とする半導体装置の製造方法が得られる。
According to the present invention, a silicon oxide film or a silicon nitride film on a silicon substrate is coated with CF 4 +H 2 , CHF 3 ,
Parallel plate plasma etching, reactive sputter etching, reactive ion shower using carbon fluorochloride gas such as C 2 F 6 , C 3 F 8 , C 4 F 8 , CClF 3 +H 2 CCl 4 A method for manufacturing a semiconductor device is obtained, which comprises etching a silicon substrate until it is exposed by a dry etching technique such as etching, and then performing surface treatment in an oxygen plasma gas containing at least 10 mol% of CF 4 at most. .

酸素はシリコン表面を酸化する働きをし、CF4
は生成した酸化膜をエツチングしていく。本発明
ではCF4は最大でも10モル%しか含ませないので
エツチング速度は小さく、酸化の速度の方が大き
い。エツチング速度があまり大きいと基板が大き
く掘れてしまい表面の平坦性が失われ半導体集積
回路の製造工程に採用することはできない。しか
し次に示す実施例からもわかるようにエツチング
速度は小さいので好都合である。また上述のよう
にエツチングより酸化の方が速いので表面は常に
酸化膜で被われることになり表面保護の役割をは
たす。
Oxygen acts to oxidize the silicon surface, causing CF 4
etches the formed oxide film. In the present invention, the CF 4 content is only 10 mol % at most, so the etching rate is low and the oxidation rate is high. If the etching rate is too high, the substrate will be deeply etched and the surface will lose its flatness, making it impossible to use it in the manufacturing process of semiconductor integrated circuits. However, as can be seen from the following examples, the etching rate is low, which is advantageous. Furthermore, as mentioned above, since oxidation is faster than etching, the surface is always covered with an oxide film, which serves as surface protection.

次に実施例として、ドライエツチング後のシリ
コン表面処理にCF4を酸素に添加した場合につい
て述べる。
Next, as an example, a case will be described in which CF 4 is added to oxygen in silicon surface treatment after dry etching.

第1図に例示したデータは、微小な穴が数多く
あけられたアルミ製の筒で外部の放電領域から分
離された直径20cm、長さ30cmの円筒型のプラズマ
装置の内部にシリコン基板を置き、この装置に
CF4とO2混合ガスを導入し、0.3Torr、200Wの条
件で放電を起したときに、シリコン基板表面に形
成されたシリコン酸化膜厚のCF4の濃度依存性を
示す。
The data illustrated in Figure 1 shows that a silicon substrate is placed inside a cylindrical plasma device with a diameter of 20 cm and a length of 30 cm, which is separated from the external discharge area by an aluminum cylinder with many minute holes. to this device
This figure shows the dependence of the thickness of the silicon oxide film formed on the silicon substrate surface on the concentration of CF 4 when a mixed gas of CF 4 and O 2 is introduced and a discharge is generated under the conditions of 0.3 Torr and 200 W.

上述のように本発明の方法では表面が常に酸化
膜でおおわれエツチングガスがその酸化膜をエツ
チングしていく。第1図に示したのは表面を被う
酸化膜の厚さである。
As described above, in the method of the present invention, the surface is always covered with an oxide film, and the etching gas etches the oxide film. What is shown in FIG. 1 is the thickness of the oxide film covering the surface.

シリコン酸化膜厚は30〜56Åの範囲にあり、こ
れといつたCF4濃度依存性はみられない。CF4
O2への添加はシリコン酸化膜への影響より、シ
リコン基板、酸化膜、窒化膜のエツチング速度へ
の影響の方が大きい。
The silicon oxide film thickness is in the range of 30 to 56 Å, and no similar dependence on CF 4 concentration is observed. CF 4
Addition of O 2 has a greater effect on the etching rate of the silicon substrate, oxide film, and nitride film than on the silicon oxide film.

半導体集積回路の製造工程で表面処理を行うと
きには、その方法によつて表面に大きな凹凸が生
じてはならない。なぜならその凹凸によつてその
上に形成する電極や配線が断線する恐れが大きく
なるからである。また表面処理はふつう数十Åと
いうきわめてうすい層を対象としているため、あ
まり処理速度が大きいと制御性がなくなつてしま
う。本発明でいえばエツチング速度が小さいこと
が必要となるが次に示すように十分にエツチング
速度が小さいので半導体集積回路の製造に用いる
ことができる。
When surface treatment is performed in the manufacturing process of semiconductor integrated circuits, the method must not create large irregularities on the surface. This is because the unevenness increases the risk that the electrodes and wiring formed thereon will be disconnected. Furthermore, since surface treatment is usually aimed at extremely thin layers of several tens of angstroms, controllability will be lost if the processing speed is too high. Although the present invention requires a low etching rate, as shown below, the etching rate is sufficiently low so that it can be used for manufacturing semiconductor integrated circuits.

第2図に例示したデータは、シリコン基板(図
中1)、シリコン酸化膜(図中2)、シリコン窒化
膜(図中3)のエツチング速度のCF4の濃度依存
性を示したものである。エツチング速度は次のよ
うに測定した。一部をエツチングされないように
ガラス板でカバーしたシリコン基板、表面に
CVD法でシリコン酸化膜を形成したシリコン基
板、表面にCVD法でシリコン窒化膜を形成した
シリコン基板を用意する。各基板はそれぞれシリ
コン、シリコン酸化膜、シリコン窒化膜のエツチ
ング速度を測定するためのものである。次に本実
施例の処理を30分〜1時間施す。エツチング速度
が小さいのである程度長い時間処理し測定精度を
上げる。処理後のシリコン基板はガラス板でカバ
ーした部分とそうでない部分とに段差が生じるの
で、表面荒さ計で測定し処理時間で割ればエツチ
ング速度(Å/min)が求まる。なおエツチング
された表面は酸化膜で被われているが、第1図で
示したように厚さはきわめて薄いので処理時間を
長くすれば大きな誤差とはならない。シリコン酸
化膜とシリコン窒化膜は処理前後の膜厚をエリプ
ソメータで測定すればよい。CF4濃度10%までは
そのエツチング速度はCF4濃度にほぼ比例する。
10%以上のCF4添加はシリン基板表面が荒れ、シ
リコン基板表面の鏡面エツチングは不可能とな
る。
The data illustrated in Figure 2 shows the dependence of the etching rate of the silicon substrate (1 in the figure), the silicon oxide film (2 in the figure), and the silicon nitride film (3 in the figure) on the CF 4 concentration. . The etching rate was measured as follows. A silicon substrate whose surface is partially covered with a glass plate to prevent etching.
A silicon substrate with a silicon oxide film formed by the CVD method and a silicon substrate with a silicon nitride film formed on the surface by the CVD method are prepared. Each substrate is used to measure the etching rate of silicon, silicon oxide film, and silicon nitride film, respectively. Next, the treatment of this example is performed for 30 minutes to 1 hour. Since the etching speed is low, processing is performed for a certain amount of time to improve measurement accuracy. After processing, the silicon substrate has a difference in level between the part covered by the glass plate and the part not covered by the glass plate, so the etching rate (Å/min) can be determined by measuring it with a surface roughness meter and dividing it by the processing time. Note that although the etched surface is covered with an oxide film, the thickness is extremely thin as shown in FIG. 1, so if the processing time is lengthened, there will not be a large error. The thickness of the silicon oxide film and silicon nitride film before and after treatment may be measured using an ellipsometer. The etching rate is approximately proportional to the CF 4 concentration up to 10%.
If CF 4 is added in an amount of 10% or more, the silicon substrate surface becomes rough, and mirror etching of the silicon substrate surface becomes impossible.

表面が荒れるとそこに酸化膜を形成した場合絶
縁耐圧が低くなり集積回路として使うことができ
ない。表面が鏡面かどうかは、基板表面に光をあ
て目視で判断している。光をあてても基板上で光
束が見えなければ鏡面、見えれば鏡面でない。鏡
面でないと光のあたつた部分が白く見える。この
方法はシリコン基板メーカ等で行われている周知
の方法である。
If the surface becomes rough and an oxide film is formed there, the dielectric strength will be low and it cannot be used as an integrated circuit. Whether the surface is mirror-like or not is determined visually by shining a light onto the substrate surface. Even if you shine light on it, if you can't see the light flux on the substrate, it's a mirror surface, and if you can see it, it's not a mirror surface. If it's not a mirror surface, the parts that are hit by the light will look white. This method is a well-known method used by silicon substrate manufacturers and the like.

以上の実験は基板温度が60〜70℃の範囲で行わ
れた。
The above experiments were conducted at a substrate temperature in the range of 60 to 70°C.

代表的に3モル%のCF4添加の場合について示
せば、シリコン基板、シリコン酸化膜のエツチン
グ速度はそれぞれ6.5Å/min、10Å/minであつ
た。
As a representative example of the case where 3 mol % of CF 4 was added, the etching rates of the silicon substrate and the silicon oxide film were 6.5 Å/min and 10 Å/min, respectively.

この差はそれぞれの密度を勘案すれば、シリコ
ン基板が酸化されながら、その酸化膜がエツチン
グされていくということで説明できる。
This difference can be explained by the fact that the oxide film is etched while the silicon substrate is oxidized, taking into consideration the respective densities.

本実施例の場合、シリコン基板表面に成長した
酸化膜の膜厚は約40Åである。このことはシリコ
ン基板表面の20Åの深さまでが表面処理の極めて
初期の間にシリコン酸化膜に変化していると見る
ことができる。従つて、前記のオージエ電子分光
法により観測されたドライエツチング後のシリコ
ン表面の深さ30Åの損傷層は、シリコンのエツチ
ング速度が6.5Å/minであることと考え合わせ
ると、約2分間で消失することとなる。
In the case of this example, the thickness of the oxide film grown on the surface of the silicon substrate is approximately 40 Å. This indicates that the silicon substrate surface up to a depth of 20 Å is converted into a silicon oxide film during the very early stage of surface treatment. Therefore, considering that the etching rate of silicon is 6.5 Å/min, the damage layer of 30 Å deep on the silicon surface after dry etching observed by the above-mentioned Auger electron spectroscopy disappears in about 2 minutes. I will do it.

直径40cm、電極間隔10cmの平行平板型の反応性
スパツタエツチング装置にCF4;100SCCM、
H2;20SCCMのガスを導入し、10Paの圧力の下
で、13.56MHzの高周波放電を起こすという条件
の下で2分間エツチングしたシリコン基板表面上
に作成したMOSダイオードによるゲート絶縁膜
の絶縁耐圧は平均値が6.9MV/cm、標準偏差が
0.85MV/cmであつた。
CF 4 ; 100 SCCM in a parallel plate type reactive sputter etching device with a diameter of 40 cm and an electrode spacing of 10 cm.
The dielectric strength voltage of the gate insulating film of the MOS diode created on the silicon substrate surface was etched for 2 minutes under the conditions of introducing H 2 ; 20 SCCM gas and generating a high frequency discharge of 13.56 MHz under a pressure of 10 Pa. The average value is 6.9MV/cm, and the standard deviation is
It was 0.85MV/cm.

また上記反応性スパツタエツチング後に前記の
3モル%のCF4を添加したガスを用いた表面処理
を2分間行つたシリコン基板表面上に作成した
MOSダイオードでは、ゲート絶縁膜の破壊電圧
は10.5MV/cmで、その標準偏差は0.42MV/cm
であつた。なお特別の処理をしないシリコン基板
上ではそれぞれ9.5MV/cm、1.5MV/cmであつ
た。このことはエツチング後の表面処理を行うと
絶縁破壊電圧が向上するとともに偏差が少なく、
特性のそろつたものができ、無処理のものより良
い結果を得ることができることを示している。
In addition, after the above-mentioned reactive sputter etching, the surface treatment using the above-mentioned gas containing 3 mol% CF 4 was performed for 2 minutes on the silicon substrate surface.
In a MOS diode, the breakdown voltage of the gate insulating film is 10.5MV/cm, and its standard deviation is 0.42MV/cm.
It was hot. Furthermore, on a silicon substrate without any special treatment, the values were 9.5 MV/cm and 1.5 MV/cm, respectively. This means that surface treatment after etching improves the dielectric breakdown voltage and reduces deviation.
This shows that it is possible to produce products with uniform properties and to obtain better results than untreated products.

この実験過程で、ドライエツチングをしただけ
のものと、無処理及びドライエツチング後に本発
明の表面処理を行つたものを、同時に酸素中950
℃の温度で400Åをねらつて酸化したところ、無
処理のもの、及びドライエツチング後に本発明の
前記実施例の表面処理を行つたものでは、ねらい
通り400±5Åの膜厚が得られたが、ドライエツ
チングしただけのものでは、325±5Åの膜厚と
なり、ドライエツチング後のシリコン表面に炭素
等の不純物が存在するというオージエ電子分光法
による結果を裏づける結果を得た。
In this experimental process, we simultaneously exposed two specimens, one that had just been dry etched, one that had not been subjected to any treatment, and one that had been subjected to the surface treatment of the present invention after dry etching, in oxygen at 950°C.
When the film was oxidized to a thickness of 400 Å at a temperature of °C, a film thickness of 400 ± 5 Å was obtained as desired in the untreated film and in the surface treated film according to the above embodiment of the present invention after dry etching. The film thickness was 325±5 Å after dry etching alone, and the result supported the Auger electron spectroscopy finding that impurities such as carbon were present on the silicon surface after dry etching.

本発明の第1の特長は、実施例に示されている
如く、60〜70℃といつた低温で表面処理を行うこ
とが可能な点である。シリコン酸化膜及びシリコ
ン窒化膜の反応性スパツタエツチング中の基板温
度は、本発明の前記実施例と同じ条件では80〜90
℃まで上昇する。本発明の表面処理方法では、上
記の如く60〜70℃であるので、エツチング時より
も低温で表面処理が行われるわけである。従つて
例えば、不活性ガス中での高温アニールとは違つ
て、極く表面層にのみ限られていたドライエツチ
ングの損傷層から熱的に拡大、発生する欠陥がな
いという良い特長を持つ。
The first feature of the present invention is that surface treatment can be carried out at a low temperature of 60 to 70°C, as shown in the Examples. The substrate temperature during reactive sputter etching of silicon oxide and silicon nitride films was 80-90°C under the same conditions as in the above embodiments of the present invention.
The temperature rises to ℃. In the surface treatment method of the present invention, the temperature is 60 to 70°C as described above, so the surface treatment is performed at a lower temperature than that during etching. Therefore, unlike high-temperature annealing in an inert gas, for example, it has the advantage that there are no defects that are thermally expanded and generated from the damaged layer caused by dry etching, which was limited only to the surface layer.

本発明の第2の特長は、実施例に示した如く、
処理が乾燥した状態で、しかも2分程度といつた
短時間で完了するということである。
The second feature of the present invention is, as shown in the examples,
This means that the process can be completed in a dry state and in a short time of about 2 minutes.

本発明の第3の特長は、処理雰囲気中にF、Cl
といつた半導体装置の製造において問題となる
Na、Ka、Li等のアルカリ金属との間で安定でし
かもその後の水洗工程で容易に溶解する塩を作る
ハロゲン元素を含んでいることである。従つて、
本発明を実施するときはアルカリ金属汚染を気に
することなく、容易に場所を選ばず行うことが可
能である。但し、過度の弗化塩化炭素系ガスの添
加はシリコン表面を荒らすので、このため表面上
に形成される絶縁膜の絶縁耐圧を下げるのみでな
く、二次的な欠陥の発生を誘引する。従つて、多
くとも10モル%程度に限定することが望ましい。
The third feature of the present invention is that F, Cl, and
This is a problem in the manufacture of semiconductor devices such as
It contains a halogen element that forms a salt that is stable with alkali metals such as Na, Ka, Li, etc. and easily dissolves in the subsequent water washing process. Therefore,
The present invention can be carried out easily anywhere without worrying about alkali metal contamination. However, excessive addition of fluorochloride-based gas roughens the silicon surface, which not only lowers the dielectric strength voltage of the insulating film formed on the surface but also induces the generation of secondary defects. Therefore, it is desirable to limit the amount to about 10 mol% at most.

本発明の第4の特長は、半導体集積回路で使用
されるシリコン酸化膜及びシリコン窒化膜のエツ
チング速度が10〜50Å程度以下の条件を容易に選
べるのでそれまでの写真刻食技術により得られた
パターン形状に実質上まつたくといつて良い程変
化を与えないことである。
The fourth feature of the present invention is that the etching rate of silicon oxide films and silicon nitride films used in semiconductor integrated circuits can be easily selected to be less than about 10 to 50 Å, which is faster than that obtained by conventional photoetching techniques. The purpose is to not substantially change the pattern shape to the extent that it can be described as blinking.

なお前記実施例では円筒形プラズマ装置を用い
たが、本発明の表面処理はプラズマ中に発生する
反応活性種の化学反応によるものなので、同種の
反応活性種を発生するものであれば円筒形以外の
プラズマ装置であつても同様の効果を得ることが
できる。
Although a cylindrical plasma device was used in the above embodiment, since the surface treatment of the present invention is based on a chemical reaction of reactive active species generated in plasma, a plasma device other than a cylindrical shape may be used as long as it generates the same type of reactive active species. A similar effect can be obtained even with a plasma device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例についてシリコン基
板上に形成されるシリコン酸化膜のCF4濃度依存
性の一例を示したものである。第2図は同じく本
発明の一実施例におけるシリコン基板(図中1)、
シリコン酸化膜(図中2)、シリコン窒化膜(図
中3)のエツチング速度のCF4濃度依存性の一例
を示したものである。
FIG. 1 shows an example of the CF 4 concentration dependence of a silicon oxide film formed on a silicon substrate in one embodiment of the present invention. FIG. 2 also shows a silicon substrate (1 in the figure) in an embodiment of the present invention;
This figure shows an example of the CF 4 concentration dependence of the etching rate of a silicon oxide film (2 in the figure) and a silicon nitride film (3 in the figure).

Claims (1)

【特許請求の範囲】[Claims] 1 シリコン基板上のシリコン窒化膜又はシリコ
ン酸化膜を少なくとも炭素を含みしかも弗素また
は塩素のいずれかを含むエツチングガスにてドラ
イエツチングする工程に引き続き、露出したシリ
コン基板表面を最大10モル%までのCF4を含んだ
酸素ガスプラズマ中で低温で表面処理する工程を
備えていることを特徴とする半導体装置の製造方
法。
1. Following the step of dry etching a silicon nitride film or silicon oxide film on a silicon substrate with an etching gas containing at least carbon and either fluorine or chlorine, the exposed silicon substrate surface is etched with CF of up to 10 mol%. 4. A method for manufacturing a semiconductor device, comprising a step of surface treatment at low temperature in oxygen gas plasma containing 4 .
JP2483180A 1980-02-28 1980-02-28 Manufacture of semiconductor device Granted JPS56122129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2483180A JPS56122129A (en) 1980-02-28 1980-02-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2483180A JPS56122129A (en) 1980-02-28 1980-02-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS56122129A JPS56122129A (en) 1981-09-25
JPH0123938B2 true JPH0123938B2 (en) 1989-05-09

Family

ID=12149135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2483180A Granted JPS56122129A (en) 1980-02-28 1980-02-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56122129A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021052039A (en) * 2019-09-24 2021-04-01 東京エレクトロン株式会社 Etching method, method for removing damaged layer, and storage medium

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JPS57114235A (en) * 1981-01-08 1982-07-16 Toshiba Corp Cleaning of semiconductor substrate
JPS5893235A (en) * 1981-11-30 1983-06-02 Toshiba Corp Preparation of semiconductor device
US4418094A (en) * 1982-03-02 1983-11-29 Texas Instruments Incorporated Vertical-etch direct moat isolation process
JPH0722148B2 (en) * 1983-03-07 1995-03-08 株式会社日立製作所 Anisotropic etching control method
JPS6098626A (en) * 1983-11-02 1985-06-01 Oki Electric Ind Co Ltd Surface treating method of semiconductor layer
JPS6197824A (en) * 1984-10-18 1986-05-16 Sanyo Electric Co Ltd Formation of contact hole of semiconductor device
JPH0646630B2 (en) * 1985-06-07 1994-06-15 株式会社日立製作所 Plasma processing method
EP0424299A3 (en) * 1989-10-20 1991-08-28 International Business Machines Corporation Selective silicon nitride plasma etching
JP2580373B2 (en) * 1990-08-10 1997-02-12 大日本スクリーン製造株式会社 Substrate surface treatment method
JP2573108B2 (en) * 1991-06-14 1997-01-22 株式会社 半導体エネルギー研究所 Plasma processing method
JP3019002B2 (en) * 1996-09-20 2000-03-13 日本電気株式会社 Dry etching apparatus and dry etching method
US6551924B1 (en) * 1999-11-02 2003-04-22 International Business Machines Corporation Post metalization chem-mech polishing dielectric etch
JP7390134B2 (en) * 2019-08-28 2023-12-01 東京エレクトロン株式会社 Etching processing method and etching processing equipment

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JPS54124683A (en) * 1978-03-20 1979-09-27 Nippon Telegr & Teleph Corp <Ntt> Processing method of silicon wafer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54124683A (en) * 1978-03-20 1979-09-27 Nippon Telegr & Teleph Corp <Ntt> Processing method of silicon wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021052039A (en) * 2019-09-24 2021-04-01 東京エレクトロン株式会社 Etching method, method for removing damaged layer, and storage medium

Also Published As

Publication number Publication date
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