CN117976520A - Silicon nitride cleaning method and semiconductor device - Google Patents
Silicon nitride cleaning method and semiconductor device Download PDFInfo
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- CN117976520A CN117976520A CN202410339420.6A CN202410339420A CN117976520A CN 117976520 A CN117976520 A CN 117976520A CN 202410339420 A CN202410339420 A CN 202410339420A CN 117976520 A CN117976520 A CN 117976520A
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- 238000004140 cleaning Methods 0.000 title claims abstract description 150
- 229910052581 Si3N4 Inorganic materials 0.000 title claims abstract description 123
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims abstract description 123
- 238000000034 method Methods 0.000 title claims abstract description 81
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000005530 etching Methods 0.000 claims abstract description 98
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 144
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 96
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 72
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 56
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 56
- 238000000137 annealing Methods 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 9
- 238000011010 flushing procedure Methods 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 abstract description 4
- 239000002253 acid Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000011049 filling Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The application provides a silicon nitride cleaning method and a semiconductor device, relates to the technical field of semiconductor preparation, and solves the problems that the etching difficulty of a silicon nitride layer is increased and the step height is difficult to control in the etching process in the related technology.
Description
Technical Field
The application relates to the technical field of semiconductor preparation, in particular to a silicon nitride cleaning method and a semiconductor device.
Background
In a 55nm Process, for trench filling of STI (Shallow Trench Isolation ), high aspect Ratio HARP (HIGH ASPECT Ratio Process), silicon oxide is used as a filling material. The silicon oxide is annealed in a high-temperature process to densify the silicon oxide and improve the moisture resistance of the silicon oxide, and the silicon nitride simultaneously generates corresponding physical and chemical changes in the process, so that a corresponding film structure is formed on the surface of the silicon nitride, the etching difficulty of the silicon nitride after the high-temperature process is increased, and the required cleaning time is prolonged.
On the other hand, the STI process generally requires removal of the silicon nitride layer by wet etching (e.g., by high temperature phosphoric acid, etc.), and a step height is formed between the silicon oxide layer and the silicon substrate after removal of the silicon nitride layer. The etching difficulty of the silicon nitride layer after high-temperature processing is increased, and the increase of the phosphoric acid consumption can also affect the silicon oxide layer, so that the step height is difficult to control, and the structure and the performance of the device are further affected.
Disclosure of Invention
The application provides a silicon nitride cleaning method and a semiconductor device, which solve the problems that the etching difficulty of a silicon nitride layer is increased and the step height is difficult to control in the etching process in the related technology.
In a first aspect, the present application provides a method for cleaning silicon nitride, the method comprising:
after high-temperature annealing treatment of the STI process, cleaning the silicon nitride layer of the semiconductor device subjected to the high-temperature annealing treatment for the first time by using a hydrofluoric acid solution based on a wet etching process;
stopping the first cleaning and flushing the semiconductor device to remove the hydrofluoric acid solution under the condition that the time length of the first cleaning of the silicon nitride layer reaches the first cleaning time length;
Based on the wet etching process, cleaning the silicon nitride layer for the second time by using a phosphoric acid solution;
in the case where the second cleaning time period of the silicon nitride layer reaches the second cleaning time period, the second cleaning is stopped and the semiconductor device is rinsed to remove the phosphoric acid solution.
In a second aspect, the present application also provides a semiconductor device fabricated using the silicon nitride cleaning method described above.
According to the scheme, in the process of cleaning the silicon nitride, the cleaning time of etching by using the hydrofluoric acid solution and the phosphoric acid solution can be controlled, so that the cleaning of the silicon nitride layer is completed, meanwhile, based on the control of the cleaning time, the excessive etching of the silicon oxide layer by using the solution can be avoided, the thickness of the silicon oxide layer is further controlled, the step height of the semiconductor device is controlled, and the manufactured semiconductor device has better device structure and performance.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor device during an STI process provided in the related art;
FIG. 2 is a graph of etch rate for cleaning silicon nitride using phosphoric acid as provided in the related art;
FIG. 3 is a schematic diagram illustrating a method for cleaning silicon nitride according to an embodiment of the present application;
FIG. 4 is a graph showing the etching rate of silicon nitride by phosphoric acid solution after cleaning with hydrofluoric acid solution;
FIG. 5 is a graph showing the relationship between the cleaning time of the phosphoric acid solution and the loss of the silicon nitride layer according to one embodiment of the present application;
FIG. 6 is a graph illustrating the etching rate of phosphoric acid to silicon oxide according to one embodiment of the present application;
Fig. 7 is a schematic cross-sectional view of a semiconductor device after cleaning according to an embodiment of the present application.
Reference numerals:
A silicon substrate layer 110, a silicon nitride layer 120, a silicon oxide layer 130.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the drawings and examples. It should be understood that the particular embodiments described herein are illustrative only and are not limiting of embodiments of the application. It should be further noted that, for convenience of description, only some, but not all structures related to the embodiments of the present application are shown in the drawings, and those skilled in the art will appreciate that any combination of technical features may constitute alternative embodiments as long as the technical features are not contradictory to each other after reading the present specification.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship. In the description of the present application, "a plurality" means two or more, and "a number" means one or more.
In the STI process filled trench, silicon oxide is generally used as a filling material, as shown in fig. 1, fig. 1 is a schematic cross-sectional view of a semiconductor device during the STI process provided in the related art, and corresponding trenches are etched in the silicon substrate layer 110 and the silicon nitride layer 120 during the shallow trench preparation of the semiconductor device, so that oxides such as silicon oxide are filled as a filling material in the trenches, thereby forming a filled silicon oxide layer 130. In order to densify the silicon oxide layer, the silicon oxide layer is usually subjected to high-temperature annealing through a high-temperature process in the process, so that the moisture resistance of the silicon oxide layer is improved while the silicon oxide layer is densified.
However, in the high temperature process, the silicon nitride layer as the hard grinding layer will generate corresponding physical and chemical changes, so that a corresponding film structure is formed on the surface of the silicon nitride layer, and the subsequent etching difficulty of the silicon nitride is increased, and the cleaning time required for cleaning the silicon nitride is longer. As shown in fig. 2, fig. 2 is a graph showing an etch rate curve (i.e., curve Y (SiN)) for silicon nitride not subjected to a high temperature process and an etch rate curve (i.e., curve Y (sin+ann)) for silicon nitride subjected to a high temperature process, in which the etch rate of phosphoric acid for silicon nitride not subjected to a high temperature process may be stabilized at 52.5A/min (where a is an Angstrom, a length unit commonly used in the semiconductor field), but the etch rate of phosphoric acid for silicon nitride is significantly changed after the high temperature process. As shown, a time of 20min is theoretically required for cleaning 1000A of silicon nitride that has not undergone a high temperature process, but a time of 50min is required for cleaning 1000A of silicon nitride that has undergone a high temperature process.
Since a step height is formed between the silicon oxide layer and the silicon substrate after the silicon nitride is removed, the poor control of the step height directly affects the device and affects the stability of the patterning and subsequent processes. In addition, in the process of removing silicon nitride by adopting phosphoric acid, the phosphoric acid has a certain etching rate on a silicon oxide layer (STI-Harp) in the process of removing the silicon nitride, so that the height of a step can be influenced in the process of removing the silicon nitride, and the structure and the performance of the prepared semiconductor device are influenced.
Therefore, the present application provides a silicon nitride cleaning method, after performing high temperature annealing treatment on a semiconductor device in an STI process, when cleaning a silicon nitride layer thereon, a hydrofluoric acid solution and a phosphoric acid solution are required to be used for cleaning for a corresponding period of time, as shown in fig. 3, fig. 3 is a schematic step diagram of the silicon nitride cleaning method according to an embodiment of the present application, and in the cleaning process of the semiconductor device, the cleaning period of time of the solution used is required to be controlled to control the thickness of a silicon oxide layer of the device, which specifically includes the following steps:
Step S110, after the high-temperature annealing treatment of the STI process, the silicon nitride layer on the semiconductor device after the high-temperature annealing treatment is cleaned for the first time by using hydrofluoric acid solution based on the wet etching process.
Step S120, stopping the first cleaning and rinsing the semiconductor device to remove the hydrofluoric acid solution when the duration of the first cleaning of the silicon nitride layer reaches the first cleaning duration.
Step S130, cleaning the silicon nitride layer for the second time by using a phosphoric acid solution based on a wet etching process.
And step 140, stopping the second etching and flushing the semiconductor device to remove the phosphoric acid solution when the second cleaning time of the silicon nitride layer reaches the second cleaning time.
After the high temperature process, the silicon oxide layer of the semiconductor device is densified, and the silicon nitride layer of the semiconductor device is changed due to the high temperature process, so that a film layer structure is formed on the surface of the silicon nitride layer. The silicon nitride layer is cleaned by directly adopting phosphoric acid solution in the process, and the corresponding etching rate is shown in figure 2. After cleaning with hydrofluoric acid solution for different time periods, the etching rate of silicon nitride can be changed along with the change of the cleaning time period of the prior hydrofluoric acid solution when the phosphoric acid solution is used for secondary cleaning, the specific change is shown in fig. 4, and fig. 4 is a graph of the etching rate of the phosphoric acid solution to the silicon nitride after the cleaning with the hydrofluoric acid solution. In fig. 4, in the case where the duration of using the hydrofluoric acid solution is short, the phosphoric acid solution is used to clean the silicon nitride layer, and the corresponding etching rate is low; after a period of time (e.g., at least 104 seconds) of cleaning with the hydrofluoric acid solution, the phosphoric acid solution is used to clean, and it can be seen that the graph of FIG. 4 shows the etch rate as smooth.
Fig. 5 is a graph showing a relationship between a cleaning time period of a phosphoric acid solution and a loss amount of a silicon nitride layer according to an embodiment of the present application, wherein an x-axis represents the cleaning time period using the phosphoric acid solution, a y-axis represents the loss amount of the silicon nitride layer, a curve I (y=52.5x, r 2 =1) represents the loss amount of the silicon nitride layer which has not undergone a high temperature process, and a curve II (y=49 x-392, r 2 =1) represents the loss amount of the silicon nitride layer which has undergone a high temperature process. As shown, for the silicon nitride layer that has not undergone the high temperature process, the loss amount is proportional to the cleaning time period using the phosphoric acid solution; for the silicon nitride layer subjected to the high-temperature process, after the cleaning time of using the phosphoric acid solution reaches 9min, the loss amount of the silicon nitride layer is directly proportional to the cleaning time of using the phosphoric acid solution, for example, when the cleaning time of using the phosphoric acid solution reaches 9min, the loss amount of the silicon nitride layer is 40A.
It will be appreciated that the film structure formed on the surface of the silicon nitride layer affects the etching rate of the silicon nitride by phosphoric acid, and that when the etching rate of the silicon nitride by cleaning with the phosphoric acid solution is stabilized, i.e., the loss amount of the silicon nitride layer is proportional to the cleaning time by using the phosphoric acid solution, it is indicated that the film structure has been completely etched, and thus, as can be seen from fig. 5, the thickness of the film structure formed on the surface of the silicon nitride layer is 40A. Therefore, the silicon nitride layer after the high-temperature annealing treatment is cleaned for the first time by adopting the hydrofluoric acid solution preferentially, and meanwhile, the cleaning time length by using the hydrofluoric acid solution is controlled, namely, the first cleaning time length is set.
It is conceivable that the silicon oxide layer is also etched when using a hydrofluoric acid solution. Thus, in some embodiments, it may be desirable to incorporate the etching effect of the hydrofluoric acid solution on the silicon oxide layer on the semiconductor device for the determination of the first cleaning duration. And the first cleaning time corresponding to the use of the hydrofluoric acid solution can be determined according to the first etching rate of the hydrofluoric acid solution on the silicon oxide layer on the semiconductor device, the target etching amount corresponding to the silicon oxide layer, the second etching rate of the phosphoric acid solution on the silicon oxide layer and the second cleaning time.
It will be appreciated that in order to control the thickness of the silicon oxide layer in the semiconductor device, the entire cleaning process needs to control the cleaning time periods corresponding to the hydrofluoric acid solution and the phosphoric acid solution, that is, the cleaning time period of the first cleaning time period is performed by using the hydrofluoric acid solution and the cleaning time period of the second cleaning time period is performed by using the phosphoric acid solution, and the thickness of the silicon oxide layer in the semiconductor device can meet the requirement of the step height. In this regard, in the calculation corresponding to the first cleaning period, a second etching rate of the silicon oxide layer by the phosphoric acid solution and the second cleaning period are also required to be combined.
Specifically, in an embodiment, a product of the second etching rate and the second cleaning duration is determined, and the product is taken as a first etching amount; in the case that the silicon oxide layer is determined corresponding to the target etching amount, the difference between the target etching amount and the first etching amount is taken as the second etching amount, and it is conceivable that the second etching amount is a product value of the first etching rate and the first cleaning duration of the silicon oxide layer on the semiconductor device by the hydrofluoric acid solution, so that the specific value of the first cleaning duration can be determined by dividing the second etching amount by the first etching rate. The corresponding calculation formula is as follows:
Wherein, T (HF) is the first cleaning time period, thk (loss) is the target etching amount, T (H 3PO4) is the second cleaning time period, Y 3 is the first etching rate, and Y is the second etching rate.
Further, the cleaning time of the semiconductor device by the hydrofluoric acid solution may be determined based on the first cleaning time period to clean the film layer on the silicon nitride layer, thereby enabling the silicon nitride layer to be cleaned more quickly when the phosphoric acid solution is subsequently used. When the first cleaning period reaches the first cleaning period, the first cleaning is stopped, and the semiconductor device is rinsed to remove the hydrofluoric acid solution remaining thereon.
In addition, the remaining silicon nitride layer needs to be cleaned, namely, the semiconductor device is cleaned for the second time, and in the process of the second cleaning, the phosphoric acid solution is adopted to clean the silicon nitride layer of the semiconductor device for the second time, and the cleaning time length needs to reach the second cleaning time length.
When the silicon nitride layer is cleaned by the phosphoric acid solution, the corresponding etching rate is lower when the film structure exists in the silicon nitride layer, and for this purpose, after the cleaning with the hydrofluoric acid solution for a first cleaning time, the second cleaning is performed by the phosphoric acid solution, so that the corresponding etching rate is greatly improved. In some embodiments, for the second cleaning period, it is required to determine according to the thickness of the silicon nitride layer, the film thickness, the third etching rate of the silicon nitride layer by the phosphoric acid solution after using the hydrofluoric acid solution, the fourth etching rate of the silicon nitride layer by the phosphoric acid solution when stably etching, and the excess coefficient, that is, the second cleaning period is related to the thickness of the structure and the excess coefficient in addition to the corresponding etching rate, wherein the excess coefficient is the coefficient corresponding to the excess etching of phosphoric acid.
Specifically, in one embodiment, the film thickness may be determined to have a value of 40A according to the loss amount of silicon nitride shown in fig. 5, and the thickness of the silicon nitride layer may be obtained by measurement after the high temperature annealing treatment is completed. Likewise, a fourth etching rate at which the phosphoric acid solution stably etches the silicon nitride layer can be determined according to fig. 4, which has a value of 49.5A/min.
Further, the thickness of the film layer is divided by the third etching rate to determine a first duration, and a difference between the thickness of the silicon nitride layer and the thickness of the film layer is calculated to determine a remaining thickness, such that the remaining thickness is divided by the fourth etching rate and multiplied by an excess factor to determine a second duration, and the second cleaning duration is a sum of the first duration and the second duration, respectively. The corresponding calculation formula is as follows:
Wherein, T (H 3PO4) is the second cleaning time, Y 0 is the film thickness, thk (SiN) is the thickness of the silicon nitride layer, Y 1 is the third etching rate, Y 2 is the fourth etching rate, and n is the excess coefficient.
After the second cleaning time period is determined, the second cleaning of the silicon nitride layer by the phosphoric acid solution is performed according to the second cleaning time period, and when the cleaning time reaches the second cleaning time period, the second cleaning is stopped, and the semiconductor device is rinsed to remove the residual phosphoric acid solution on the device.
It can be understood that although the silicon nitride on the semiconductor device changes after the high temperature process to increase the etching difficulty, as shown in fig. 4, after the cleaning with the hydrofluoric acid solution, the etching rate gradually becomes stable along with the increase of the use time of the hydrofluoric acid solution, i.e. the etching difficulty can be reduced. In order to control the thickness of the silicon oxide layer to have the effect of controlling the step height while cleaning the silicon nitride, the solution is set to a first cleaning time period by using a hydrofluoric acid solution and a second cleaning time period by using a phosphoric acid solution.
According to the scheme, in the process of cleaning the silicon nitride, the cleaning time of etching is controlled by using the hydrofluoric acid solution and the phosphoric acid solution, so that the silicon nitride layer is cleaned, meanwhile, based on the control of the cleaning time, excessive etching of the silicon oxide layer by using the solution can be avoided, the thickness of the silicon oxide layer is further controlled, the step height of the semiconductor device is controlled, and the manufactured semiconductor device has better device structure and performance.
In one embodiment, the second etch rate is associated with a used time period of the phosphoric acid solution, where the used time period of the phosphoric acid solution is determined in combination with a number of wafers (wafer) to be cleaned in the phosphoric acid solution and a cleaned time period, e.g., the number of wafers cleaned with the phosphoric acid solution in the first lot is 4 and the cleaned time period is 20 minutes, and correspondingly, the used time period is 80 minutes for the next lot. Further, for the third lot, its corresponding used time length needs to be determined in combination with the time of the first two lots. In the case of a used time length determination, the second etch rate can also be determined based on the following formula, which is specifically calculated as follows:
wherein X 0 is the used time period.
The phosphoric acid solution has a certain etching rate on silicon oxide, but along with the change of the old acid and the new acid (such as the situation that the new acid is used for replacing the old acid and the new acid is used for a long time), the corresponding etching rate also has a certain fluctuation, as shown in fig. 6, fig. 6 is a schematic diagram of the etching rate of the phosphoric acid on the silicon oxide, along with the increase of the used time, the new acid is changed into the old acid, the corresponding etching rate is continuously reduced, and the formula is fitted with the curve corresponding to the etching rate, and the fitting degree is 0.9983. Thus, in determining the first cleaning duration, the second etch rate needs to be determined in combination with the used duration of the phosphoric acid solution in order to better control the thickness of the silicon oxide layer.
In an embodiment, the third etching rate is the etching rate of the phosphoric acid solution to the silicon nitride layer after using the hydrofluoric acid solution, as shown in fig. 4, as the time of using the hydrofluoric acid solution is prolonged, the etching rate of the phosphoric acid solution to the silicon nitride layer is continuously increased, and then after the time of using the hydrofluoric acid solution reaches a corresponding time length, the etching rate is stable. Thus, the third etching rate is related to the first cleaning period, i.e., the period of time during which the cleaning is performed using the hydrofluoric acid solution, and the specific formula is as follows:
Wherein T (HF) is the first cleaning duration.
The formula is fitted with the curve shown in fig. 4, and the etching rate of the phosphoric acid solution to the silicon nitride after the hydrofluoric acid solution is cleaned for the first cleaning time is calculated through the formula, so that the cleaning time of the phosphoric acid solution can be better controlled, the silicon nitride layer can be better removed, the thickness of the silicon oxide layer can be simultaneously controlled, and the semiconductor device has better device structure and performance.
In some embodiments, the excess factor is associated with a target etch rate of a silicon oxide layer on the semiconductor device and has a value in the range of [1.2,1.6], i.e., the excess factor has a value greater than or equal to 1.2 and less than or equal to 1.6, and is adjustable according to the target etch rate, e.g., to a value corresponding to a corresponding etch rate threshold when the target etch rate is greater than the threshold.
Illustratively, after the semiconductor device is subjected to 1050 ℃ high-temperature annealing treatment, the silicon oxide layer on the semiconductor device is densified, and the silicon nitride layer on the semiconductor device is also changed to generate a corresponding film structure. The average thickness of the silicon oxide layer was 3650A, and the thickness Thk (SiN) of the silicon nitride layer was 1100A, as determined by measurement. In addition, the etching rate of the hydrofluoric acid solution to the silicon oxide layer, namely the first etching rate Y 3, is a fixed value, and the value is 35A/min. And the corresponding excess factor n takes a value of 1.3.
When the current used duration X 0 of the phosphoric acid solution is 1250min, the second etching rate Y can be correspondingly determined to be 1.42A/min according to the calculation formula of the second etching rate Y. Further, based on the graph shown in FIG. 4, it was determined that the fourth etching rate Y 2 at the time of stable etching of the silicon nitride layer by the phosphoric acid solution was 49.5A/min. When the target thickness of the silicon oxide layer in the process is 3550A, that is, the target etching amount Thk (loss) of the silicon oxide layer is 100A.
Further, as can be seen from the above formula, the first cleaning duration T (HF) is:
the second cleaning time period T (H 3PO4) is:
The third etching rate Y 1 is:
Therefore, the corresponding equation and the above values (such as the above target etching amount Thk (loss), the first etching rate Y 3, the second etching rate Y, the fourth etching rate Y 2, the silicon nitride layer thickness Thk (SiN), the excess coefficient n, and the film layer thickness Y 0) are substituted into the calculation equation of the first cleaning duration T (HF), so that the following equation can be obtained:
And
Correspondingly, the first cleaning time period T (HF) may be calculated to be about 1.70min (two bits after the decimal point), and the second cleaning time period T (H 3PO4) may be calculated to be about 28.68min (two bits after the decimal point). Therefore, after the first cleaning period T (HF) is determined, the semiconductor device is first cleaned with a hydrofluoric acid solution for the first cleaning period T (HF), and the semiconductor device is rinsed after the first cleaning is finished to remove the residual hydrofluoric acid solution. And further, in the second cleaning process, the semiconductor device is cleaned according to the second cleaning time length T (H 3PO4), and of course, the semiconductor device is also rinsed after the second cleaning is finished so as to remove the residual phosphoric acid solution, so that the silicon oxide layer can be etched by the target etching amount while the cleaning of the silicon nitride layer is finished.
Fig. 7 is a schematic cross-sectional view of a semiconductor device after cleaning according to an embodiment of the present application, where the silicon nitride layer 120 on the semiconductor device is removed after the cleaning according to the above steps, only the silicon substrate layer 110 and the silicon oxide layer 130 remain, and the thickness of the silicon oxide layer 130 can be controlled while the silicon nitride layer 120 is cleaned, so as to control the step height of the device. Fig. 7 and 1 are exemplary representations of semiconductor devices, and are not intended to limit parameters such as thickness, proportion, etc. of the device structures shown in fig. 7 and 1.
It is conceivable that the front surface and the back surface of the semiconductor device are both provided with silicon nitride layers, that is, the silicon nitride layers are provided on both surfaces of the silicon substrate, and the thicknesses of the two silicon nitride layers are equal.
According to the scheme, the cleaning time of etching by using the hydrofluoric acid solution and the phosphoric acid solution is controlled, so that the silicon nitride layer can be cleaned, and the thickness of the silicon oxide layer can be controlled, so that the step height of the semiconductor device is controlled, and the manufactured semiconductor device has better device structure and performance.
The application also provides a semiconductor device, wherein the silicon nitride cleaning method is applied in the preparation process of the semiconductor device so as to remove the silicon nitride layer on the semiconductor device, and the thickness of the silicon oxide layer can be effectively controlled in the process of cleaning the silicon nitride layer, so that the requirement of a target etching amount is met, the step height of the semiconductor device can be controlled, and the semiconductor device manufactured by the method has better device structure and performance.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Note that the above is only a preferred embodiment of the present application and the technical principle applied. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, while the application has been described in connection with the above embodiments, the application is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the application, which is set forth in the following claims.
Claims (9)
1. A method of cleaning silicon nitride, comprising:
after high-temperature annealing treatment of the STI process, cleaning the silicon nitride layer of the semiconductor device subjected to the high-temperature annealing treatment for the first time by using a hydrofluoric acid solution based on a wet etching process;
Stopping the first cleaning and flushing the semiconductor device to remove the hydrofluoric acid solution under the condition that the time length of the first cleaning of the silicon nitride layer reaches the first cleaning time length;
Based on a wet etching process, cleaning the silicon nitride layer for the second time by using a phosphoric acid solution;
Stopping the second etching and flushing the semiconductor device to remove the phosphoric acid solution under the condition that the second cleaning time of the silicon nitride layer reaches the second cleaning time;
After the high-temperature annealing treatment of the STI process, the first cleaning of the silicon nitride layer on the semiconductor device, which is subjected to the high-temperature annealing treatment, with a hydrofluoric acid solution based on a wet etching process includes:
Determining a first cleaning duration corresponding to the use of the hydrofluoric acid solution according to a first etching rate of the hydrofluoric acid solution on a silicon oxide layer on the semiconductor device, a target etching amount corresponding to the silicon oxide layer, a second etching rate of the phosphoric acid solution on the silicon oxide layer and the second cleaning duration;
And performing first cleaning on the semiconductor device by using the hydrofluoric acid solution based on the first cleaning duration.
2. The method of claim 1, wherein determining the first cleaning duration corresponding to the use of the hydrofluoric acid solution based on a first etching rate of the hydrofluoric acid solution to a silicon oxide layer on the semiconductor device, a target etching amount corresponding to the silicon oxide layer, a second etching rate of the phosphoric acid solution to the silicon oxide layer, and the second cleaning duration comprises:
Wherein T (HF) is the first cleaning duration, thk (loss) is the target etching amount, T (H 3PO4) is the second cleaning duration, Y 3 is the first etching rate, and Y is the second etching rate.
3. The method of claim 1 or 2, wherein the second etch rate is related to a used time of the phosphoric acid solution, the second etch rate being:
wherein X 0 is the used time period.
4. The method of claim 1, wherein the second cleaning of the silicon nitride layer with a phosphoric acid solution based on a wet etching process comprises:
Determining the second cleaning duration according to the thickness of the silicon nitride layer, the film thickness, the third etching rate of the phosphoric acid solution to the silicon nitride layer after the hydrofluoric acid solution is used, the fourth etching rate of the phosphoric acid solution to the silicon nitride layer during stable etching and the excess coefficient;
and based on the second cleaning time period, performing second cleaning on the silicon nitride layer by using the phosphoric acid solution.
5. The method according to claim 4, wherein determining the second cleaning duration based on the thickness of the silicon nitride layer, the film thickness, the third etching rate of the silicon nitride layer by the phosphoric acid solution after the hydrofluoric acid solution is used, the fourth etching rate of the silicon nitride layer by the phosphoric acid solution when the silicon nitride layer is stably etched, and the excess coefficient comprises:
Wherein T (H 3PO4) is the second cleaning time period, Y 0 is the film thickness, thk (SiN) is the thickness of the silicon nitride layer, Y 1 is the third etching rate, Y 2 is the fourth etching rate, and n is the excess coefficient.
6. The method of claim 5, wherein the third etch rate is associated with the first cleaning duration, the third etch rate being:
Wherein T (HF) is the first cleaning duration.
7. The method of claim 4, wherein the value of the excess factor is related to a target etching amount of a silicon oxide layer on the semiconductor device, and wherein the value of the excess factor is greater than or equal to 1.2 and less than or equal to 1.6.
8. The method of cleaning silicon nitride according to claim 7, wherein the excess factor has a value of 1.3.
9. A semiconductor device, characterized in that it is manufactured by applying the silicon nitride cleaning method according to any one of the preceding claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410339420.6A CN117976520B (en) | 2024-03-25 | 2024-03-25 | Silicon nitride cleaning method and semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20040077171A1 (en) * | 2002-10-21 | 2004-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and composition to improve a nitride/oxide wet etching selectivity |
| US20080081384A1 (en) * | 2006-09-29 | 2008-04-03 | Fujitsu Limited | Semiconductor device fabrication method and semiconductor device fabrication system |
| CN102136446A (en) * | 2010-01-27 | 2011-07-27 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing silicon wafer with shallow slot isolation structure by wet etching |
| CN115241058A (en) * | 2022-09-23 | 2022-10-25 | 广州粤芯半导体技术有限公司 | Semiconductor device etching method and semiconductor device manufacturing method |
| CN117012636A (en) * | 2023-08-15 | 2023-11-07 | 粤芯半导体技术股份有限公司 | Method for controlling thickness of semiconductor film, semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20040077171A1 (en) * | 2002-10-21 | 2004-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and composition to improve a nitride/oxide wet etching selectivity |
| US20080081384A1 (en) * | 2006-09-29 | 2008-04-03 | Fujitsu Limited | Semiconductor device fabrication method and semiconductor device fabrication system |
| CN102136446A (en) * | 2010-01-27 | 2011-07-27 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing silicon wafer with shallow slot isolation structure by wet etching |
| CN115241058A (en) * | 2022-09-23 | 2022-10-25 | 广州粤芯半导体技术有限公司 | Semiconductor device etching method and semiconductor device manufacturing method |
| CN117012636A (en) * | 2023-08-15 | 2023-11-07 | 粤芯半导体技术股份有限公司 | Method for controlling thickness of semiconductor film, semiconductor device and method for manufacturing the same |
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