JPH03108356A - Manufacturing method of semiconductor substrate - Google Patents
Manufacturing method of semiconductor substrateInfo
- Publication number
- JPH03108356A JPH03108356A JP24603189A JP24603189A JPH03108356A JP H03108356 A JPH03108356 A JP H03108356A JP 24603189 A JP24603189 A JP 24603189A JP 24603189 A JP24603189 A JP 24603189A JP H03108356 A JPH03108356 A JP H03108356A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- layer
- forming
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000005498 polishing Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 7
- 238000000926 separation method Methods 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000003082 abrasive agent Substances 0.000 abstract 2
- 238000007598 dipping method Methods 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 25
- 235000012431 wafers Nutrition 0.000 description 12
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000011863 silicon-based powder Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 235000007575 Calluna vulgaris Nutrition 0.000 description 1
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 210000004185 liver Anatomy 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229960001730 nitrous oxide Drugs 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
Ｓｏｌ基板の製造方法に関し、
シリコン膜厚が平坦で基板間の膜厚の変動も少ないＳＯ
■基板を製造することを目的とし、ウェハ接着法で形成
したＳｏｌ基板の素子形成側のシリコン層に必要とする
パターン幅で下地の絶縁膜に達する分離溝を形成する工
程と、分離溝を形成した該基板上にシリコン酸化物より
なる第１の膜を形成する工程と、該第１の膜の上にポリ
シリコンよりなる第２の膜を形成する工程と、該第１の
膜をストッパとし、分離溝の部分を除き、第２の膜を研
磨して第１の膜を露出させる工程と、溝の段差の高さだ
け第１の膜をエツチングする工程と、溝の部分の第１の
膜をストッパとしてシリコン層を研磨する工程とからな
るか、或いはウェハ接着法で形成したＳｏｌ基板の素子
形成側のシリコン層に必要とするパターン幅で下地の絶
縁膜に達する分離溝を形成する工程と、分離溝を形成し
た該基板上にシリコン酸化物よりなる第１の膜を形成す
る工程と、該第１の膜の上にレジスト膜を被覆する工程
と、反応性イオンエツチングを行って分離溝の部分を除
いてレジスト膜を除去する工程と、分離溝の段差の高さ
だけ第１の膜をエツチングする工程と、分離溝の部分の
第１の膜をストッパとしてシリコン層を研磨する工程と
を含むことを特徴として半導体基板の製造方法を構成す
る。[Detailed Description of the Invention] [Summary] Regarding the method for manufacturing a Sol substrate, the SO substrate has a flat silicon film thickness and little variation in film thickness between substrates.
■For the purpose of manufacturing a substrate, a process of forming a separation groove reaching the underlying insulating film with the required pattern width in the silicon layer on the element formation side of the Sol substrate formed by wafer bonding method, and forming the separation groove. forming a first film made of silicon oxide on the substrate, forming a second film made of polysilicon on the first film, and using the first film as a stopper. , a step of polishing the second film to expose the first film except for the separation groove portion, a step of etching the first film by the height of the groove step, and a step of etching the first film in the groove portion. A step of polishing the silicon layer using the film as a stopper, or a step of forming a separation groove reaching the underlying insulating film with the required pattern width in the silicon layer on the element formation side of the Sol substrate formed by wafer bonding method. A step of forming a first film made of silicon oxide on the substrate in which a separation groove is formed, a step of coating a resist film on the first film, and a step of performing reactive ion etching to separate the substrate. A step of removing the resist film except for the groove portion, a step of etching the first film by the height of the step of the separation groove, and a step of polishing the silicon layer using the first film in the separation groove portion as a stopper. A method for manufacturing a semiconductor substrate is characterized by comprising the following steps.
本発明はシリコン膜の膜厚分布の良い５ｏｉｌ板の製造
方法に関する。The present invention relates to a method for manufacturing a 5-oil plate with a good silicon film thickness distribution.
Ｓ ＯＩ （Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎ５ｕｌａｔ
ｏｒ）基板は、■ この上に形成されるデバイスと基板
間の寄生容量が少ないことから高速動作が可能なこと、
■ 外装に使用するセラミック或いは樹脂パッケージか
らのα線に対して耐性が優れていることから、偉績性の
高いデバイスが形成できることなどから注目されている
。SOI (Silicon On In5ulat)
or) The substrate is capable of high-speed operation due to the low parasitic capacitance between the device formed on it and the substrate;
■ It is attracting attention because it has excellent resistance to alpha rays from the ceramic or resin package used for the exterior, and can be used to form devices with high performance.
Ｓｏｌ基板には各種の製造方法があるが、ウェハ接着法
はＳｉ層の結晶性が優れ、特性の良いデバイスが形成で
きることから本命視されている。There are various methods for manufacturing Sol substrates, but the wafer bonding method is considered the favorite because the Si layer has excellent crystallinity and devices with good characteristics can be formed.
二＼で、従来の方法は二枚のＳｉウェハの一枚を熱酸化
して表面に６０００人〜１μｍの二酸化シリコン（Ｓｉ
ｎｇ）膜を形成した後、二枚のＳｉウェハを接着し、１
１００〜１２００°Ｃの温度で加熱することにより接合
して一体化させる。The conventional method is to thermally oxidize one of two Si wafers to coat the surface with 6,000 to 1 μm of silicon dioxide (Si).
ng) After forming the film, bond two Si wafers and
They are joined and integrated by heating at a temperature of 100 to 1200°C.
次に、５ｔｏｔ膜が形成されているＳｉウェハを数１０
μｍの厚さまで研削し、その後、研削により生じた機械
的なダメージ層を研磨によって除去することによって厚
さが３〜５μｍのＳｉ層を残す方法である。Next, several tens of Si wafers on which a 5tot film was formed were
This method involves grinding to a thickness of 3 to 5 μm, and then removing the mechanically damaged layer caused by the grinding by polishing, leaving a Si layer with a thickness of 3 to 5 μm.
然し、この方法は研削および研磨の工程で厚さの分布が
生ずるために、ＳＯ■基板におけるＳｉ膜の厚さの変動
は約±１μｍあり、また基板相互間では約±２μ−の変
動がある。However, in this method, the thickness distribution occurs during the grinding and polishing process, so the thickness of the Si film on the SO substrate varies by about ±1 μm, and between the substrates there is a variation of about ±2 μ−. .
そして、このＳｉ膜の膜厚変動はバイポーラトランジス
タにおいては素子分離溝の深さ制御の必要を生じ、また
コレクタの直列抵抗値やベース・コレクタ間の抵抗値に
変動をもたらすと云う問題がある。This variation in the thickness of the Si film makes it necessary to control the depth of the isolation trench in bipolar transistors, and also causes variations in the series resistance value of the collector and the resistance value between the base and the collector.
以上のことから、ウェハ接着法で形成したＳＯＩ基板を
量産化するに当たってはＳｉの膜厚分布を改良すること
が必要であった。In view of the above, it is necessary to improve the Si film thickness distribution in order to mass produce SOI substrates formed by the wafer bonding method.
以上記したように従来のウェハ接着法で得られるＳｏｌ
基板はＳｉ膜の膜厚の変動が大きいことがら膜厚分布を
改良することが目的である。As mentioned above, Sol obtained by the conventional wafer bonding method
Since the thickness of the Si film on the substrate varies greatly, the purpose is to improve the film thickness distribution.
上記の課題はウェハ接着法で形成したＳｏｌ基板の素子
形成側のＳｉ層に必要とするパターン幅で下地の絶縁膜
に達する溝を形成する工程と、分離溝を形成した該基板
上にＳｉ酸化物よりなる第１の膜を形成する工程と、該
第１の膜の上にポリＳｉよりなる第２の膜を形成する工
程と、該第１の膜をストッパとし、分離溝の部分を除き
、第２の膜を研磨して第１の膜を露出させる工程と、分
離溝の段差の高さだけ第１の膜をエツチングする工程と
、分離溝の部分の第１の膜をストッパとしてＳｉ層を研
磨する工程とからなるか、或いはウェハ接着法で形成し
たＳｏｌ基板の素子形成側のＳｉ層に必要とするパター
ン幅で下地の絶縁膜に達する分離溝を形成する工程と、
分離溝を形成した該基板上にＳｔ酸化物よりなる第１の
膜を形成する工程と、該第１の膜の上にレジスト膜を被
覆する工程と、反応性イオンエツチングを行って分離溝
の部分を除いてレジスト膜を除去する工程と、分離溝の
段差の高さだけ第１の膜をエツチングする工程と、分離
溝の部分の第１の膜をストッパとしてＳｉ層を研磨する
工程とを含むことを特徴として半導体基板の製造方法を
構成することにより解決することができる。The above issues are the process of forming grooves reaching the underlying insulating film with the required pattern width in the Si layer on the element formation side of the Sol substrate formed by the wafer bonding method, and the process of oxidizing Si on the substrate with the isolation grooves formed. a step of forming a first film made of poly-Si on the first film, and a step of forming a second film made of poly-Si on the first film, using the first film as a stopper and removing the separation groove portion. , a step of polishing the second film to expose the first film, a step of etching the first film by the height of the step of the separation trench, and a step of etching the first film in the part of the separation trench as a stopper. a step of polishing the layer, or a step of forming a separation groove reaching the underlying insulating film with the required pattern width in the Si layer on the element formation side of the Sol substrate formed by wafer bonding;
A step of forming a first film made of St oxide on the substrate with the separation groove formed thereon, a step of coating the first film with a resist film, and a step of performing reactive ion etching to form the separation groove. A step of removing the resist film except for a portion, a step of etching the first film by the height of the step of the separation trench, and a step of polishing the Si layer using the first film in the portion of the separation trench as a stopper. This problem can be solved by configuring a method for manufacturing a semiconductor substrate that includes the following features.
〔作用］
本発明は気相成長法（略称ＣＶＤ法）で被処理基板上に
得られるＳｉ酸化物膜（ＳｉＯ□膜）の膜厚分布が比較
的よいことから、ＳＯＩ基板におけるＳｉ層の膜厚をこ
のＳｉＯ□膜の膜厚と等しくすることにより膜厚変動の
少ないＳｏｌ基板を作るものである。[Function] The present invention has a relatively good film thickness distribution of the Si oxide film (SiO□ film) obtained on the substrate to be processed by the vapor phase growth method (abbreviated as CVD method). By making the thickness equal to the thickness of this SiO□ film, a Sol substrate with less variation in film thickness is produced.
すなわち、ウェハ接合法により得られるＳＯＩ基板の１
層は厚さが約１ｕＩＩ＋程度のＳｉＯ□膜であり、この
上にＳｉ膜が設けられているが、本発明は予め写真蝕刻
技術（フォトリソグラフィ）により部分的にＳｉ膜を除
いてＳｉ０ｇ膜を露出しておき、この上にＣＶＤ法によ
り必要とする厚さのＳｉｎ、膜を作り、このＳｉｎ、膜
の厚さまでＳｉ膜を研磨することにより膜厚分布の良い
ＳＯＩ基板を形成するものである。That is, one of the SOI substrates obtained by the wafer bonding method
The layer is a SiO□ film with a thickness of approximately 1uII+, and a Si film is provided on top of this.However, in the present invention, the Si film is partially removed by photolithography to form an Si0g film. The SOI substrate with a good film thickness distribution is formed by exposing the Si film, forming a Si film of the required thickness by CVD on this, and polishing the Si film to the thickness of this Sin film. .
そのためにはＳｉｎｇとＳｔのエツチングにおいて選択
比の優れた薬品の使用が必要であり、Ｓｉｎｇのみをエ
ツチングするには弗酸（ＨＰ）を用い、一方、Ｓｉのみ
をエツチングするにはエチレンジアミン（ＨｚＮＣＨｚ
ＣｌｈＮＨｚ）などの使用が必要である。For this purpose, it is necessary to use chemicals with excellent selectivity in etching Sing and St. Hydrofluoric acid (HP) is used to etch only Sing, while ethylenediamine (HzNCHz) is used to etch only Si.
ClhNHz) etc. are required.
なお、ＨＦ液に浸漬してＳｉＯ□膜をエツチングする場
合には時により、オーバエツチングが生じ、熱酸化膜ま
で侵される恐れがあるが、これを避けるにはＳｉＯ□膜
を二層構造とするとよい。Note that when etching a SiO□ film by immersing it in an HF solution, over-etching may sometimes occur, and there is a risk that the thermal oxide film may be attacked. good.
〔実施例］
実施例１： （請求項１および第１図関連）ウェハ接着
法で形成したＳｏｌ基板の素子形成側のＳｉ層■の上に
従来と同様にレジストを膜形成した後、投影露光と現像
を行ってレジスト膜を窓開けし、四弗化炭素（ＣＦ４）
と酸素（０２）を使用ガスとし反応性イオンエツチング
（ＲＩＥ）を行い、Ｓｉｎｇからなる絶縁膜２に達する
までエツチングを行って素子間分離用の分離溝３を形成
した。[Example] Example 1: (Related to Claim 1 and FIG. 1) After forming a resist film in the same way as in the conventional method on the Si layer (1) on the element formation side of the Sol substrate formed by the wafer bonding method, projection exposure was performed. The resist film was developed and developed to open a window, and carbon tetrafluoride (CF4) was applied.
Reactive ion etching (RIE) was performed using oxygen (02) and oxygen (02) as gases, and etching was performed until reaching the insulating film 2 made of Sing to form isolation grooves 3 for isolation between elements.
（以上第１図Ａ）
次に、シラン（ＳｉＨ４）と−酸化二窒素（ＮｚＯ）を
反応ガスとしてＣＶＤを行い、作らんとするＳＯ■基板
の１層の厚さに等しい厚さまでＳｉＯ□よりなる第１の
膜４を形成した。（以上同図Ｂ）次に、この上に５ｉ）
Ｉ４と水素（Ｈ２） を反応ガスとしてＣＶＤを行い
、ポリＳｔからなる第２の膜５を形成した。（以上同図
Ｃ）
次に、エチレンジアミンにコロイダルＳｉ粉末を０．１
〜０．５％混合しである研磨剤を用いて研磨し、分離溝
３の部分を除いてＳＯＩ基板上の第２の膜（ポリＳｉ膜
）を除去した。(See Figure 1 A) Next, CVD is performed using silane (SiH4) and dinitrogen oxide (NzO) as reaction gases, and SiO□ is heated to a thickness equal to the thickness of one layer of the SO□ substrate to be made. A first film 4 was formed. (The above is B in the same figure) Next, 5i on top of this)
CVD was performed using I4 and hydrogen (H2) as reaction gases to form a second film 5 made of polySt. (The above is C in the same figure) Next, 0.1% of colloidal Si powder was added to ethylenediamine.
The second film (poly-Si film) on the SOI substrate was removed except for the separation groove 3 by polishing using a polishing agent containing ~0.5% of the mixture.
なお、第１の膜（Ｓｉ０ｇ膜）はエチレンジアミンには
溶解しない。（以上同図Ｄ）
次に、肝液に浸漬することにより第１の膜（ＳｔＯ□膜
）を分離溝３の段差相当分だけ溶解して除去した。Note that the first film (Si0g film) does not dissolve in ethylenediamine. (See Figure D) Next, by immersing it in liver fluid, the first film (StO□ film) was dissolved and removed by an amount corresponding to the step difference in the separation groove 3.
なお、ＨＦ液には第２の膜（ポリＳｉ）は溶解しない。Note that the second film (poly-Si) is not dissolved in the HF solution.
（以上同図Ｅ）
次に、先と同様にエチレンジアミンにコロイダルＳｉ粉
末を０．１〜０．５％混合しである研磨剤を用いて研磨
すると、分離溝３の第１の膜（ＳｉＯ□膜）がストッパ
として働き、この第１の膜の厚さに相当する厚さのＳｉ
層１が残った。（以上同図Ｆ）これにより、必要とする
厚さのＳｉ膜を備えたＳＯｒ基板が完成した。(See Figure E) Next, as before, polishing is performed using an abrasive containing 0.1 to 0.5% colloidal Si powder in ethylenediamine, and the first film (SiO□ film) acts as a stopper, and a Si film with a thickness corresponding to the thickness of this first film acts as a stopper.
Layer 1 remained. (The above is F in the same figure) As a result, an SOr substrate provided with a Si film of the required thickness was completed.
実施例２： （請求項２および第２図関連）実施例１と
全く同様にして準備したＳｏｌ基板のＳｉ層１をドライ
エツチングして素子間分離用の分離溝３を形成した。（
以上第２図Ａ）次に実施例１と同様に必要とする厚さに
５ｉｎ２からなる第１の膜４を形成した。（以上同図Ｂ
）次に、スピンコード法によりレジストを被覆し表面に
レジスト膜６を形成した。Example 2: (Related to Claim 2 and FIG. 2) The Si layer 1 of a Sol substrate prepared in exactly the same manner as in Example 1 was dry-etched to form isolation grooves 3 for isolation between elements. (
Above (FIG. 2A) Next, as in Example 1, a first film 4 having a thickness of 5 inches was formed to the required thickness. (The above figure B
) Next, a resist was coated by a spin code method to form a resist film 6 on the surface.
なお、分離溝３はレジストにより穴埋めされている。（
以上同図Ｃ）
次に、０２プラズマを用いるアッシング処理により、分
離溝３の部分を除いてレジスト膜６を除去した。（以上
同図Ｄ）
以下、実施例１と同様にＨＰを用い、分離溝３のレジス
ト膜６の下にある第１の膜の高さまでＳｉＯ□からなる
第１の膜４を溶解除去した。Note that the separation groove 3 is filled with resist. (
C) Next, the resist film 6 was removed except for the separation groove 3 by ashing using 02 plasma. (The above is D in the same figure) Thereafter, as in Example 1, using HP, the first film 4 made of SiO□ was dissolved and removed up to the height of the first film below the resist film 6 in the separation groove 3.
（以上同図Ｅ）
次に、研磨剤を用いて第１の膜４の高さまでＳｉ層１を
研磨することにより必要とする厚さのＳｉ膜を備えたＳ
ＯＩ基板が完成した。（以上同図Ｆ）実施例３： （請
求項３および第３図関連、 ＩＰのオーバエツチングに
強い構造）
実施例１と全く同様にして準備した３０１基板のＳｉ層
１をドライエツチングして素子間分離用の分離溝３を形
成した後、下層をポリＳｉ膜８．上層をＳｉＯ□膜９と
してＣＶＤ法により第１の膜４を二層に形成した。(E in the same figure) Next, by polishing the Si layer 1 to the height of the first film 4 using an abrasive, the Si layer 1 is formed with a Si film of the required thickness.
The OI board has been completed. (The above figure F) Example 3: (Related to claim 3 and Figure 3, structure resistant to IP overetching) The Si layer 1 of the 301 substrate prepared in exactly the same manner as in Example 1 was dry etched to form an element. After forming the isolation groove 3 for separation between the layers, the lower layer is formed with a poly-Si film 8. The first film 4 was formed into two layers by CVD using the SiO□ film 9 as the upper layer.
こ＼で、下層のポリＳｉ膜８の厚さは上層の５ｉＯｚ膜
９よりも薄くてもよい。（以上第３図Ａ）以下実施例１
と同様にこの上にポリＳｔよりなる第２の膜５を形成し
、（同図Ｂ）、研磨により分離溝３を部分を除いて第２
の膜を除去する。Here, the thickness of the lower poly-Si film 8 may be thinner than the 5iOz film 9 of the upper layer. (Above, Figure 3 A) Below, Example 1
In the same manner as above, a second film 5 made of polySt is formed (FIG. B), and by polishing, the separation groove 3 is polished except for the second film 5.
remove the film.
（以上同図Ｃ）
次に、同図りは、ＨＦ液に浸漬して第１の膜を構成する
Ｓｉｎ、膜９を溶解除去する際にオーバエツチングが生
じ、ＳｉＯ□膜９のレベルよりも溶解が進行したが、ポ
リＳｉ膜８の存在によりエツチングを止めることができ
た。(See Figure C) Next, when the film is immersed in an HF solution to dissolve and remove the Sin film 9 that constitutes the first film, overetching occurs, and the level of dissolution is higher than that of the SiO□ film 9. However, the presence of the poly-Si film 8 made it possible to stop the etching.
以下、実施例１と同様に研磨剤を用いてポリＳｉ膜８と
５ｉ０２膜９からなる第１の膜の位置まで研磨すること
により、必要とする厚さのＳｉ膜を備えたＳＯＴ基板が
完成した。（以上同図Ｅ）なお、第１の膜をポリＳｉ膜
とＳｉＯ□膜で形成する代わりに窒化硅素（Ｓｉ、Ｎ、
）膜と５ｉＯｚ膜で形成しても結果は同様である。Thereafter, as in Example 1, polishing was performed using an abrasive to the position of the first film consisting of the poly-Si film 8 and the 5i02 film 9, thereby completing the SOT substrate with the Si film of the required thickness. did. (E in the same figure) Note that instead of forming the first film with a poly-Si film and a SiO□ film, silicon nitride (Si, N,
) film and a 5iOz film, the results are similar.
なお、実施例１〜３においては不純物を含まないＳｉ０
ｇ膜を使用しているが、燐（Ｐ）あるいは硼素（Ｂ）を
含んだＳｉＯ□膜であっても差支えない。In addition, in Examples 1 to 3, Si0 containing no impurities was used.
Although a SiO□ film containing phosphorus (P) or boron (B) is used, there is no problem.
第３図は本発明に係る更に別のＳＯＩ基板の製造工程を
示す断面図、
図において、
１はＳｉ層、
３は分離溝、
５は第２の膜、
８はポリＳｉ膜、
である。FIG. 3 is a cross-sectional view showing the manufacturing process of yet another SOI substrate according to the present invention. In the figure, 1 is a Si layer, 3 is a separation groove, 5 is a second film, and 8 is a poly-Si film.
２は絶縁膜、
４は第１の膜、
６はレジスト膜、
９はＳｉＯ□膜、
〔発明の効果〕
本発明の実施により必要とする厚さのＳｉ膜を備え、膜
厚分布の優れたＳＯＩ基板を得ることができる。2 is an insulating film; 4 is a first film; 6 is a resist film; 9 is a SiO□ film; An SOI substrate can be obtained.
第１図は本発明に係るＳｏｌ基板の製造工程を示す断面
図、
第２図は本発明に係る別のＳｏｌ基板の製造工程を示す
断面図、
４努ご萌に羞：ａｓｏｒｓ仮の製造エイを示１１野面記
ｖＩ ｉ 起
（８）
（Ｆン
杢発明に停う別ｆ）５０１基後のＩ！Ｉ造工韓を示す断
市旧１２ 記FIG. 1 is a cross-sectional view showing the manufacturing process of a Sol substrate according to the present invention, and FIG. 2 is a cross-sectional view showing the manufacturing process of another Sol substrate according to the present invention. 11 Nomenki vI i Ki (8) (Another f that stops at the Fn heather invention) I after 501 units! 12 old city records showing the construction of Korea
Claims (3)
のシリコン層（１）に必要とするパターン幅で下地の絶
縁膜（２）に達する分離溝（３）を形成する工程と、 分離溝（３）を形成した該基板上にシリコン酸化物より
なる第１の膜（４）を形成する工程と、該第１の膜の上
にポリシリコンよりなる第２の膜（５）を形成する工程
と、 該第１の膜（４）をストッパとし、分離溝（３）の部分
を除き、第２の膜（５）を研磨して第１の膜（４）を露
出させる工程と、 分離溝（３）の段差の高さだけ第１の膜（４）をエッチ
ングする工程と、 分離溝（３）の部分の第１の膜（４）をストッパとして
シリコン層（１）を研磨する工程と、 を含むことを特徴とする半導体基板の製造方法。(1) A step of forming an isolation groove (3) reaching the underlying insulating film (2) with the required pattern width in the silicon layer (1) on the element formation side of the SOI substrate formed by the wafer bonding method; A step of forming a first film (4) made of silicon oxide on the substrate on which (3) has been formed, and forming a second film (5) made of polysilicon on the first film. a step of using the first film (4) as a stopper and polishing the second film (5) except for the separation groove (3) to expose the first film (4); A process of etching the first film (4) by the height of the step of the groove (3), and a process of polishing the silicon layer (1) using the first film (4) in the separation groove (3) as a stopper. A method for manufacturing a semiconductor substrate, comprising: and.
のシリコン層（１）に必要とするパターン幅で下地の絶
縁膜（２）に達する分離溝（３）を形成する工程と、 分離溝（３）を形成した該基板上にシリコン酸化物より
なる第１の膜（４）を形成する工程と、該第１の膜（４
）の上にレジスト膜（６）を被覆する工程と、 反応性イオンエッチングを行なって分離溝（３）の部分
を除いてレジスト膜（６）を除去する工程と、分離溝（
３）の段差の高さだけ第１の膜（４）をエッチ ングす
る工程と、 分離溝（３）の部分の第１の膜（４）をストッパとして
シリコン層（１）を研磨する工程と、 を含むことを特徴とする半導体基板の製造方法。(2) A step of forming an isolation groove (3) reaching the underlying insulating film (2) with the required pattern width in the silicon layer (1) on the element forming side of the SOI substrate formed by the wafer bonding method; and a step of forming a first film (4) made of silicon oxide on the substrate on which the film (3) has been formed;
) is coated with a resist film (6), a step of performing reactive ion etching to remove the resist film (6) except for the part of the separation groove (3), and a process of removing the resist film (6) on the separation groove (3).
3) a step of etching the first film (4) by the height of the step; and a step of polishing the silicon layer (1) using the first film (4) in the separation groove (3) as a stopper. A method for manufacturing a semiconductor substrate, comprising: .
おいて、 第１の膜（４）が酸化シリコン膜（９）とポリシリコン
膜（８）との二層膜あるいは酸化シリコン膜と窒化シ
リコン膜との二層膜からなることを特徴とする半導体基
板の製造方法。(3) In the method of manufacturing a semiconductor substrate according to claims 1 and 2, the first film (4) is a double layer film of a silicon oxide film (9) and a polysilicon film (8) or a silicon oxide film and a silicon nitride film.
A method for manufacturing a semiconductor substrate, characterized in that it consists of a two-layer film including a silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24603189A JPH03108356A (en) | 1989-09-21 | 1989-09-21 | Manufacturing method of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24603189A JPH03108356A (en) | 1989-09-21 | 1989-09-21 | Manufacturing method of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03108356A true JPH03108356A (en) | 1991-05-08 |
Family
ID=17142424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24603189A Pending JPH03108356A (en) | 1989-09-21 | 1989-09-21 | Manufacturing method of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03108356A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5399233A (en) * | 1991-12-05 | 1995-03-21 | Fujitsu Limited | Method of and apparatus for manufacturing a semiconductor substrate |
| US5643837A (en) * | 1992-04-15 | 1997-07-01 | Nec Corporation | Method of flattening the surface of a semiconductor device by polishing |
| US6242320B1 (en) | 1998-12-17 | 2001-06-05 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating SOI wafer |
-
1989
- 1989-09-21 JP JP24603189A patent/JPH03108356A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5399233A (en) * | 1991-12-05 | 1995-03-21 | Fujitsu Limited | Method of and apparatus for manufacturing a semiconductor substrate |
| US5643837A (en) * | 1992-04-15 | 1997-07-01 | Nec Corporation | Method of flattening the surface of a semiconductor device by polishing |
| US5688720A (en) * | 1992-04-15 | 1997-11-18 | Nec Corporation | Method of flattening the surface of a semiconductor device by polishing |
| US6242320B1 (en) | 1998-12-17 | 2001-06-05 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating SOI wafer |
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