JPH012342A - Package for semiconductor devices - Google Patents
Package for semiconductor devicesInfo
- Publication number
- JPH012342A JPH012342A JP62-158067A JP15806787A JPH012342A JP H012342 A JPH012342 A JP H012342A JP 15806787 A JP15806787 A JP 15806787A JP H012342 A JPH012342 A JP H012342A
- Authority
- JP
- Japan
- Prior art keywords
- external connection
- view
- package
- connection terminals
- sectional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000011810 insulating material Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 description 5
- 125000002091 cationic group Chemical group 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置用パッケージに関し、特に外部接続
用端子部の構造を改良する半導体装置用パッケージに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor device, and more particularly to a package for a semiconductor device in which the structure of a terminal portion for external connection is improved.
従来、この種の半導体装置用パッケージは、その−例の
平面図および断面図が、それぞれ第５図および第６図に
示されるように、ケース１．外部接続用端子３、ボンデ
ィングワイヤ４および半３．）体チップ５を備えて構成
されている。第６図は第５図におけるＡ−Ａ’線に対す
る断面図である。Conventionally, this type of semiconductor device package has a case 1, an example of which is shown in a plan view and a cross-sectional view in FIGS. 5 and 6, respectively. External connection terminal 3, bonding wire 4 and half 3. ) body chip 5. FIG. 6 is a sectional view taken along line AA' in FIG. 5.
第５図および第６図より明らかなように、外部接続用端
子３は導電体である金属を使用しているために、それぞ
れ分離された構造となっている。As is clear from FIGS. 5 and 6, since the external connection terminals 3 are made of conductive metal, they are separated from each other.
上述した従来の半導体装置用パッケージは、外部接続用
端子が個々に分離されて構成されているため、パッケー
ジに外力が加えられると簡単に外部接続用端子が変形し
たり、または隣接する外部接続用端子と接触してしまう
という欠点がある。In the conventional semiconductor device package described above, the external connection terminals are separated individually, so when an external force is applied to the package, the external connection terminals easily deform or the adjacent external connection terminals are easily deformed. The disadvantage is that it comes into contact with the terminal.
本発明の半導体装置用パッケージは、所定の外部接続用
端子の外部との接続部を除く部分を絶縁物質にて被覆し
、且つ相互に隣接する前記外部接続用端子を前記絶縁物
質を介して一体化構造として形成される。In the semiconductor device package of the present invention, a portion of a predetermined external connection terminal except for a connection portion with the outside is covered with an insulating material, and the mutually adjacent external connection terminals are integrated through the insulating material. It is formed as a cationic structure.
次に、本発明について図面を参照して説明す゛る。 Next, the present invention will be explained with reference to the drawings.
第１図および第２図は、それぞれ本発明の第１の実施例
の平面図および断面図である。なお、第２図の断面図は
、第１図におけるＡ−Ａ’線に対応する断面図である。1 and 2 are a plan view and a sectional view, respectively, of a first embodiment of the present invention. Note that the cross-sectional view in FIG. 2 is a cross-sectional view corresponding to the line AA' in FIG. 1.
第１図および第２図に示されるように、本実施例は、ケ
ース１と、端子間絶縁物２と、外部接続用端子３と、ボ
ンディングワイヤ・１と、半導体チップ５と、備えて構
成されろ。As shown in FIGS. 1 and 2, this embodiment includes a case 1, an inter-terminal insulator 2, an external connection terminal 3, a bonding wire 1, and a semiconductor chip 5. Be it.
第１図および第２図より明らかなように、ケース１に取
付けられている外部接続用端子３は、端子間絶縁’Ｍ２
により、先端部を除いて被覆されるとともに相互に隣接
する外部接続用端子３が一体化された構造となっている
。このため、隣接する外部接続用端子３の相互間の接触
は未然に防止される。As is clear from FIGS. 1 and 2, the external connection terminal 3 attached to the case 1 has inter-terminal insulation 'M2'.
As a result, the external connection terminals 3 are covered except for their tips and are integrated with each other. Therefore, contact between adjacent external connection terminals 3 is prevented.
第３図および第４図は、それぞれ本発明の第２の実施例
の平面図および断面図である。第４図の断面図は、第３
図におけるＡ−Ａ’線に対応する断面図である。第３図
および第４図に示されるように、外部接続用端子３は、
その中間部を端子間絶縁物２により被覆されるとともに
相互に隣接する外部接続用端子３が一体化された構造と
なっている。この第２の実施例においては、ケース１に
半導体チップ５および外部接続用端子３を封止した後に
おいても、端子間絶縁物２を形成することができる。従
って、端子間絶縁物２の着脱が可能な構造とすることが
できるという利点がある。3 and 4 are a plan view and a sectional view, respectively, of a second embodiment of the invention. The cross-sectional view in Figure 4 shows the third
It is a sectional view corresponding to the AA' line in the figure. As shown in FIGS. 3 and 4, the external connection terminal 3 is
The intermediate portion is covered with an inter-terminal insulator 2, and mutually adjacent external connection terminals 3 are integrated. In this second embodiment, even after the semiconductor chip 5 and the external connection terminals 3 are sealed in the case 1, the inter-terminal insulator 2 can be formed. Therefore, there is an advantage that the structure allows the inter-terminal insulator 2 to be attached and detached.
以上説明したように、本発明は、半導体装置用パッケー
ジに適用されて、隣接する外部接続用端子の外部接続部
分を除いた部分を絶縁物で被覆し、且つ前記外部接続用
端子を前記絶縁物を介して一体化構造とすることにより
、外部接続用端子が変形しにくくなるとともに、隣接す
る外部接続端子の接触を防止することができるという効
果がある。As described above, the present invention is applied to a package for a semiconductor device, in which the portions of adjacent external connection terminals excluding external connection portions are covered with an insulating material, and the external connection terminals are covered with an insulating material. By forming an integrated structure via the external connection terminals, it is possible to prevent the external connection terminals from deforming easily and to prevent adjacent external connection terminals from coming into contact with each other.
°第１図および第２図は、それぞれ本発明の第１の実施
例の平面図および断面図、第３図および第４図は、それ
ぞれの本発明の第２の実施例の平面図および断面図、第
５図および第６図は、それぞれ従来の半導体装置用パッ
ケージの平面図および断面図である。
図において、１・・・ケース、２・・・端子絶縁物、３
・・・外部接続用端子、４・・・ボンディングワイヤ、
５・・・半導体チップ。
代理人 弁理士 内 原 晋・′・
第１図
第２図
第５図1 and 2 are a plan view and a sectional view of a first embodiment of the present invention, respectively, and FIGS. 3 and 4 are a plan view and a sectional view of a second embodiment of the present invention, respectively. 5 and 6 are a plan view and a cross-sectional view, respectively, of a conventional package for a semiconductor device. In the figure, 1... Case, 2... Terminal insulator, 3
...External connection terminal, 4...Bonding wire,
5...Semiconductor chip. Agent: Susumu Uchihara, Patent Attorney Figure 1 Figure 2 Figure 5
Claims (1)
絶縁物質にて被覆し、且つ相互に隣接する前記外部接続
用端子を前記絶縁物質を介して一体化構造として形成さ
れることを特徴とする半導体装置用パッケージ。A portion of a predetermined external connection terminal except for a connection portion with the outside is covered with an insulating material, and the mutually adjacent external connection terminals are formed as an integrated structure with the insulating material interposed therebetween. Package for semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-158067A JPH012342A (en) | 1987-06-24 | Package for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-158067A JPH012342A (en) | 1987-06-24 | Package for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS642342A JPS642342A (en) | 1989-01-06 |
| JPH012342A true JPH012342A (en) | 1989-01-06 |
Family
ID=
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