JPH01230223A - Manufacture of superlattice - Google Patents

Manufacture of superlattice

Info

Publication number
JPH01230223A
JPH01230223A JP5495188A JP5495188A JPH01230223A JP H01230223 A JPH01230223 A JP H01230223A JP 5495188 A JP5495188 A JP 5495188A JP 5495188 A JP5495188 A JP 5495188A JP H01230223 A JPH01230223 A JP H01230223A
Authority
JP
Japan
Prior art keywords
layer
superlattice
growing
growth
temperatures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5495188A
Other languages
Japanese (ja)
Inventor
Kenji Kono
憲司 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5495188A priority Critical patent/JPH01230223A/en
Publication of JPH01230223A publication Critical patent/JPH01230223A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make a transition layer yielded at a heterointerface thinner than a superlattice layer, by setting a growing temperatures for various semiconductors as specified in a method wherein a plurality of the kinds of semiconductor layers of superlattices on a substrate are formed by vapor growth of organic metal. CONSTITUTION:Growing temperatures of a plurality of the different kinds of semiconductors are set at the temperatures within reaction-rate determining processes. Then, the growing temperatures can be decreased. The growing speed becomes very low. Therefore, a transition layer which is yielded at a heterointerface in continuous growing of the different compound semiconductor becomes thinner than each superlattice layer. The very thin layer is steeply grown with good controllability of the film thickness, and the device having the desired characteristics can be obtained.

Description

【発明の詳細な説明】 〔概 要〕 超格子層の製造方法に係り、特にM[1CVD(有機金
属を用いた気相成長)法を用いてHEMTあるいは量子
井戸レーザを作るために数原子オーダーの超格子層を形
成する方法に関し、 複数、特に異種の化合物半導体の結晶の成長に際し、半
導体層へテロ界面を急峻にする超格子の製造方法を提供
することを目的とし、 有機金属の熱分解を用いた気相成長法を用いて、基板上
に複数の化合物半導体層からなる超格子を製造する方法
において、 前記複数の化合物半導体の各々の成長温度を、各々の反
応律速過程内の温度に設定することを構成とする。
[Detailed Description of the Invention] [Summary] It relates to a method for manufacturing a superlattice layer, particularly in the order of several atoms to create a HEMT or a quantum well laser using the M [1CVD (organic metal vapor phase epitaxy) method. The purpose of the present invention is to provide a method for producing a superlattice that makes the heterointerface of semiconductor layers steep when growing crystals of multiple, especially different types of compound semiconductors, and to provide a method for producing a superlattice that makes the heterointerface of semiconductor layers steep. In a method of manufacturing a superlattice consisting of a plurality of compound semiconductor layers on a substrate using a vapor phase growth method using Setting is configuration.

〔産業上の利用分野〕[Industrial application field]

本発明は超格子層の製造方法に係り、特にNr o c
 v D(有機金属を用いた気相成長)法を用いてHE
MTあるいは量子井戸レーザを作るために数原子オーダ
ーの超格子層を形成する方法に関する。
The present invention relates to a method for manufacturing a superlattice layer, and particularly to a method for manufacturing a superlattice layer, and in particular,
HE using the vD (organometallic vapor phase growth) method
The present invention relates to a method for forming a superlattice layer of several atoms order in order to create an MT or quantum well laser.

〔従来の技術及び解決すべき課題〕[Conventional technology and issues to be solved]

従来HE!、IT (高電子移動度トランジスタ)や量
子井戸レーザを製造するために、例えば数原子オーダー
の化合物半導体の極薄膜あるいは超格子層の形成がなさ
れる。
Conventional HE! , IT (high electron mobility transistors) and quantum well lasers, for example, extremely thin films or superlattice layers of compound semiconductors on the order of several atoms are formed.

このような超格子層の形成は上記、M OCV D法に
よりなされる。
Formation of such a superlattice layer is performed by the MOCVD method described above.

例えばGaAs基板上に例えばG a A Sからなる
A層があり、その上にA I GaAsからなるBi2
を形成する場合ガスの切換えが第5A図のように急峻で
あれば第5B図に示すようにA層とB層とのへテロ界面
が明確に(急峻に)なる。しかしながら、通常供給ガス
AからガスBの切換えが、供給ガスの切れが悪いためA
、Bの各ガスが混合して第6A図及び第6B図に示すよ
うにヘテロ界面が急峻な単層膜や超格子層が形成できず
、従って所望のデバイス特性を得ることができない。
For example, there is an A layer made of GaAs on a GaAs substrate, and on top of that is a Bi2 layer made of A I GaAs.
If the gas switching is steep as shown in FIG. 5A, the hetero interface between the A layer and the B layer becomes clear (steep) as shown in FIG. 5B. However, normally, switching from supply gas A to gas B is difficult, so A
, B cannot be mixed to form a single layer film or a superlattice layer with a steep heterointerface as shown in FIGS. 6A and 6B, and therefore desired device characteristics cannot be obtained.

本発明は複数、特に異種の化合物半導体の結晶の成長に
際し、半導体層へテロ界面を急峻にする超格子の製造方
法を提供することを目的とする。
An object of the present invention is to provide a method for manufacturing a superlattice in which a heterointerface between semiconductor layers is made steep during the growth of crystals of a plurality of compound semiconductors, particularly different types of compound semiconductors.

口課題を解決するための手段〕 上記課題は本発明によれば有機金属の熱分解を用いた気
相成長法(!、l0CVD法)を用いて、基板上に複数
の化合物半導体層からなる超格子を製造する方法におい
て、前記複数の化合物半導体の各々の成長温度を、各々
の反応律速過程内の温度に設定することを特徴とする超
格子の製造方法によって解決される。
[Means for Solving the Problems] According to the present invention, the above problems are achieved by forming a superstructure consisting of a plurality of compound semiconductor layers on a substrate using a vapor phase growth method (!, 10CVD method) using thermal decomposition of an organic metal. The problem is solved by a superlattice manufacturing method characterized in that the growth temperature of each of the plurality of compound semiconductors is set to a temperature within each reaction rate-limiting process.

〔作 用〕[For production]

本発明によれば反応律速過程において温度に依存して成
長速度が変化するMOCVD法を成長法として用いた場
合、成長温度を下げることにより、成長速度を極端に遅
くできる。従って、複数、特に異種の化合物半導体の連
続成長におけるヘテロ界面に生じる遷移層が各々の超格
子層厚に比して極めて4く形成されるので各化合物半導
体の超格子層界面が急峻に形成される。
According to the present invention, when the MOCVD method in which the growth rate changes depending on temperature in a reaction rate-limiting process is used as a growth method, the growth rate can be extremely slowed by lowering the growth temperature. Therefore, in the continuous growth of multiple, especially different types of compound semiconductors, the number of transition layers that occur at the hetero interface is extremely large compared to the thickness of each superlattice layer, so the superlattice layer interface of each compound semiconductor is formed steeply. Ru.

〔実施例〕〔Example〕

以下まず本発明の原理を図面に基づいて説明する。 First, the principle of the present invention will be explained based on the drawings.

第1図及び第2図はそれぞれ本発明の詳細な説明するた
めの、時間とガス供給量の関係を示す図及びその条件に
より形成された超格子層を示す模式図である。
FIG. 1 and FIG. 2 are diagrams showing the relationship between time and gas supply amount, and schematic diagrams showing a superlattice layer formed under the conditions, respectively, for detailed explanation of the present invention.

第1図に示すように本発明では成長速度が極端に遅くな
るのでたとえ数原子オーダーのA層を形成する時でも、
ガスA、Bの混合時間ΔTARに辻較してA層の成長時
間TAは十分に長い。このため第2図に示したA、8間
の遷移層ΔdABは無視できへテロ界面が急峻なA層、
B層を得ることができるのである。
As shown in FIG. 1, in the present invention, the growth rate is extremely slow, so even when forming an A layer of the order of several atoms,
The growth time TA of the A layer is sufficiently long compared to the mixing time ΔTAR of the gases A and B. Therefore, the transition layer ΔdAB between A and 8 shown in FIG. 2 can be ignored, and the A layer with a steep hetero interface,
Thus, layer B can be obtained.

第3図は、原料ガス(アルシンAsH,、トリメチルガ
リウムT M G )の供給量を一定にした時の成長温
度の逆数(1/成成長度に一’ Xl03)と、成長速
度(人/分)との関係を示す図である。
Figure 3 shows the reciprocal of the growth temperature (1/1' Xl03 to the growth rate) and the growth rate (person/min) when the supply amount of the raw material gas (arsine AsH, trimethylgallium TMG) is kept constant. ) is a diagram showing the relationship between

一般にMOCVD法ではその反応過程が反応律速過程で
あれば温度に依存してその成長速度は変化する。
Generally, in the MOCVD method, if the reaction process is a rate-limiting process, the growth rate changes depending on the temperature.

第3図に示すように一般に温度が約600℃以下では反
応律速域に入るので成長温度を下げることにより、成長
速度を指数関数的に低下させることができるう また第3図から、成長温度が約350℃以下であれば成
長速度は毎分数人すなわち約1分間で1原子層を形成す
ることになる。この値は拡散律速過程を利用する通常の
MOCVD法ではほとんど実現不可能な値である。
As shown in Figure 3, in general, when the temperature is below about 600°C, it enters the reaction rate-limiting region, so by lowering the growth temperature, the growth rate can be reduced exponentially. If the temperature is about 350° C. or lower, the growth rate is several layers per minute, that is, one atomic layer is formed in about one minute. This value is almost impossible to achieve with the normal MOCVD method that utilizes a diffusion controlled process.

このように反応律速過程を利用して低温で成長したGa
As、 AβGaAs等の薄膜の結晶は一般に多結晶か
あるいはアモルファス状態であるので成長過程終了後熱
処理を行ない単結晶化する。
Ga grown at low temperature using the reaction rate-limiting process in this way
Since the crystals of thin films such as As and AβGaAs are generally in a polycrystalline or amorphous state, a heat treatment is performed after the growth process to convert them into single crystals.

第4図は成長温度プログラムを示す図である。FIG. 4 is a diagram showing a growth temperature program.

第4図によれば成長温度は約350℃、アニール温度及
びその時間は約750℃、10分程度である。
According to FIG. 4, the growth temperature is about 350° C., and the annealing temperature and time are about 750° C. and about 10 minutes.

アニール温度は、極薄膜を単結晶化させるためには高け
れば高い方が良いと思われるが高過ぎると熱損傷を受け
たり、固相拡販により界面がダレるので750℃以下が
適当である。
It is thought that the higher the annealing temperature is, the better in order to make the extremely thin film into a single crystal, but if it is too high, thermal damage may occur or the interface will sag due to solid phase sales, so a temperature of 750° C. or lower is appropriate.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば反応律速過程を利用
した低温成長による成長速度の極端な減少に伴なって極
薄膜を急峻にかつ膜厚制御性良く成長させることができ
る。このため理論通りのデバイス特性を引き出すことが
可能となる。
As explained above, according to the present invention, an extremely thin film can be grown steeply and with good film thickness control as the growth rate is extremely reduced by low-temperature growth using a reaction rate-determining process. Therefore, it is possible to bring out the device characteristics according to theory.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ本発明の詳細な説明するた
めの、時間とガス供給量の関係を示す図及びその条件に
より形成された超格子層を示す模式図であり、 第3図は、原料ガスの供給lを一定にした時の成長温度
の逆数(1/成成長度に一’ XIO’)と、成長速度
(人/分)との関係を示す図であり、第4図は成長温度
プログラムを示す図であり、第5A図及び第5B図は供
給ガスの切換えが急峻な場合の時間とガスの供給量の関
係を示す図及びその条件により形成されたML格子層を
示す模式第6A図及び第6B図は供給ガスの切換えが急
峻でない場合の時間とガスの供給量の関係を示す図及び
その条件により形成された超格子層を示す図である。 第1rA 第2図 1/成成長度 (K−’)X10’ 第3図
1 and 2 are diagrams showing the relationship between time and gas supply amount, and a schematic diagram showing a superlattice layer formed under the conditions, respectively, for detailed explanation of the present invention, and FIG. , is a diagram showing the relationship between the reciprocal of the growth temperature (1/growth rate 1' FIG. 5A and FIG. 5B are diagrams showing the relationship between time and gas supply amount when the supply gas is abruptly switched, and a schematic diagram showing the ML lattice layer formed under the conditions. FIGS. 6A and 6B are diagrams showing the relationship between time and gas supply amount when the supply gas is not abruptly switched, and diagrams showing the superlattice layer formed under the conditions. 1st rA Figure 2 1/ Growth rate (K-')X10' Figure 3

Claims (1)

【特許請求の範囲】 1、有機金属の熱分解を用いた気相成長法を用いて、基
板上に複数の異なる種類の半導体層からなる超格子を製
造する方法において、 前記複数の異なる種類の半導体の各々の成長温度を、各
々の反応律速過程内の温度に設定することを特徴とする
超格子の製造方法。
[Claims] 1. A method for manufacturing a superlattice consisting of a plurality of different types of semiconductor layers on a substrate using a vapor phase growth method using organic metal thermal decomposition, comprising the steps of: A method for manufacturing a superlattice, characterized in that the growth temperature of each semiconductor is set to a temperature within the rate-limiting process of each reaction.
JP5495188A 1988-03-10 1988-03-10 Manufacture of superlattice Pending JPH01230223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5495188A JPH01230223A (en) 1988-03-10 1988-03-10 Manufacture of superlattice

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5495188A JPH01230223A (en) 1988-03-10 1988-03-10 Manufacture of superlattice

Publications (1)

Publication Number Publication Date
JPH01230223A true JPH01230223A (en) 1989-09-13

Family

ID=12984974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5495188A Pending JPH01230223A (en) 1988-03-10 1988-03-10 Manufacture of superlattice

Country Status (1)

Country Link
JP (1) JPH01230223A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61275195A (en) * 1985-05-29 1986-12-05 Nippon Telegr & Teleph Corp <Ntt> Method and device for forming compound semiconductor thin film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61275195A (en) * 1985-05-29 1986-12-05 Nippon Telegr & Teleph Corp <Ntt> Method and device for forming compound semiconductor thin film

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