JPH0122941B2 - - Google Patents

Info

Publication number
JPH0122941B2
JPH0122941B2 JP16016281A JP16016281A JPH0122941B2 JP H0122941 B2 JPH0122941 B2 JP H0122941B2 JP 16016281 A JP16016281 A JP 16016281A JP 16016281 A JP16016281 A JP 16016281A JP H0122941 B2 JPH0122941 B2 JP H0122941B2
Authority
JP
Japan
Prior art keywords
data
byte
word
input
order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16016281A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5862723A (ja
Inventor
Isamu Yasui
Etsuo Masuda
Tomiji Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP16016281A priority Critical patent/JPS5862723A/ja
Publication of JPS5862723A publication Critical patent/JPS5862723A/ja
Publication of JPH0122941B2 publication Critical patent/JPH0122941B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP16016281A 1981-10-09 1981-10-09 デ−タ転送制御装置 Granted JPS5862723A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16016281A JPS5862723A (ja) 1981-10-09 1981-10-09 デ−タ転送制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16016281A JPS5862723A (ja) 1981-10-09 1981-10-09 デ−タ転送制御装置

Publications (2)

Publication Number Publication Date
JPS5862723A JPS5862723A (ja) 1983-04-14
JPH0122941B2 true JPH0122941B2 (enrdf_load_stackoverflow) 1989-04-28

Family

ID=15709198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16016281A Granted JPS5862723A (ja) 1981-10-09 1981-10-09 デ−タ転送制御装置

Country Status (1)

Country Link
JP (1) JPS5862723A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6210756A (ja) * 1985-07-09 1987-01-19 Fujitsu Ltd 複数プロセツサ間の通信方式

Also Published As

Publication number Publication date
JPS5862723A (ja) 1983-04-14

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